2007-07-16 Sandra Loosemore <sandra@codesourcery.com>
+ David Ung <davidu@mips.com>
+
+ * config/mips/mips.h (TUNE_24K): Define.
+ (TUNE_MACC_CHAINS): Add TUNE_24K.
+ * config/mips/mips.md: (*mul_acc_si, *mul_sub_si): Change type to
+ imadd.
+ * config/mips/74k.md (r74k_int_mult): Split madd/msub to ..
+ (r74k_int_madd): .. this new reservation.
+ (define_bypass): Fixed bypasses for r74k_int_madd to use
+ mips_linked_madd_p.
+ * config/mips/24k.md (define_bypass): Define new
+ r24k_int_mul3->r24k_int_madd bypass using mips_linked_madd_p.
+
+2007-07-16 Sandra Loosemore <sandra@codesourcery.com>
Nigel Stephens <nigel@mips.com>
* config/mips/mips.md: Include 20kc.md.
(define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!store_data_bypass_p")
(define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch")
+;; mul3->madd/msub : 1 cycle
+(define_bypass 1 "r24k_int_mul3" "r24k_int_madd" "mips_linked_madd_p")
+
;; mfhilo->next use : 5 cycles (default)
;; mfhilo->l/s base : 6 cycles
;; mfhilo->prefetch : 6 cycles
"r74k_agen*2")
;; MDU: fully pipelined multiplier
-;; mult, madd, msub - delivers result to hi/lo in 4 cycle (pipelined)
+;; mult - delivers result to hi/lo in 4 cycle (pipelined)
(define_insn_reservation "r74k_int_mult" 4
(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
- (eq_attr "type" "imul,imadd"))
+ (eq_attr "type" "imul"))
+ "r74k_alu+r74k_mul")
+
+;; madd, msub - delivers result to hi/lo in 4 cycle (pipelined)
+(define_insn_reservation "r74k_int_madd" 4
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
+ (eq_attr "type" "imadd"))
"r74k_alu+r74k_mul")
;; mul - delivers result to general register in 7 cycles
(define_bypass 5 "r74k_int_cmove" "r74k_int_load")
(define_bypass 5 "r74k_int_cmove" "r74k_int_store" "!store_data_bypass_p")
-;; mult/madd->int_mfhilo : 4 cycles (default)
-;; mult/madd->mult/madd : 1 cycles
-(define_bypass 1 "r74k_int_mult" "r74k_int_mult")
+;; mult/madd/msub->int_mfhilo : 4 cycles (default)
+;; mult->madd/msub : 1 cycles
+;; madd/msub->madd/msub : 1 cycles
+(define_bypass 1 "r74k_int_mult,r74k_int_mul3" "r74k_int_madd"
+ "mips_linked_madd_p")
+(define_bypass 1 "r74k_int_madd" "r74k_int_madd"
+ "mips_linked_madd_p")
;; --------------------------------------------------------------
;; Floating Point Instructions
#define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
#define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
|| mips_tune == PROCESSOR_SB1A)
+#define TUNE_24K (mips_tune == PROCESSOR_24KC \
+ || mips_tune == PROCESSOR_24KF2_1 \
+ || mips_tune == PROCESSOR_24KF1_1)
#define TUNE_74K (mips_tune == PROCESSOR_74KC \
|| mips_tune == PROCESSOR_74KF2_1 \
|| mips_tune == PROCESSOR_74KF1_1 \
than others, so this macro is defined on an opt-in basis. */
#define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
|| TUNE_MIPS4120 \
- || TUNE_MIPS4130)
+ || TUNE_MIPS4130 \
+ || TUNE_24K)
#define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
#define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
return "#";
return madd[which_alternative];
}
- [(set_attr "type" "imadd,imadd,multi")
+ [(set_attr "type" "imadd")
(set_attr "mode" "SI")
(set_attr "length" "4,4,8")])
msub\t%2,%3
#
#"
- [(set_attr "type" "imadd,multi,multi")
+ [(set_attr "type" "imadd")
(set_attr "mode" "SI")
(set_attr "length" "4,8,8")])
+2007-07-16 Sandra Loosemore <sandra@codesourcery.com>
+ David Ung <davidu@mips.com>
+
+ * gcc.target/mips/mips-sched-madd.c: New test case.
+
2007-07-15 Jerry DeLisle <jvdelisle@gcc.gnu.org>
PR libfortran/32611
--- /dev/null
+/* Test for case where another independent multiply insn may interfere
+ with a macc chain. */
+/* { dg-do compile } */
+/* { dg-mips-options "-Os -march=24kf -mno-mips16" } */
+
+int foo (int a, int b, int c, int d, int e, int f, int g)
+{
+ int temp;
+ int acc;
+
+ acc = a * b;
+ temp = a * c;
+ acc = d * e + acc;
+ acc = f * g + acc;
+ return acc > temp ? acc : temp;
+}
+
+/* { dg-final { scan-assembler "\tmult\t" } } */
+/* { dg-final { scan-assembler "\tmadd\t" } } */