spi-cadence-quadspi:use reset framwork to reset qspi

use reset framwork to reset qspi

Signed-off-by: ziv.xu <ziv.xu@starfive.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 9ff8701..5a3b7c6 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -343,7 +343,6 @@
                        resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
                                 <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
                                 <&rstgen RSTN_U0_CDNS_QSPI_REF>;
-                       resets-names = "rst_apb", "rst_ahb", "rst_ref";
                        cdns,fifo-depth = <256>;
                        cdns,fifo-width = <4>;
                        cdns,trigger-address = <0x0>;

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 9be48b1..352a88c 100644 (file)
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -72,6 +72,8 @@ struct cqspi_st {
        struct clk              *clks[CLK_QSPI_NUM];
        unsigned int            sclk;
 
+       struct reset_control *qspi_rst;
+
        void __iomem            *iobase;
        void __iomem            *ahb_base;
        resource_size_t         ahb_size;
@@ -1027,6 +1029,7 @@ static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
        writel(reg, reg_base + CQSPI_REG_CONFIG);
 }
 
+
 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
                                   const bool bypass,
                                   const unsigned int delay)
@@ -1251,10 +1254,8 @@ static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
        struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master);
 
        if (op->cmd.opcode == SPINOR_OP_RDCR) {
-               void __iomem    *reset_res;
-
-               reset_res = ioremap(STARFIVE_RESET_REG_BASE_ADDR, 0x300);
-               writel(0X7E7FE00, reset_res + QSPI_RESET_REG_OFFSET);
+               reset_control_assert(cqspi->qspi_rst);
+               reset_control_deassert(cqspi->qspi_rst);
        }
        ret = cqspi_mem_process(mem, op);
 
@@ -1527,13 +1528,11 @@ disable_apb_clk:
 static int cqspi_probe(struct platform_device *pdev)
 {
        const struct cqspi_driver_platdata *ddata;
-       struct reset_control *rst_apb, *rst_ahb, *rst_ref;
        struct device *dev = &pdev->dev;
        struct spi_master *master;
        struct resource *res_ahb;
        struct cqspi_st *cqspi;
        struct resource *res;
-       void __iomem    *reset_res;
        int ret;
        int irq;
 
@@ -1603,33 +1602,15 @@ static int cqspi_probe(struct platform_device *pdev)
                goto probe_clk_failed;
 
        /* Obtain QSPI reset control */
-       rst_apb = devm_reset_control_get_optional_exclusive(dev, "rst_apb");
-       if (IS_ERR(rst_apb)) {
-               ret = PTR_ERR(rst_apb);
-               dev_err(dev, "Cannot get APB reset.\n");
-               goto probe_reset_failed;
-       }
-
-       rst_ahb = devm_reset_control_get_optional_exclusive(dev, "rst_ahb");
-       if (IS_ERR(rst_ahb)) {
-               ret = PTR_ERR(rst_ahb);
-               dev_err(dev, "Cannot get QSPI ahb reset.\n");
+       cqspi->qspi_rst = devm_reset_control_array_get_exclusive(&pdev->dev);
+       if (IS_ERR(cqspi->qspi_rst)) {
+               ret = PTR_ERR(cqspi->qspi_rst);
+               dev_err(dev, "Cannot get QSPI reset.\n");
                goto probe_reset_failed;
        }
 
-       rst_ref = devm_reset_control_get_optional_exclusive(dev, "rst_ref");
-       if (IS_ERR(rst_ref)) {
-               ret = PTR_ERR(rst_ref);
-               dev_err(dev, "Cannot get QSPI ref reset.\n");
-               goto probe_reset_failed;
-       }
-
-       /*
-        *  Due to the problem of reset in the current QSPI driver
-        *  we temporarily reset QSPI by writing register
-        */
-       reset_res = ioremap(STARFIVE_RESET_REG_BASE_ADDR, 0x300);
-       writel(0X7E7FE00, reset_res + QSPI_RESET_REG_OFFSET);
+       reset_control_assert(cqspi->qspi_rst);
+       reset_control_deassert(cqspi->qspi_rst);
 
        cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clks[CLK_QSPI_REF]);