--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 Isp Clock Driver
+ *
+ * Copyright (C) 2022 Xingyu Wu <xingyu.wu@starfivetech.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+#include <linux/reset.h>
+#include <linux/reset-controller.h>
+#include <dt-bindings/clock/starfive-jh7110-isp.h>
+#include <soc/starfive/jh7110_pmu.h>
+
+#include "clk-starfive-jh7110.h"
+
+static const struct jh7110_clk_data jh7110_clk_isp_data[] __initconst = {
+ //syscon
+ JH7110__DIV(JH7110_DOM4_APB_FUNC, "dom4_apb_func",
+ 15, JH7110_ISP_TOP_CLK_ISP_AXI_CLKGEN),
+ //crg
+ JH7110__DIV(JH7110_MIPI_RX0_PXL, "mipi_rx0_pxl",
+ 8, JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN),
+ JH7110__INV(JH7110_DVP_INV, "dvp_inv", JH7110_ISP_TOP_CLK_DVP_CLKGEN),
+ //vin
+ JH7110__DIV(JH7110_U0_M31DPHY_CFGCLK_IN, "u0_m31dphy_cfgclk_in",
+ 16, JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN),
+ JH7110__DIV(JH7110_U0_M31DPHY_REFCLK_IN, "u0_m31dphy_refclk_in",
+ 16, JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN),
+ JH7110__DIV(JH7110_U0_M31DPHY_TXCLKESC_LAN0, "u0_m31dphy_txclkesc_lan0",
+ 60, JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN),
+ JH7110_GATE(JH7110_U0_VIN_PCLK, "u0_vin_pclk",
+ GATE_FLAG_NORMAL, JH7110_DOM4_APB),
+ JH7110__DIV(JH7110_U0_VIN_SYS_CLK, "u0_vin_sys_clk",
+ 8, JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN),
+ JH7110_GATE(JH7110_U0_VIN_PIXEL_CLK_IF0, "u0_vin_pixel_clk_if0",
+ GATE_FLAG_NORMAL, JH7110_MIPI_RX0_PXL),
+ JH7110_GATE(JH7110_U0_VIN_PIXEL_CLK_IF1, "u0_vin_pixel_clk_if1",
+ GATE_FLAG_NORMAL, JH7110_MIPI_RX0_PXL),
+ JH7110_GATE(JH7110_U0_VIN_PIXEL_CLK_IF2, "u0_vin_pixel_clk_if2",
+ GATE_FLAG_NORMAL, JH7110_MIPI_RX0_PXL),
+ JH7110_GATE(JH7110_U0_VIN_PIXEL_CLK_IF3, "u0_vin_pixel_clk_if3",
+ GATE_FLAG_NORMAL, JH7110_MIPI_RX0_PXL),
+ JH7110__MUX(JH7110_U0_VIN_CLK_P_AXIWR, "u0_vin_clk_p_axiwr",
+ PARENT_NUMS_2,
+ JH7110_MIPI_RX0_PXL,
+ JH7110_DVP_INV),
+ //ispv2_top_wrapper
+ JH7110_GMUX(JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C,
+ "u0_ispv2_top_wrapper_clk_c",
+ GATE_FLAG_NORMAL, PARENT_NUMS_2,
+ JH7110_MIPI_RX0_PXL,
+ JH7110_DVP_INV),
+};
+
+static struct clk_hw *jh7110_isp_clk_get(struct of_phandle_args *clkspec,
+ void *data)
+{
+ struct jh7110_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < JH7110_CLK_ISP_REG_END)
+ return &priv->reg[idx].hw;
+
+ if (idx < JH7110_CLK_ISP_END)
+ return priv->pll[PLL_OFI(idx)];
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int __init clk_starfive_jh7110_isp_probe(struct platform_device *pdev)
+{
+ struct jh7110_clk_priv *priv;
+ unsigned int idx;
+ struct clk *clk_isp_2x;
+ struct clk *clk_isp_axi;
+ struct reset_control *rst_isp_n;
+ struct reset_control *rst_isp_axi;
+ int ret = 0;
+
+ priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg,
+ JH7110_CLK_ISP_END), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->dev = &pdev->dev;
+ priv->isp_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->isp_base))
+ return PTR_ERR(priv->isp_base);
+
+ starfive_power_domain_set(POWER_DOMAIN_ISP, 1);
+
+ clk_isp_2x = devm_clk_get(priv->dev,
+ "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x");
+ if (!IS_ERR(clk_isp_2x)){
+ ret = clk_prepare_enable(clk_isp_2x);
+ if(ret){
+ dev_err(priv->dev, "clk_isp_2x enable failed\n");
+ return ret;
+ }
+ }else{
+ dev_err(priv->dev, "clk_isp_2x get failed\n");
+ return PTR_ERR(clk_isp_2x);
+ }
+
+ clk_isp_axi = devm_clk_get(priv->dev,
+ "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi");
+ if (!IS_ERR(clk_isp_axi)){
+ ret = clk_prepare_enable(clk_isp_axi);
+ if(ret){
+ dev_err(priv->dev, "clk_isp_axi enable failed\n");
+ return ret;
+ }
+ }else{
+ dev_err(priv->dev, "clk_isp_axi get failed\n");
+ return PTR_ERR(clk_isp_axi);
+ }
+
+ rst_isp_n = devm_reset_control_get_exclusive(
+ priv->dev, "rst_isp_top_n");
+ if (!IS_ERR(rst_isp_n)) {
+ ret = reset_control_deassert(rst_isp_n);
+ if(ret){
+ dev_err(priv->dev, "rst_isp_n deassert failed.\n");
+ return ret;
+ }
+ }else{
+ dev_err(priv->dev, "rst_isp_n get failed.\n");
+ return PTR_ERR(rst_isp_n);
+ }
+
+ rst_isp_axi = devm_reset_control_get_exclusive(
+ priv->dev, "rst_isp_top_axi");
+ if (!IS_ERR(rst_isp_axi)) {
+ ret = reset_control_deassert(rst_isp_axi);
+ if(ret){
+ dev_err(priv->dev, "rst_isp_axi deassert failed.\n");
+ return ret;
+ }
+ }else{
+ dev_err(priv->dev, "rst_isp_axi get failed.\n");
+ return PTR_ERR(rst_isp_axi);
+ }
+
+ priv->pll[PLL_OFI(JH7110_U3_PCLK_MUX_FUNC_PCLK)] =
+ devm_clk_hw_register_fixed_factor(
+ priv->dev, "u3_pclk_mux_func_pclk",
+ "dom4_apb_func", 0, 1, 1);
+ priv->pll[PLL_OFI(JH7110_U3_PCLK_MUX_BIST_PCLK)] =
+ devm_clk_hw_register_fixed_factor(
+ priv->dev, "u3_pclk_mux_bist_pclk",
+ "u0_dom_isp_top_clk_dom_isp_top_clk_bist_apb", 0, 1, 1);
+ priv->pll[PLL_OFI(JH7110_DOM4_APB)] =
+ devm_clk_hw_register_fixed_factor(priv->dev, "dom4_apb",
+ "u3_pclk_mux_pclk", 0, 1, 1);
+ //vin
+ priv->pll[PLL_OFI(JH7110_U0_VIN_PCLK_FREE)] =
+ devm_clk_hw_register_fixed_factor(
+ priv->dev, "u0_vin_pclk_free",
+ "dom4_apb", 0, 1, 1);
+ priv->pll[PLL_OFI(JH7110_U0_VIN_CLK_P_AXIRD)] =
+ devm_clk_hw_register_fixed_factor(
+ priv->dev, "u0_vin_clk_p_axird",
+ "mipi_rx0_pxl", 0, 1, 1);
+ priv->pll[PLL_OFI(JH7110_U0_VIN_ACLK)] =
+ devm_clk_hw_register_fixed_factor(
+ priv->dev, "u0_vin_ACLK",
+ "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi", 0, 1, 1);
+ priv->pll[PLL_OFI(JH7110_U0_ISPV2_TOP_WRAPPER_CLK_ISP_AXI_IN)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_ispv2_top_wrapper_clk_isp_axi_in",
+ "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi", 0, 1, 1);
+ priv->pll[PLL_OFI(JH7110_U0_ISPV2_TOP_WRAPPER_CLK_ISP_X2)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_ispv2_top_wrapper_clk_isp_x2",
+ "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
+ 0, 1, 1);
+ //wrapper
+ priv->pll[PLL_OFI(JH7110_U0_ISPV2_TOP_WRAPPER_CLK_ISP)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_ispv2_top_wrapper_clk_isp",
+ "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi", 0, 1, 1);
+ priv->pll[PLL_OFI(JH7110_U0_ISPV2_TOP_WRAPPER_CLK_P)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_ispv2_top_wrapper_clk_p",
+ "mipi_rx0_pxl", 0, 1, 1);
+ priv->pll[PLL_OFI(JH7110_U0_CRG_PCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_crg_pclk", "dom4_apb", 0, 1, 1);
+ priv->pll[PLL_OFI(JH7110_U0_SYSCON_PCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_syscon_pclk", "dom4_apb", 0, 1, 1);
+ priv->pll[PLL_OFI(JH7110_U0_M31DPHY_APBCFG_PCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_m31dphy_apbcfg_pclk", "dom4_apb", 0, 1, 1);
+ priv->pll[PLL_OFI(JH7110_U0_AXI2APB_BRIDGE_CLK_DOM4_APB)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_axi2apb_bridge_clk_dom4_apb", "dom4_apb", 0, 1, 1);
+ priv->pll[PLL_OFI(JH7110_U0_AXI2APB_BRIDGE_ISP_AXI4SLV_CLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_axi2apb_bridge_isp_axi4slv_clk",
+ "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi", 0, 1, 1);
+ priv->pll[PLL_OFI(JH7110_U3_PCLK_MUX_PCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u3_pclk_mux_pclk", "u3_pclk_mux_func_pclk", 0, 1, 1);
+
+ for (idx = 0; idx < JH7110_CLK_ISP_REG_END; idx++) {
+ u32 max = jh7110_clk_isp_data[idx].max;
+ struct clk_parent_data parents[2] = {};
+ struct clk_init_data init = {
+ .name = jh7110_clk_isp_data[idx].name,
+ .ops = starfive_jh7110_clk_ops(max),
+ .parent_data = parents,
+ .num_parents = ((max & JH7110_CLK_MUX_MASK) \
+ >> JH7110_CLK_MUX_SHIFT) + 1,
+ .flags = jh7110_clk_isp_data[idx].flags,
+ };
+ struct jh7110_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh7110_clk_isp_data[idx].parents[i];
+
+ if (pidx < JH7110_CLK_ISP_REG_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx < JH7110_CLK_ISP_END)
+ parents[i].hw = priv->pll[PLL_OFI(pidx)];
+ else if (pidx == JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN)
+ parents[i].fw_name = \
+ "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x";
+ else if (pidx == JH7110_ISP_TOP_CLK_ISP_AXI_CLKGEN)
+ parents[i].fw_name = \
+ "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi";
+ else if (pidx == JH7110_ISP_TOP_CLK_BIST_APB_CLKGEN)
+ parents[i].fw_name = \
+ "u0_dom_isp_top_clk_dom_isp_top_clk_bist_apb";
+ else if (pidx == JH7110_ISP_TOP_CLK_DVP_CLKGEN)
+ parents[i].fw_name = \
+ "u0_dom_isp_top_clk_dom_isp_top_clk_dvp";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & JH7110_CLK_DIV_MASK;
+ clk->reg_flags = JH7110_CLK_ISP_FLAG;
+
+ ret = devm_clk_hw_register(priv->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(priv->dev, jh7110_isp_clk_get, priv);
+ if (ret)
+ return ret;
+
+ dev_info(&pdev->dev,"starfive JH7110 clk_isp init successfully.");
+ return 0;
+}
+
+static const struct of_device_id clk_starfive_jh7110_isp_match[] = {
+ {.compatible = "starfive,jh7110-clk-isp" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_starfive_jh7110_isp_driver = {
+ .probe = clk_starfive_jh7110_isp_probe,
+ .driver = {
+ .name = "clk-starfive-jh7110-isp",
+ .of_match_table = clk_starfive_jh7110_isp_match,
+ },
+};
+module_platform_driver(clk_starfive_jh7110_isp_driver);
+
+MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JH7110 isp clock driver");
+MODULE_LICENSE("GPL");
static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
/*root*/
- JH7110__MUX(JH7110_CPU_ROOT, "cpu_root", 2,
+ JH7110__MUX(JH7110_CPU_ROOT, "cpu_root", PARENT_NUMS_2,
JH7110_OSC,
JH7110_PLL0_OUT),
JH7110__DIV(JH7110_CPU_CORE, "cpu_core", 7, JH7110_CPU_ROOT),
JH7110__DIV(JH7110_CPU_BUS, "cpu_bus", 2, JH7110_CPU_CORE),
- JH7110__MUX(JH7110_GPU_ROOT, "gpu_root", 2,
+ JH7110__MUX(JH7110_GPU_ROOT, "gpu_root", PARENT_NUMS_2,
JH7110_PLL2_OUT,
JH7110_PLL1_OUT),
- JH7110_MDIV(JH7110_PERH_ROOT, "perh_root", 2, 2,
+ JH7110_MDIV(JH7110_PERH_ROOT, "perh_root", 2, PARENT_NUMS_2,
JH7110_PLL0_OUT,
JH7110_PLL2_OUT),
- JH7110__MUX(JH7110_BUS_ROOT, "bus_root", 2,
+ JH7110__MUX(JH7110_BUS_ROOT, "bus_root", PARENT_NUMS_2,
JH7110_OSC,
JH7110_PLL2_OUT),
JH7110__DIV(JH7110_NOCSTG_BUS, "nocstg_bus", 3, JH7110_BUS_ROOT),
JH7110__DIV(JH7110_AXI_CFG0, "axi_cfg0", 3, JH7110_BUS_ROOT),
JH7110__DIV(JH7110_STG_AXIAHB, "stg_axiahb", 2, JH7110_AXI_CFG0),
- JH7110_GATE(JH7110_AHB0, "ahb0", 0, JH7110_STG_AXIAHB),
- JH7110_GATE(JH7110_AHB1, "ahb1", 0, JH7110_STG_AXIAHB),
+ JH7110_GATE(JH7110_AHB0, "ahb0", GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
+ JH7110_GATE(JH7110_AHB1, "ahb1", GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
JH7110__DIV(JH7110_APB_BUS_FUNC, "apb_bus_func",
8, JH7110_STG_AXIAHB),
- JH7110_GATE(JH7110_APB0, "apb0", 0, JH7110_APB_BUS),
+ JH7110_GATE(JH7110_APB0, "apb0", GATE_FLAG_NORMAL, JH7110_APB_BUS),
JH7110__DIV(JH7110_PLL0_DIV2, "pll0_div2", 2, JH7110_PLL0_OUT),
JH7110__DIV(JH7110_PLL1_DIV2, "pll1_div2", 2, JH7110_PLL1_OUT),
JH7110__DIV(JH7110_PLL2_DIV2, "pll2_div2", 2, JH7110_PLL2_OUT),
JH7110__DIV(JH7110_AUDIO_ROOT, "audio_root", 8, JH7110_PLL2_OUT),
JH7110__DIV(JH7110_MCLK_INNER, "mclk_inner", 64, JH7110_AUDIO_ROOT),
- JH7110__MUX(JH7110_MCLK, "mclk", 2,
+ JH7110__MUX(JH7110_MCLK, "mclk", PARENT_NUMS_2,
JH7110_MCLK_INNER,
JH7110_MCLK_EXT),
- JH7110_GATE(JH7110_MCLK_OUT, "mclk_out", 0, JH7110_MCLK_INNER),
- JH7110_MDIV(JH7110_ISP_2X, "isp_2x", 8, 2,
+ JH7110_GATE(JH7110_MCLK_OUT, "mclk_out", GATE_FLAG_NORMAL,
+ JH7110_MCLK_INNER),
+ JH7110_MDIV(JH7110_ISP_2X, "isp_2x", 8, PARENT_NUMS_2,
JH7110_PLL2_OUT,
JH7110_PLL1_OUT),
JH7110__DIV(JH7110_ISP_AXI, "isp_axi", 4, JH7110_ISP_2X),
- JH7110_GDIV(JH7110_GCLK0, "gclk0", 0, 62, JH7110_PLL0_DIV2),
- JH7110_GDIV(JH7110_GCLK1, "gclk1", 0, 62, JH7110_PLL1_DIV2),
- JH7110_GDIV(JH7110_GCLK2, "gclk2", 0, 62, JH7110_PLL2_DIV2),
+ JH7110_GDIV(JH7110_GCLK0, "gclk0", GATE_FLAG_NORMAL,
+ 62, JH7110_PLL0_DIV2),
+ JH7110_GDIV(JH7110_GCLK1, "gclk1", GATE_FLAG_NORMAL,
+ 62, JH7110_PLL1_DIV2),
+ JH7110_GDIV(JH7110_GCLK2, "gclk2", GATE_FLAG_NORMAL,
+ 62, JH7110_PLL2_DIV2),
/*u0_u7mc_sft7110*/
JH7110_GATE(JH7110_U7_CORE_CLK, "u0_u7mc_sft7110_core_clk",
- 0, JH7110_CPU_CORE),
+ GATE_FLAG_NORMAL, JH7110_CPU_CORE),
JH7110_GATE(JH7110_U7_CORE_CLK1, "u0_u7mc_sft7110_core_clk1",
- 0, JH7110_CPU_CORE),
+ GATE_FLAG_NORMAL, JH7110_CPU_CORE),
JH7110_GATE(JH7110_U7_CORE_CLK2, "u0_u7mc_sft7110_core_clk2",
- 0, JH7110_CPU_CORE),
+ GATE_FLAG_NORMAL, JH7110_CPU_CORE),
JH7110_GATE(JH7110_U7_CORE_CLK3, "u0_u7mc_sft7110_core_clk3",
- 0, JH7110_CPU_CORE),
+ GATE_FLAG_NORMAL, JH7110_CPU_CORE),
JH7110_GATE(JH7110_U7_CORE_CLK4, "u0_u7mc_sft7110_core_clk4",
- 0, JH7110_CPU_CORE),
+ GATE_FLAG_NORMAL, JH7110_CPU_CORE),
JH7110_GATE(JH7110_U7_DEBUG_CLK, "u0_u7mc_sft7110_debug_clk",
- 0, JH7110_CPU_BUS),
+ GATE_FLAG_NORMAL, JH7110_CPU_BUS),
JH7110__DIV(JH7110_U7_RTC_TOGGLE, "u0_u7mc_sft7110_rtc_toggle",
6, JH7110_OSC),
JH7110_GATE(JH7110_U7_TRACE_CLK0, "u0_u7mc_sft7110_trace_clk0",
- 0, JH7110_CPU_CORE),
+ GATE_FLAG_NORMAL, JH7110_CPU_CORE),
JH7110_GATE(JH7110_U7_TRACE_CLK1, "u0_u7mc_sft7110_trace_clk1",
- 0, JH7110_CPU_CORE),
+ GATE_FLAG_NORMAL, JH7110_CPU_CORE),
JH7110_GATE(JH7110_U7_TRACE_CLK2, "u0_u7mc_sft7110_trace_clk2",
- 0, JH7110_CPU_CORE),
+ GATE_FLAG_NORMAL, JH7110_CPU_CORE),
JH7110_GATE(JH7110_U7_TRACE_CLK3, "u0_u7mc_sft7110_trace_clk3",
- 0, JH7110_CPU_CORE),
+ GATE_FLAG_NORMAL, JH7110_CPU_CORE),
JH7110_GATE(JH7110_U7_TRACE_CLK4, "u0_u7mc_sft7110_trace_clk4",
- 0, JH7110_CPU_CORE),
+ GATE_FLAG_NORMAL, JH7110_CPU_CORE),
JH7110_GATE(JH7110_U7_TRACE_COM_CLK, "u0_u7mc_sft7110_trace_com_clk",
- 0, JH7110_CPU_BUS),
+ GATE_FLAG_NORMAL, JH7110_CPU_BUS),
//NOC
JH7110_GATE(JH7110_NOC_BUS_CLK_CPU_AXI,
"u0_sft7110_noc_bus_clk_cpu_axi",
- 0, JH7110_CPU_BUS),
+ GATE_FLAG_NORMAL, JH7110_CPU_BUS),
JH7110_GATE(JH7110_NOC_BUS_CLK_AXICFG0_AXI,
"u0_sft7110_noc_bus_clk_axicfg0_axi",
- 0, JH7110_AXI_CFG0),
+ GATE_FLAG_NORMAL, JH7110_AXI_CFG0),
//DDRC
JH7110__DIV(JH7110_OSC_DIV2, "osc_div2", 2, JH7110_OSC),
JH7110__DIV(JH7110_PLL1_DIV4, "pll1_div4", 2, JH7110_PLL1_DIV2),
JH7110__DIV(JH7110_PLL1_DIV8, "pll1_div8", 2, JH7110_PLL1_DIV4),
- JH7110__MUX(JH7110_DDR_BUS, "ddr_bus", 4,
+ JH7110__MUX(JH7110_DDR_BUS, "ddr_bus", PARENT_NUMS_4,
JH7110_OSC_DIV2,
JH7110_PLL1_DIV2,
JH7110_PLL1_DIV4,
JH7110_PLL1_DIV8),
JH7110_GATE(JH7110_DDR_CLK_AXI, "u0_ddr_sft7110_clk_axi",
- 0, JH7110_DDR_BUS),
+ GATE_FLAG_NORMAL, JH7110_DDR_BUS),
//GPU
JH7110__DIV(JH7110_GPU_CORE, "gpu_core", 7, JH7110_GPU_ROOT),
JH7110_GATE(JH7110_GPU_CORE_CLK, "u0_img_gpu_core_clk",
- 0, JH7110_GPU_CORE),
+ GATE_FLAG_NORMAL, JH7110_GPU_CORE),
JH7110_GATE(JH7110_GPU_SYS_CLK, "u0_img_gpu_sys_clk",
- 0, JH7110_AXI_CFG1),
+ GATE_FLAG_NORMAL, JH7110_AXI_CFG1),
JH7110_GATE(JH7110_GPU_CLK_APB, "u0_img_gpu_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
JH7110_GDIV(JH7110_GPU_RTC_TOGGLE, "u0_img_gpu_rtc_toggle",
- 0, 12, JH7110_OSC),
+ GATE_FLAG_NORMAL, 12, JH7110_OSC),
JH7110_GATE(JH7110_NOC_BUS_CLK_GPU_AXI,
"u0_sft7110_noc_bus_clk_gpu_axi",
- 0, JH7110_GPU_CORE),
+ GATE_FLAG_NORMAL, JH7110_GPU_CORE),
//ISP
JH7110_GATE(JH7110_ISP_TOP_CLK_ISPCORE_2X,
"u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
- 0, JH7110_ISP_2X),
+ GATE_FLAG_NORMAL, JH7110_ISP_2X),
JH7110_GATE(JH7110_ISP_TOP_CLK_ISP_AXI,
"u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
- 0, JH7110_ISP_AXI),
+ GATE_FLAG_NORMAL, JH7110_ISP_AXI),
JH7110_GATE(JH7110_NOC_BUS_CLK_ISP_AXI,
"u0_sft7110_noc_bus_clk_isp_axi",
- 0, JH7110_ISP_AXI),
+ GATE_FLAG_NORMAL, JH7110_ISP_AXI),
//HIFI4
JH7110__DIV(JH7110_HIFI4_CORE, "hifi4_core", 15, JH7110_BUS_ROOT),
JH7110__DIV(JH7110_HIFI4_AXI, "hifi4_axi", 2, JH7110_HIFI4_CORE),
//AXICFG1_DEC
JH7110_GATE(JH7110_AXI_CFG1_DEC_CLK_MAIN, "u0_axi_cfg1_dec_clk_main",
- 0, JH7110_AXI_CFG1),
+ GATE_FLAG_NORMAL, JH7110_AXI_CFG1),
JH7110_GATE(JH7110_AXI_CFG1_DEC_CLK_AHB, "u0_axi_cfg1_dec_clk_ahb",
- 0, JH7110_AHB0),
+ GATE_FLAG_NORMAL, JH7110_AHB0),
//VOUT
JH7110_GATE(JH7110_VOUT_SRC,
"u0_dom_vout_top_clk_dom_vout_top_clk_vout_src",
- 0, JH7110_VOUT_ROOT),
+ GATE_FLAG_NORMAL, JH7110_VOUT_ROOT),
JH7110__DIV(JH7110_VOUT_AXI, "vout_axi", 7, JH7110_VOUT_ROOT),
JH7110_GATE(JH7110_NOC_BUS_CLK_DISP_AXI,
"u0_sft7110_noc_bus_clk_disp_axi",
- 0, JH7110_VOUT_AXI),
+ GATE_FLAG_NORMAL, JH7110_VOUT_AXI),
JH7110_GATE(JH7110_VOUT_TOP_CLK_VOUT_AHB,
"u0_dom_vout_top_clk_dom_vout_top_clk_vout_ahb",
- 0, JH7110_AHB1),
+ GATE_FLAG_NORMAL, JH7110_AHB1),
JH7110_GATE(JH7110_VOUT_TOP_CLK_VOUT_AXI,
"u0_dom_vout_top_clk_dom_vout_top_clk_vout_axi",
- 0, JH7110_VOUT_AXI),
+ GATE_FLAG_NORMAL, JH7110_VOUT_AXI),
JH7110_GATE(JH7110_VOUT_TOP_CLK_HDMITX0_MCLK,
"u0_dom_vout_top_clk_dom_vout_top_clk_hdmitx0_mclk",
- 0, JH7110_MCLK),
+ GATE_FLAG_NORMAL, JH7110_MCLK),
JH7110__DIV(JH7110_VOUT_TOP_CLK_MIPIPHY_REF,
"u0_dom_vout_top_clk_dom_vout_top_clk_mipiphy_ref",
2, JH7110_OSC),
//JPEGC
JH7110__DIV(JH7110_JPEGC_AXI, "jpegc_axi", 16, JH7110_VENC_ROOT),
JH7110_GATE(JH7110_CODAJ12_CLK_AXI, "u0_CODAJ12_clk_axi",
- 0, JH7110_JPEGC_AXI),
+ GATE_FLAG_NORMAL, JH7110_JPEGC_AXI),
JH7110_GDIV(JH7110_CODAJ12_CLK_CORE, "u0_CODAJ12_clk_core",
- 0, 16, JH7110_VENC_ROOT),
+ GATE_FLAG_NORMAL, 16, JH7110_VENC_ROOT),
JH7110_GATE(JH7110_CODAJ12_CLK_APB, "u0_CODAJ12_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
//VDEC
JH7110__DIV(JH7110_VDEC_AXI, "vdec_axi", 7, JH7110_BUS_ROOT),
JH7110_GATE(JH7110_WAVE511_CLK_AXI, "u0_WAVE511_clk_axi",
- 0, JH7110_VDEC_AXI),
+ GATE_FLAG_NORMAL, JH7110_VDEC_AXI),
JH7110_GDIV(JH7110_WAVE511_CLK_BPU, "u0_WAVE511_clk_bpu",
- 0, 7, JH7110_BUS_ROOT),
+ GATE_FLAG_NORMAL, 7, JH7110_BUS_ROOT),
JH7110_GDIV(JH7110_WAVE511_CLK_VCE, "u0_WAVE511_clk_vce",
- 0, 7, JH7110_VDEC_ROOT),
+ GATE_FLAG_NORMAL, 7, JH7110_VDEC_ROOT),
JH7110_GATE(JH7110_WAVE511_CLK_APB, "u0_WAVE511_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
JH7110_GATE(JH7110_VDEC_JPG_ARB_JPGCLK, "u0_vdec_jpg_arb_jpgclk",
- 0, JH7110_JPEGC_AXI),
+ GATE_FLAG_NORMAL, JH7110_JPEGC_AXI),
JH7110_GATE(JH7110_VDEC_JPG_ARB_MAINCLK, "u0_vdec_jpg_arb_mainclk",
- 0, JH7110_VDEC_AXI),
+ GATE_FLAG_NORMAL, JH7110_VDEC_AXI),
JH7110_GATE(JH7110_NOC_BUS_CLK_VDEC_AXI,
"u0_sft7110_noc_bus_clk_vdec_axi",
- 0, JH7110_VDEC_AXI),
+ GATE_FLAG_NORMAL, JH7110_VDEC_AXI),
//VENC
JH7110__DIV(JH7110_VENC_AXI, "venc_axi", 15, JH7110_VENC_ROOT),
JH7110_GATE(JH7110_WAVE420L_CLK_AXI, "u0_wave420l_clk_axi",
- 0, JH7110_VENC_AXI),
+ GATE_FLAG_NORMAL, JH7110_VENC_AXI),
JH7110_GDIV(JH7110_WAVE420L_CLK_BPU, "u0_wave420l_clk_bpu",
- 0, 15, JH7110_VENC_ROOT),
+ GATE_FLAG_NORMAL, 15, JH7110_VENC_ROOT),
JH7110_GDIV(JH7110_WAVE420L_CLK_VCE, "u0_wave420l_clk_vce",
- 0, 15, JH7110_VENC_ROOT),
+ GATE_FLAG_NORMAL, 15, JH7110_VENC_ROOT),
JH7110_GATE(JH7110_WAVE420L_CLK_APB, "u0_wave420l_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
JH7110_GATE(JH7110_NOC_BUS_CLK_VENC_AXI,
"u0_sft7110_noc_bus_clk_venc_axi",
- 0, JH7110_VENC_AXI),
+ GATE_FLAG_NORMAL, JH7110_VENC_AXI),
//INTMEM
JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_MAIN_DIV,
"u0_axi_cfg0_dec_clk_main_div",
- 0, JH7110_AHB1),
+ GATE_FLAG_NORMAL, JH7110_AHB1),
JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_MAIN, "u0_axi_cfg0_dec_clk_main",
- 0, JH7110_AXI_CFG0),
+ GATE_FLAG_NORMAL, JH7110_AXI_CFG0),
JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_HIFI4, "u0_axi_cfg0_dec_clk_hifi4",
- 0, JH7110_HIFI4_AXI),
+ GATE_FLAG_NORMAL, JH7110_HIFI4_AXI),
JH7110_GATE(JH7110_AXIMEM2_128B_CLK_AXI, "u2_aximem_128b_clk_axi",
- 0, JH7110_AXI_CFG0),
+ GATE_FLAG_NORMAL, JH7110_AXI_CFG0),
//QSPI
JH7110_GATE(JH7110_QSPI_CLK_AHB, "u0_cdns_qspi_clk_ahb",
- 0, JH7110_AHB1),
+ GATE_FLAG_NORMAL, JH7110_AHB1),
JH7110_GATE(JH7110_QSPI_CLK_APB, "u0_cdns_qspi_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
JH7110__DIV(JH7110_QSPI_REF_SRC, "u0_cdns_qspi_ref_src",
16, JH7110_GMACUSB_ROOT),
- JH7110_GMUX(JH7110_QSPI_CLK_REF, "u0_cdns_qspi_clk_ref", 0, 2,
+ JH7110_GMUX(JH7110_QSPI_CLK_REF, "u0_cdns_qspi_clk_ref",
+ GATE_FLAG_NORMAL, PARENT_NUMS_2,
JH7110_OSC,
JH7110_QSPI_REF_SRC),
//SDIO
JH7110_GATE(JH7110_SDIO0_CLK_AHB, "u0_dw_sdio_clk_ahb",
- 0, JH7110_AHB0),
+ GATE_FLAG_NORMAL, JH7110_AHB0),
JH7110_GATE(JH7110_SDIO1_CLK_AHB, "u1_dw_sdio_clk_ahb",
- 0, JH7110_AHB0),
+ GATE_FLAG_NORMAL, JH7110_AHB0),
JH7110_GDIV(JH7110_SDIO0_CLK_SDCARD, "u0_dw_sdio_clk_sdcard",
- 0, 15, JH7110_AXI_CFG0),
+ GATE_FLAG_NORMAL, 15, JH7110_AXI_CFG0),
JH7110_GDIV(JH7110_SDIO1_CLK_SDCARD, "u1_dw_sdio_clk_sdcard",
- 0, 15, JH7110_AXI_CFG0),
+ GATE_FLAG_NORMAL, 15, JH7110_AXI_CFG0),
//STG
JH7110__DIV(JH7110_USB_125M, "usb_125m", 15, JH7110_GMACUSB_ROOT),
JH7110_GATE(JH7110_NOC_BUS_CLK_STG_AXI,
"u0_sft7110_noc_bus_clk_stg_axi",
- 0, JH7110_NOCSTG_BUS),
+ GATE_FLAG_NORMAL, JH7110_NOCSTG_BUS),
//GMAC1
JH7110_GATE(JH7110_GMAC5_CLK_AHB, "u1_dw_gmac5_axi64_clk_ahb",
- 0, JH7110_AHB0),
+ GATE_FLAG_NORMAL, JH7110_AHB0),
JH7110_GATE(JH7110_GMAC5_CLK_AXI, "u1_dw_gmac5_axi64_clk_axi",
- 0, JH7110_STG_AXIAHB),
+ GATE_FLAG_NORMAL, JH7110_STG_AXIAHB),
JH7110__DIV(JH7110_GMAC_SRC, "gmac_src", 7, JH7110_GMACUSB_ROOT),
JH7110__DIV(JH7110_GMAC1_GTXCLK, "gmac1_gtxclk",
15, JH7110_GMACUSB_ROOT),
JH7110__DIV(JH7110_GMAC1_RMII_RTX, "gmac1_rmii_rtx",
30, JH7110_GMAC1_RMII_REFIN),
JH7110_GDIV(JH7110_GMAC5_CLK_PTP, "u1_dw_gmac5_axi64_clk_ptp",
- 0, 31, JH7110_GMAC_SRC),
- JH7110__MUX(JH7110_GMAC5_CLK_RX, "u1_dw_gmac5_axi64_clk_rx", 2,
+ GATE_FLAG_NORMAL, 31, JH7110_GMAC_SRC),
+ JH7110__MUX(JH7110_GMAC5_CLK_RX, "u1_dw_gmac5_axi64_clk_rx",
+ PARENT_NUMS_2,
JH7110_GMAC1_RGMII_RXIN,
JH7110_GMAC1_RMII_RTX),
JH7110__INV(JH7110_GMAC5_CLK_RX_INV, "u1_dw_gmac5_axi64_clk_rx_inv",
JH7110_GMAC5_CLK_RX),
- JH7110_GMUX(JH7110_GMAC5_CLK_TX, "u1_dw_gmac5_axi64_clk_tx", 0, 2,
+ JH7110_GMUX(JH7110_GMAC5_CLK_TX, "u1_dw_gmac5_axi64_clk_tx",
+ GATE_FLAG_NORMAL, PARENT_NUMS_2,
JH7110_GMAC1_GTXCLK,
JH7110_GMAC1_RMII_RTX),
JH7110__INV(JH7110_GMAC5_CLK_TX_INV, "u1_dw_gmac5_axi64_clk_tx_inv",
JH7110_GMAC5_CLK_TX),
JH7110_GATE(JH7110_GMAC1_GTXC, "gmac1_gtxc",
- 0, JH7110_GMAC1_GTXCLK),
+ GATE_FLAG_NORMAL, JH7110_GMAC1_GTXCLK),
//GMAC0
JH7110_GDIV(JH7110_GMAC0_GTXCLK, "gmac0_gtxclk",
- 0, 15, JH7110_GMACUSB_ROOT),
+ GATE_FLAG_NORMAL, 15, JH7110_GMACUSB_ROOT),
JH7110_GDIV(JH7110_GMAC0_PTP, "gmac0_ptp",
- 0, 31, JH7110_GMAC_SRC),
+ GATE_FLAG_NORMAL, 31, JH7110_GMAC_SRC),
JH7110_GDIV(JH7110_GMAC_PHY, "gmac_phy",
- 0, 31, JH7110_GMAC_SRC),
+ GATE_FLAG_NORMAL, 31, JH7110_GMAC_SRC),
JH7110_GATE(JH7110_GMAC0_GTXC, "gmac0_gtxc",
- 0, JH7110_GMAC0_GTXCLK),
+ GATE_FLAG_NORMAL, JH7110_GMAC0_GTXCLK),
//SYS MISC
JH7110_GATE(JH7110_SYS_IOMUX_PCLK, "u0_sys_iomux_pclk",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
JH7110_GATE(JH7110_MAILBOX_CLK_APB, "u0_mailbox_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
JH7110_GATE(JH7110_INT_CTRL_CLK_APB, "u0_int_ctrl_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
//CAN
JH7110_GATE(JH7110_CAN0_CTRL_CLK_APB, "u0_can_ctrl_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
JH7110_GDIV(JH7110_CAN0_CTRL_CLK_TIMER, "u0_can_ctrl_clk_timer",
- 0, 24, JH7110_OSC),
+ GATE_FLAG_NORMAL, 24, JH7110_OSC),
JH7110_GDIV(JH7110_CAN0_CTRL_CLK_CAN, "u0_can_ctrl_clk_can",
- 0, 63, JH7110_PERH_ROOT),
+ GATE_FLAG_NORMAL, 63, JH7110_PERH_ROOT),
JH7110_GATE(JH7110_CAN1_CTRL_CLK_APB, "u1_can_ctrl_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
JH7110_GDIV(JH7110_CAN1_CTRL_CLK_TIMER, "u1_can_ctrl_clk_timer",
- 0, 24, JH7110_OSC),
+ GATE_FLAG_NORMAL, 24, JH7110_OSC),
JH7110_GDIV(JH7110_CAN1_CTRL_CLK_CAN, "u1_can_ctrl_clk_can",
- 0, 63, JH7110_PERH_ROOT),
+ GATE_FLAG_NORMAL, 63, JH7110_PERH_ROOT),
//PWM
JH7110_GATE(JH7110_PWM_CLK_APB, "u0_pwm_8ch_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
//WDT
JH7110_GATE(JH7110_DSKIT_WDT_CLK_APB, "u0_dskit_wdt_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
JH7110_GATE(JH7110_DSKIT_WDT_CLK_WDT, "u0_dskit_wdt_clk_wdt",
- 0, JH7110_OSC),
+ GATE_FLAG_NORMAL, JH7110_OSC),
//TIMER
JH7110_GATE(JH7110_TIMER_CLK_APB, "u0_si5_timer_clk_apb",
- CLK_IGNORE_UNUSED, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
JH7110_GATE(JH7110_TIMER_CLK_TIMER0, "u0_si5_timer_clk_timer0",
- CLK_IGNORE_UNUSED, JH7110_OSC),
+ GATE_FLAG_NORMAL, JH7110_OSC),
JH7110_GATE(JH7110_TIMER_CLK_TIMER1, "u0_si5_timer_clk_timer1",
- CLK_IGNORE_UNUSED, JH7110_OSC),
+ GATE_FLAG_NORMAL, JH7110_OSC),
JH7110_GATE(JH7110_TIMER_CLK_TIMER2, "u0_si5_timer_clk_timer2",
- CLK_IGNORE_UNUSED, JH7110_OSC),
+ GATE_FLAG_NORMAL, JH7110_OSC),
JH7110_GATE(JH7110_TIMER_CLK_TIMER3, "u0_si5_timer_clk_timer3",
- CLK_IGNORE_UNUSED, JH7110_OSC),
+ GATE_FLAG_NORMAL, JH7110_OSC),
//TEMP SENSOR
JH7110_GATE(JH7110_TEMP_SENSOR_CLK_APB, "u0_temp_sensor_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
JH7110_GDIV(JH7110_TEMP_SENSOR_CLK_TEMP, "u0_temp_sensor_clk_temp",
- 0, 24, JH7110_OSC),
+ GATE_FLAG_NORMAL, 24, JH7110_OSC),
//SPI
JH7110_GATE(JH7110_SPI0_CLK_APB, "u0_ssp_spi_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
JH7110_GATE(JH7110_SPI1_CLK_APB, "u1_ssp_spi_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
JH7110_GATE(JH7110_SPI2_CLK_APB, "u2_ssp_spi_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
JH7110_GATE(JH7110_SPI3_CLK_APB, "u3_ssp_spi_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
JH7110_GATE(JH7110_SPI4_CLK_APB, "u4_ssp_spi_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
JH7110_GATE(JH7110_SPI5_CLK_APB, "u5_ssp_spi_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
JH7110_GATE(JH7110_SPI6_CLK_APB, "u6_ssp_spi_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
//I2C
JH7110_GATE(JH7110_I2C0_CLK_APB, "u0_dw_i2c_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
JH7110_GATE(JH7110_I2C1_CLK_APB, "u1_dw_i2c_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
JH7110_GATE(JH7110_I2C2_CLK_APB, "u2_dw_i2c_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
JH7110_GATE(JH7110_I2C3_CLK_APB, "u3_dw_i2c_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
JH7110_GATE(JH7110_I2C4_CLK_APB, "u4_dw_i2c_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
JH7110_GATE(JH7110_I2C5_CLK_APB, "u5_dw_i2c_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
JH7110_GATE(JH7110_I2C6_CLK_APB, "u6_dw_i2c_clk_apb",
- 0, JH7110_APB12),
+ GATE_FLAG_NORMAL, JH7110_APB12),
//UART
JH7110_GATE(JH7110_UART0_CLK_APB, "u0_dw_uart_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
JH7110_GATE(JH7110_UART0_CLK_CORE, "u0_dw_uart_clk_core",
- 0, JH7110_OSC),
+ GATE_FLAG_NORMAL, JH7110_OSC),
JH7110_GATE(JH7110_UART1_CLK_APB, "u1_dw_uart_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
JH7110_GATE(JH7110_UART1_CLK_CORE, "u1_dw_uart_clk_core",
- 0, JH7110_OSC),
+ GATE_FLAG_NORMAL, JH7110_OSC),
JH7110_GATE(JH7110_UART2_CLK_APB, "u2_dw_uart_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
JH7110_GATE(JH7110_UART2_CLK_CORE, "u2_dw_uart_clk_core",
- 0, JH7110_OSC),
+ GATE_FLAG_NORMAL, JH7110_OSC),
JH7110_GATE(JH7110_UART3_CLK_APB, "u3_dw_uart_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
JH7110_GDIV(JH7110_UART3_CLK_CORE, "u3_dw_uart_clk_core",
- 0, 131071, JH7110_PERH_ROOT),
+ GATE_FLAG_NORMAL, 131071, JH7110_PERH_ROOT),
JH7110_GATE(JH7110_UART4_CLK_APB, "u4_dw_uart_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
JH7110_GDIV(JH7110_UART4_CLK_CORE, "u4_dw_uart_clk_core",
- 0, 131071, JH7110_PERH_ROOT),
+ GATE_FLAG_NORMAL, 131071, JH7110_PERH_ROOT),
JH7110_GATE(JH7110_UART5_CLK_APB, "u5_dw_uart_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
JH7110_GDIV(JH7110_UART5_CLK_CORE, "u5_dw_uart_clk_core",
- 0, 131071, JH7110_PERH_ROOT),
+ GATE_FLAG_NORMAL, 131071, JH7110_PERH_ROOT),
//PWMDAC
JH7110_GATE(JH7110_PWMDAC_CLK_APB, "u0_pwmdac_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
JH7110_GDIV(JH7110_PWMDAC_CLK_CORE, "u0_pwmdac_clk_core",
- 0, 256, JH7110_AUDIO_ROOT),
+ GATE_FLAG_NORMAL, 256, JH7110_AUDIO_ROOT),
//SPDIF
JH7110_GATE(JH7110_SPDIF_CLK_APB, "u0_cdns_spdif_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
JH7110_GATE(JH7110_SPDIF_CLK_CORE, "u0_cdns_spdif_clk_core",
- 0, JH7110_MCLK),
+ GATE_FLAG_NORMAL, JH7110_MCLK),
//I2STX0_4CH0
JH7110_GATE(JH7110_I2STX0_4CHCLK_APB, "u0_i2stx_4ch_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
JH7110_GDIV(JH7110_I2STX_4CH0_BCLK_MST, "i2stx_4ch0_bclk_mst",
- 0, 32, JH7110_MCLK),
+ GATE_FLAG_NORMAL, 32, JH7110_MCLK),
JH7110__INV(JH7110_I2STX_4CH0_BCLK_MST_INV, "i2stx_4ch0_bclk_mst_inv",
JH7110_I2STX_4CH0_BCLK_MST),
- JH7110_MDIV(JH7110_I2STX_4CH0_LRCK_MST, "i2stx_4ch0_lrck_mst", 64, 2,
+ JH7110_MDIV(JH7110_I2STX_4CH0_LRCK_MST, "i2stx_4ch0_lrck_mst",
+ 64, PARENT_NUMS_2,
JH7110_I2STX_4CH0_BCLK_MST_INV,
JH7110_I2STX_4CH0_BCLK_MST),
- JH7110__MUX(JH7110_I2STX0_4CHBCLK, "u0_i2stx_4ch_bclk", 2,
+ JH7110__MUX(JH7110_I2STX0_4CHBCLK, "u0_i2stx_4ch_bclk",
+ PARENT_NUMS_2,
JH7110_I2STX_4CH0_BCLK_MST,
JH7110_I2STX_BCLK_EXT),
JH7110__INV(JH7110_I2STX0_4CHBCLK_N, "u0_i2stx_4ch_bclk_n",
JH7110_I2STX0_4CHBCLK),
- JH7110__MUX(JH7110_I2STX0_4CHLRCK, "u0_i2stx_4ch_lrck", 2,
+ JH7110__MUX(JH7110_I2STX0_4CHLRCK, "u0_i2stx_4ch_lrck",
+ PARENT_NUMS_2,
JH7110_I2STX_4CH0_LRCK_MST,
JH7110_I2STX_LRCK_EXT),
//I2STX1_4CH0
JH7110_GATE(JH7110_I2STX1_4CHCLK_APB, "u1_i2stx_4ch_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
JH7110_GDIV(JH7110_I2STX_4CH1_BCLK_MST, "i2stx_4ch1_bclk_mst",
- 0, 32, JH7110_MCLK),
+ GATE_FLAG_NORMAL, 32, JH7110_MCLK),
JH7110__INV(JH7110_I2STX_4CH1_BCLK_MST_INV, "i2stx_4ch1_bclk_mst_inv",
JH7110_I2STX_4CH1_BCLK_MST),
- JH7110_MDIV(JH7110_I2STX_4CH1_LRCK_MST, "i2stx_4ch1_lrck_mst", 64, 2,
+ JH7110_MDIV(JH7110_I2STX_4CH1_LRCK_MST, "i2stx_4ch1_lrck_mst",
+ 64, PARENT_NUMS_2,
JH7110_I2STX_4CH1_BCLK_MST_INV,
JH7110_I2STX_4CH1_BCLK_MST),
- JH7110__MUX(JH7110_I2STX1_4CHBCLK, "u1_i2stx_4ch_bclk", 2,
+ JH7110__MUX(JH7110_I2STX1_4CHBCLK, "u1_i2stx_4ch_bclk",
+ PARENT_NUMS_2,
JH7110_I2STX_4CH1_BCLK_MST,
JH7110_I2STX_BCLK_EXT),
JH7110__INV(JH7110_I2STX1_4CHBCLK_N, "u1_i2stx_4ch_bclk_n",
JH7110_I2STX1_4CHBCLK),
- JH7110__MUX(JH7110_I2STX1_4CHLRCK, "u1_i2stx_4ch_lrck", 2,
+ JH7110__MUX(JH7110_I2STX1_4CHLRCK, "u1_i2stx_4ch_lrck",
+ PARENT_NUMS_2,
JH7110_I2STX_4CH1_LRCK_MST,
JH7110_I2STX_LRCK_EXT),
//I2SRX_3CH
JH7110_GATE(JH7110_I2SRX0_3CH_CLK_APB, "u0_i2srx_3ch_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
JH7110_GDIV(JH7110_I2SRX_3CH_BCLK_MST, "i2srx_3ch_bclk_mst",
- 0, 32, JH7110_MCLK),
+ GATE_FLAG_NORMAL, 32, JH7110_MCLK),
JH7110__INV(JH7110_I2SRX_3CH_BCLK_MST_INV, "i2srx_3ch_bclk_mst_inv",
JH7110_I2SRX_3CH_BCLK_MST),
- JH7110_MDIV(JH7110_I2SRX_3CH_LRCK_MST, "i2srx_3ch_lrck_mst", 64, 2,
+ JH7110_MDIV(JH7110_I2SRX_3CH_LRCK_MST, "i2srx_3ch_lrck_mst",
+ 64, PARENT_NUMS_2,
JH7110_I2SRX_3CH_BCLK_MST_INV,
JH7110_I2SRX_3CH_BCLK_MST),
- JH7110__MUX(JH7110_I2SRX0_3CH_BCLK, "u0_i2srx_3ch_bclk", 2,
+ JH7110__MUX(JH7110_I2SRX0_3CH_BCLK, "u0_i2srx_3ch_bclk",
+ PARENT_NUMS_2,
JH7110_I2SRX_3CH_BCLK_MST,
JH7110_I2SRX_BCLK_EXT),
JH7110__INV(JH7110_I2SRX0_3CH_BCLK_N, "u0_i2srx_3ch_bclk_n",
JH7110_I2SRX0_3CH_BCLK),
- JH7110__MUX(JH7110_I2SRX0_3CH_LRCK, "u0_i2srx_3ch_lrck", 2,
+ JH7110__MUX(JH7110_I2SRX0_3CH_LRCK, "u0_i2srx_3ch_lrck",
+ PARENT_NUMS_2,
JH7110_I2SRX_3CH_LRCK_MST,
JH7110_I2SRX_LRCK_EXT),
//PDM_4MIC
JH7110_GDIV(JH7110_PDM_CLK_DMIC, "u0_pdm_4mic_clk_dmic",
- 0, 64, JH7110_MCLK),
+ GATE_FLAG_NORMAL, 64, JH7110_MCLK),
JH7110_GATE(JH7110_PDM_CLK_APB, "u0_pdm_4mic_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
//TDM
JH7110_GATE(JH7110_TDM_CLK_AHB, "u0_tdm16slot_clk_ahb",
- 0, JH7110_AHB0),
+ GATE_FLAG_NORMAL, JH7110_AHB0),
JH7110_GATE(JH7110_TDM_CLK_APB, "u0_tdm16slot_clk_apb",
- 0, JH7110_APB0),
+ GATE_FLAG_NORMAL, JH7110_APB0),
JH7110_GDIV(JH7110_TDM_INTERNAL, "tdm_internal",
- 0, 64, JH7110_MCLK),
- JH7110__MUX(JH7110_TDM_CLK_TDM, "u0_tdm16slot_clk_tdm", 2,
+ GATE_FLAG_NORMAL, 64, JH7110_MCLK),
+ JH7110__MUX(JH7110_TDM_CLK_TDM, "u0_tdm16slot_clk_tdm",
+ PARENT_NUMS_2,
JH7110_TDM_INTERNAL,
JH7110_TDM_EXT),
JH7110__INV(JH7110_TDM_CLK_TDM_N, "u0_tdm16slot_clk_tdm_n",
projects / platform / kernel / linux-starfive.git / commitdiff