drm/amdgpu/pm: correct the firmware flag address for SMU IP v13.0.4
authorTim Huang <tim.huang@amd.com>
Wed, 1 Jun 2022 10:12:08 +0000 (18:12 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 15 Jun 2022 01:38:39 +0000 (21:38 -0400)
For SMU IP v13.0.4, the smnMP1_FIRMWARE_FLAGS address is different,
we need this to correct the reading address.

Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

index e3454a8..43de0a8 100644 (file)
@@ -43,6 +43,7 @@
 
 /* address block */
 #define smnMP1_FIRMWARE_FLAGS          0x3010024
+#define smnMP1_V13_0_4_FIRMWARE_FLAGS  0x3010028
 #define smnMP0_FW_INTF                 0x30101c0
 #define smnMP1_PUB_CTRL                        0x3010b14
 
index f9c36d2..fba0b87 100644 (file)
@@ -273,8 +273,16 @@ int smu_v13_0_check_fw_status(struct smu_context *smu)
        struct amdgpu_device *adev = smu->adev;
        uint32_t mp1_fw_flags;
 
-       mp1_fw_flags = RREG32_PCIE(MP1_Public |
-                                  (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
+       switch (adev->ip_versions[MP1_HWIP][0]) {
+       case IP_VERSION(13, 0, 4):
+               mp1_fw_flags = RREG32_PCIE(MP1_Public |
+                                          (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff));
+               break;
+       default:
+               mp1_fw_flags = RREG32_PCIE(MP1_Public |
+                                          (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
+               break;
+       }
 
        if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
            MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)