{
struct smu_power_context *smu_power = &smu->smu_power;
struct smu_power_gate *power_gate = &smu_power->power_gate;
+ struct amdgpu_device *adev = smu->adev;
+
int ret = 0;
if (enable) {
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
if (ret)
return ret;
- ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0x10000, NULL);
- if (ret)
- return ret;
+ if (adev->asic_type == CHIP_SIENNA_CICHLID) {
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
+ 0x10000, NULL);
+ if (ret)
+ return ret;
+ }
}
power_gate->vcn_gated = false;
} else {
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
if (ret)
return ret;
- ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0x10000, NULL);
- if (ret)
- return ret;
+ if (adev->asic_type == CHIP_SIENNA_CICHLID) {
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
+ 0x10000, NULL);
+ if (ret)
+ return ret;
+ }
}
power_gate->vcn_gated = true;
}