[RISCV] Rename RVV intrinsics class (NFC)
authorEvandro Menezes <evandro.menezes@sifive.com>
Thu, 31 Dec 2020 09:55:19 +0000 (03:55 -0600)
committerEvandro Menezes <evandro.menezes@sifive.com>
Tue, 5 Jan 2021 02:32:30 +0000 (20:32 -0600)
Rename the class `RISCVUnaryAAMask` to `RISCVBinaryAAAMask`, since it has two input arguments.

llvm/include/llvm/IR/IntrinsicsRISCV.td

index ebb93ff..fe0d6b0 100644 (file)
@@ -189,19 +189,19 @@ let TargetPrefix = "riscv" in {
                      LLVMPointerType<LLVMMatchType<0>>, llvm_anyvector_ty,
                      LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
                     [NoCapture<ArgIndex<1>>, IntrWriteMem]>, RISCVVIntrinsic;
-  // For destination vector type is the same as first source vector (with mask).
-  // Input: (maskedoff, vector_in, mask, vl)
-  class RISCVUnaryAAMask
-        : Intrinsic<[llvm_anyvector_ty],
-                    [LLVMMatchType<0>, LLVMMatchType<0>,
-                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
-                    [IntrNoMem]>, RISCVVIntrinsic;
   // For destination vector type is the same as first and second source vector.
   // Input: (vector_in, vector_in, vl)
   class RISCVBinaryAAANoMask
         : Intrinsic<[llvm_anyvector_ty],
                     [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty],
                     [IntrNoMem]>, RISCVVIntrinsic;
+  // For destination vector type is the same as first and second source vector.
+  // Input: (vector_in, vector_in, vl)
+  class RISCVBinaryAAAMask
+        : Intrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, LLVMMatchType<0>,
+                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
+                    [IntrNoMem]>, RISCVVIntrinsic;
   // For destination vector type is the same as first source vector.
   // Input: (vector_in, vector_in/scalar_in, vl)
   class RISCVBinaryAAXNoMask
@@ -704,7 +704,7 @@ let TargetPrefix = "riscv" in {
 
   defm vrgather : RISCVBinaryAAX;
 
-  def "int_riscv_vcompress_mask" : RISCVUnaryAAMask;
+  def "int_riscv_vcompress_mask" : RISCVBinaryAAAMask;
 
   defm vaaddu : RISCVSaturatingBinaryAAX;
   defm vaadd : RISCVSaturatingBinaryAAX;