Fri May 7 19:10:15 1999 Vladimir Makarov <vmakarov@tofu.to.cygnus.com>

	* sparc.h (GO_IF_LEGITIMATE_ADDRESS): Prohibit REG+REG addressing
 	for TFmode when there are no instructions which accept REG+REG
 	instructions.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@26825 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d33a850..e264420 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+Fri May  7 19:10:15 1999  Vladimir Makarov  <vmakarov@tofu.to.cygnus.com>
+
+       * sparc.h (GO_IF_LEGITIMATE_ADDRESS): Prohibit REG+REG addressing
+       for TFmode when there are no instructions which accept REG+REG
+       instructions.
+
 Fri May  7 12:38:54 1999  Jim Wilson  <wilson@cygnus.com>
 
        * mips/elf64.h (MAKE_DECL_ONE_ONLY, UNIQUE_SECTION_P): Define.

diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index a220ce7..b10d096 100644 (file)
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -2489,12 +2489,29 @@ extern struct rtx_def *sparc_builtin_saveregs ();
       else if (RTX_OK_FOR_BASE_P (op0))                        \
        {                                               \
          if (RTX_OK_FOR_INDEX_P (op1)                  \
+             /* We prohibit REG + REG for TFmode when  \
+                there are no instructions which accept \
+                REG+REG instructions.  We do this      \
+                because REG+REG is not an offsetable   \
+                address.  If we get the situation      \
+                in reload where source and destination \
+                of a movtf pattern are both MEMs with  \
+                REG+REG address, then only one of them \
+                gets converted to an offsetable        \
+                address. */                            \
+             && (MODE != TFmode                        \
+                 || (TARGET_FPU && TARGET_ARCH64       \
+                     && TARGET_V9 && TARGET_HARD_QUAD))\
              || RTX_OK_FOR_OFFSET_P (op1))             \
            goto ADDR;                                  \
        }                                               \
       else if (RTX_OK_FOR_BASE_P (op1))                        \
        {                                               \
          if (RTX_OK_FOR_INDEX_P (op0)                  \
+             /* See the previous comment. */           \
+             && (MODE != TFmode                        \
+                 || (TARGET_FPU && TARGET_ARCH64       \
+                     && TARGET_V9 && TARGET_HARD_QUAD))\
              || RTX_OK_FOR_OFFSET_P (op0))             \
            goto ADDR;                                  \
        }                                               \