drm/i915: decouple gen9 and gen10 dp signal levels.

Let's decouple bxt, glk and cnl dp signal levels
from other DDIs to avoid confusion.

No functional change. Only a reorg to avoid messing
with currently working DP signal levels when
moving voltage swing sequences around to match spec.

v2: ddi_signal_levels is also called from other ddi
    platforms, so don't remove IS_GEN9_BC check from
    skl_ddi_set_iboos. (Ville).

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170829232230.23051-2-rodrigo.vivi@intel.com

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 7e875e0..9a88778 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2063,23 +2063,32 @@ static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
        return translate_signal_level(signal_levels);
 }
 
-uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
+u32 bxt_signal_levels(struct intel_dp *intel_dp)
 {
        struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
        struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
        struct intel_encoder *encoder = &dport->base;
        enum port port = dport->port;
+       u32 level = intel_ddi_dp_level(intel_dp);
+
+       if (IS_CANNONLAKE(dev_priv))
+               cnl_ddi_vswing_sequence(encoder, level);
+       else
+               bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
+
+       return 0;
+}
+
+uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
+{
+       struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
+       struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
+       struct intel_encoder *encoder = &dport->base;
        uint32_t level = intel_ddi_dp_level(intel_dp);
 
        if (IS_GEN9_BC(dev_priv))
-               skl_ddi_set_iboost(encoder, level);
-       else if (IS_GEN9_LP(dev_priv))
-               bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
-       else if (IS_CANNONLAKE(dev_priv)) {
-               cnl_ddi_vswing_sequence(encoder, level);
-               /* DDI_BUF_CTL bits 27:24 are reserved on CNL */
-               return 0;
-       }
+           skl_ddi_set_iboost(encoder, level);
+
        return DDI_BUF_TRANS_SELECT(level);
 }
 

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d3e5fdf..49a8c33 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3506,13 +3506,11 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
        uint32_t signal_levels, mask = 0;
        uint8_t train_set = intel_dp->train_set[0];
 
-       if (HAS_DDI(dev_priv)) {
+       if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+               signal_levels = bxt_signal_levels(intel_dp);
+       } else if (HAS_DDI(dev_priv)) {
                signal_levels = ddi_signal_levels(intel_dp);
-
-               if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
-                       signal_levels = 0;
-               else
-                       mask = DDI_BUF_EMP_MASK;
+               mask = DDI_BUF_EMP_MASK;
        } else if (IS_CHERRYVIEW(dev_priv)) {
                signal_levels = chv_signal_levels(intel_dp);
        } else if (IS_VALLEYVIEW(dev_priv)) {

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 17649f1..469c060 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1271,6 +1271,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
                         struct intel_crtc_state *pipe_config);
 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
                                    bool state);
+u32 bxt_signal_levels(struct intel_dp *intel_dp);
 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);