arm64: dts: ti: Add initial support for J721S2 System on Module

A System on Module (SoM) contains the SoC, PMIC, DDR and basic high speed
components necessary for functionality. Therefore, add support for the
components present on the SoM.

SoM: https://www.ti.com/lit/zip/sprr439

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20211207080904.14324-5-a-govindraju@ti.com

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
new file mode 100644 (file)
index 0000000..76f0cea
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SoM: https://www.ti.com/lit/zip/sprr439
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j721s2.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+       memory@80000000 {
+               device_type = "memory";
+               /* 16 GB RAM */
+               reg = <0x00 0x80000000 0x00 0x80000000>,
+                     <0x08 0x80000000 0x03 0x80000000>;
+       };
+
+       /* Reserving memory regions still pending */
+       reserved_memory: reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               secure_ddr: optee@9e800000 {
+                       reg = <0x00 0x9e800000 0x00 0x01800000>;
+                       alignment = <0x1000>;
+                       no-map;
+               };
+       };
+
+       transceiver0: can-phy0 {
+               /* standby pin has been grounded by default */
+               compatible = "ti,tcan1042";
+               #phy-cells = <0>;
+               max-bitrate = <5000000>;
+       };
+};
+
+&main_pmx0 {
+       main_i2c0_pins_default: main-i2c0-pins-default {
+               pinctrl-single,pins = <
+                       J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
+                       J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
+               >;
+       };
+
+       main_mcan16_pins_default: main-mcan16-pins-default {
+               pinctrl-single,pins = <
+                       J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
+                       J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */
+               >;
+       };
+};
+
+&main_i2c0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_i2c0_pins_default>;
+       clock-frequency = <400000>;
+
+       exp_som: gpio@21 {
+               compatible = "ti,tca6408";
+               reg = <0x21>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
+                                 "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
+                                 "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE",
+                                  "GPIO_LIN_EN", "CAN_STB";
+       };
+};
+
+&main_mcan16 {
+       pinctrl-0 = <&main_mcan16_pins_default>;
+       pinctrl-names = "default";
+       phys = <&transceiver0>;
+};
+
+&mailbox0_cluster0 {
+       status = "disabled";
+};
+
+&mailbox0_cluster1 {
+       status = "disabled";
+};
+
+&mailbox0_cluster2 {
+       status = "disabled";
+};
+
+&mailbox0_cluster3 {
+       status = "disabled";
+};
+
+&mailbox0_cluster4 {
+       status = "disabled";
+};
+
+&mailbox0_cluster5 {
+       status = "disabled";
+};
+
+&mailbox0_cluster6 {
+       status = "disabled";
+};
+
+&mailbox0_cluster7 {
+       status = "disabled";
+};
+
+&mailbox0_cluster8 {
+       status = "disabled";
+};
+
+&mailbox0_cluster9 {
+       status = "disabled";
+};
+
+&mailbox0_cluster10 {
+       status = "disabled";
+};
+
+&mailbox0_cluster11 {
+       status = "disabled";
+};
+
+&mailbox1_cluster0 {
+       status = "disabled";
+};
+
+&mailbox1_cluster1 {
+       status = "disabled";
+};
+
+&mailbox1_cluster2 {
+       status = "disabled";
+};
+
+&mailbox1_cluster3 {
+       status = "disabled";
+};
+
+&mailbox1_cluster4 {
+       status = "disabled";
+};
+
+&mailbox1_cluster5 {
+       status = "disabled";
+};
+
+&mailbox1_cluster6 {
+       status = "disabled";
+};
+
+&mailbox1_cluster7 {
+       status = "disabled";
+};
+
+&mailbox1_cluster8 {
+       status = "disabled";
+};
+
+&mailbox1_cluster9 {
+       status = "disabled";
+};
+
+&mailbox1_cluster10 {
+       status = "disabled";
+};
+
+&mailbox1_cluster11 {
+       status = "disabled";
+};