desc = irq_to_desc(irq);
if (desc)
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
return cfg;
}
{
struct irq_cfg *cfg;
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
if (!cfg) {
- desc->chip_data = get_one_free_irq_cfg(node);
- if (!desc->chip_data) {
+ cfg = get_one_free_irq_cfg(node);
+ desc->chip_data = cfg;
+ if (!cfg) {
printk(KERN_ERR "can not alloc irq_cfg\n");
BUG_ON(1);
}
{
struct irq_cfg *old_cfg, *cfg;
- old_cfg = old_desc->chip_data;
- cfg = desc->chip_data;
+ old_cfg = get_irq_desc_chip_data(old_desc);
+ cfg = get_irq_desc_chip_data(desc);
if (old_cfg == cfg)
return;
static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
{
- struct irq_cfg *cfg = desc->chip_data;
+ struct irq_cfg *cfg = get_irq_desc_chip_data(desc);
unsigned long flags;
BUG_ON(!cfg);
static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
{
- struct irq_cfg *cfg = desc->chip_data;
+ struct irq_cfg *cfg = get_irq_desc_chip_data(desc);
unsigned long flags;
raw_spin_lock_irqsave(&ioapic_lock, flags);
raw_spin_lock(&vector_lock);
/* Mark the inuse vectors */
for_each_irq_desc(irq, desc) {
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
/*
* If it is a legacy IRQ handled by the legacy PIC, this cpu
if (!IO_APIC_IRQ(irq))
return;
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
/*
* For legacy irqs, cfg->domain starts with cpu 0 for legacy
printk(KERN_INFO "can not get irq_desc for %d\n", irq);
continue;
}
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
add_pin_to_irq_node(cfg, node, apic_id, pin);
/*
* don't mark it in pin_programmed, so later acpi could
return;
}
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
add_pin_to_irq_node(cfg, node, apic_id, pin);
if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) {
for_each_irq_desc(irq, desc) {
struct irq_pin_list *entry;
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
if (!cfg)
continue;
entry = cfg->irq_2_pin;
return -1;
irq = desc->irq;
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
if (assign_irq_vector(irq, cfg, mask))
return -1;
int ret = -1;
irq = desc->irq;
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
raw_spin_lock_irqsave(&ioapic_lock, flags);
ret = set_desc_affinity(desc, mask, &dest);
if (get_irte(irq, &irte))
return ret;
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
if (assign_irq_vector(irq, cfg, mask))
return ret;
static void __irq_complete_move(struct irq_desc **descp, unsigned vector)
{
struct irq_desc *desc = *descp;
- struct irq_cfg *cfg = desc->chip_data;
+ struct irq_cfg *cfg = get_irq_desc_chip_data(desc);
unsigned me;
if (likely(!cfg->move_in_progress))
void irq_force_complete_move(int irq)
{
struct irq_desc *desc = irq_to_desc(irq);
- struct irq_cfg *cfg = desc->chip_data;
+ struct irq_cfg *cfg = get_irq_desc_chip_data(desc);
if (!cfg)
return;
unsigned int irq;
irq = desc->irq;
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
raw_spin_lock_irqsave(&ioapic_lock, flags);
__eoi_ioapic_irq(irq, cfg);
* we use the above logic (mask+edge followed by unmask+level) from
* Manfred Spraul to clear the remote IRR.
*/
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
i = cfg->vector;
v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
* accurate and is causing problems then it is a hardware bug
* and you can go talk to the chipset vendor about it.
*/
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
if (!io_apic_level_ack_pending(cfg))
move_masked_irq(irq);
unmask_IO_APIC_irq_desc(desc);
* 0x80, because int 0x80 is hm, kind of importantish. ;)
*/
for_each_irq_desc(irq, desc) {
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
/*
* Hmm.. We don't have an entry for this,
static inline void __init check_timer(void)
{
struct irq_desc *desc = irq_to_desc(0);
- struct irq_cfg *cfg = desc->chip_data;
+ struct irq_cfg *cfg = get_irq_desc_chip_data(desc);
int node = cpu_to_node(0);
int apic1, pin1, apic2, pin2;
unsigned long flags;
printk(KERN_INFO "can not get irq_desc for %d\n", new);
continue;
}
- cfg_new = desc_new->chip_data;
+ cfg_new = get_irq_desc_chip_data(desc_new);
if (cfg_new->vector != 0)
continue;
desc_new = move_irq_desc(desc_new, node);
- cfg_new = desc_new->chip_data;
+ cfg_new = get_irq_desc_chip_data(desc_new);
if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
irq = new;
if (set_desc_affinity(desc, mask, &dest))
return -1;
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
__get_cached_msi_msg(desc->irq_data.msi_desc, &msg);
ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
{
struct irq_desc *desc = irq_to_desc(irq);
- struct irq_cfg *cfg = desc->chip_data;
+ struct irq_cfg *cfg = get_irq_desc_chip_data(desc);
unsigned int dest;
struct irte irte;
if (set_desc_affinity(desc, mask, &dest))
return -1;
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
dmar_msi_read(irq, &msg);
if (set_desc_affinity(desc, mask, &dest))
return -1;
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
hpet_msi_read(irq, &msg);
if (set_desc_affinity(desc, mask, &dest))
return -1;
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
target_ht_irq(irq, dest, cfg->vector);
* IRQs < 16 are already in the irq_2_pin[] map
*/
if (irq >= legacy_pic->nr_legacy_irqs) {
- cfg = desc->chip_data;
+ cfg = get_irq_desc_chip_data(desc);
if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
printk(KERN_INFO "can not add pin %d for irq %d\n",
pin, irq);