drm/i915/psr: Use ->get_aux_send_ctl functions

I just wanted to get rid of the rmw cycle for gen9, but this also
fixes some bugs we haven't carried over, like using recommended
precharge and timeout values.

Also I noticed that we don't set the fastwake sync length on skl, and
that's used by PSR2 selective updates. Fix that.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Sonika Jindal <sonika.jindal@intel.com>
Cc: Durgadoss R <durgadoss.r@intel.com>
Cc: "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463590036-17824-6-git-send-email-daniel.vetter@ffwll.ch

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3633002..cccf9bc 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -770,6 +770,7 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
               DP_AUX_CH_CTL_TIME_OUT_1600us |
               DP_AUX_CH_CTL_RECEIVE_ERROR |
               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
+              DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 }
 

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index e08751c..29a09bf 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -176,7 +176,6 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
        struct drm_i915_private *dev_priv = dev->dev_private;
        uint32_t aux_clock_divider;
        i915_reg_t aux_ctl_reg;
-       int precharge = 0x3;
        static const uint8_t aux_msg[] = {
                [0] = DP_AUX_NATIVE_WRITE << 4,
                [1] = DP_SET_POWER >> 8,
@@ -185,6 +184,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
                [4] = DP_SET_POWER_D0,
        };
        enum port port = dig_port->port;
+       u32 aux_ctl;
        int i;
 
        BUILD_BUG_ON(sizeof(aux_msg) > 20);
@@ -211,26 +211,9 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
                I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
                           intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 
-       if (INTEL_INFO(dev)->gen >= 9) {
-               uint32_t val;
-
-               val = I915_READ(aux_ctl_reg);
-               val &= ~DP_AUX_CH_CTL_TIME_OUT_MASK;
-               val |= DP_AUX_CH_CTL_TIME_OUT_1600us;
-               val &= ~DP_AUX_CH_CTL_MESSAGE_SIZE_MASK;
-               val |= (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
-               /* Use hardcoded data values for PSR, frame sync and GTC */
-               val &= ~DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL;
-               val &= ~DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL;
-               val &= ~DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL;
-               I915_WRITE(aux_ctl_reg, val);
-       } else {
-               I915_WRITE(aux_ctl_reg,
-                  DP_AUX_CH_CTL_TIME_OUT_400us |
-                  (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
-                  (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
-                  (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
-       }
+       aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg),
+                                            aux_clock_divider);
+       I915_WRITE(aux_ctl_reg, aux_ctl);
 }
 
 static void vlv_psr_enable_source(struct intel_dp *intel_dp)