drm/i915: Remove incorrect restriction on 32bit offsets in ppGTT backend

This is the wrong layer to apply an arbitrary restriction and the wrong
error code (object too large!). If we do want to prevent large offsets
being return to the user on 32bit systems (to hide bugs in userspace),
you want to restrict the drm_mm range manager instead. This first tells
userspace about the correct size of the GTT they can use (so they don't
try and overallocate object or batches), and fixes the eviction logic to
avoid the eventual and *guaranteed* error.

Fixes regression in
commit d7b2633dba04ef0fd7385f02a7b552abc5f1062f
Author: Michel Thierry <michel.thierry@intel.com>
Date:   Wed Apr 8 12:13:34 2015 +0100

    drm/i915/gen8: Dynamic page table allocations

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index fc562c6..ce91314 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -844,15 +844,6 @@ static int gen8_alloc_va_range(struct i915_address_space *vm,
        uint32_t pdpe;
        int ret;
 
-#ifndef CONFIG_64BIT
-       /* Disallow 64b address on 32b platforms. Nothing is wrong with doing
-        * this in hardware, but a lot of the drm code is not prepared to handle
-        * 64b offset on 32b platforms.
-        * This will be addressed when 48b PPGTT is added */
-       if (start + length > 0x100000000ULL)
-               return -E2BIG;
-#endif
-
        /* Wrap is never okay since we can only represent 48b, and we don't
         * actually use the other side of the canonical address space.
         */