+++ /dev/null
-/*
- * (C) Copyright 2009 SAMSUNG Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __S5PC100_H__
-#define __S5PC100_H__
-
-#define S3C64XX_UART_CHANNELS 3
-#define S3C64XX_SPI_CHANNELS 2
-
-#include <asm/hardware.h>
-
-#define CLOCK_REGISTER_BASE 0xE0100000
-#define OTHERS_REGISTER_BASE 0xE0200000
-
-#define ELFIN_CLOCK_POWER_BASE 0xE0100000
-
-/* Clock & Power Controller for mDirac3*/
-#define APLL_LOCK_OFFSET 0x00
-#define MPLL_LOCK_OFFSET 0x04
-#define EPLL_LOCK_OFFSET 0x08
-#define APLL_CON_OFFSET 0x100
-#define MPLL_CON_OFFSET 0x104
-#define EPLL_CON0_OFFSET 0x108
-#define EPLL_CON1_OFFSET 0x18
-#define CLK_SRC_OFFSET 0x1C
-#define CLK_DIV0_OFFSET 0x300
-#define CLK_DIV1_OFFSET 0x304
-#define CLK_DIV2_OFFSET 0x28
-#define CLK_OUT_OFFSET 0x2C
-#define HCLK_GATE_OFFSET 0x30
-#define PCLK_GATE_OFFSET 0x34
-#define SCLK_GATE_OFFSET 0x38
-#define AHB_CON0_OFFSET 0x100
-#define AHB_CON1_OFFSET 0x104
-#define AHB_CON2_OFFSET 0x108
-#define SELECT_DMA_OFFSET 0x110
-#define SW_RST_OFFSET 0x114
-#define SYS_ID_OFFSET 0x118
-#define MEM_SYS_CFG_OFFSET 0x200
-#define QOS_OVERRIDE0_OFFSET 0x124
-#define QOS_OVERRIDE1_OFFSET 0x128
-#define MEM_CFG_STAT_OFFSET 0x12C
-#define PWR_CFG_OFFSET 0x804
-#define EINT_MASK_OFFSET 0x808
-#define NOR_CFG_OFFSET 0x810
-#define STOP_CFG_OFFSET 0x814
-#define SLEEP_CFG_OFFSET 0x818
-#define OSC_FREQ_OFFSET 0x820
-#define OSC_STABLE_OFFSET 0x824
-#define PWR_STABLE_OFFSET 0x828
-#define FPC_STABLE_OFFSET 0x82C
-#define MTC_STABLE_OFFSET 0x830
-#define OTHERS_OFFSET 0x900
-#define RST_STAT_OFFSET 0x904
-#define WAKEUP_STAT_OFFSET 0x908
-#define BLK_PWR_STAT_OFFSET 0x90C
-#define INF_REG0_OFFSET 0xA00
-#define INF_REG1_OFFSET 0xA04
-#define INF_REG2_OFFSET 0xA08
-#define INF_REG3_OFFSET 0xA0C
-#define INF_REG4_OFFSET 0xA10
-#define INF_REG5_OFFSET 0xA14
-#define INF_REG6_OFFSET 0xA18
-#define INF_REG7_OFFSET 0xA1C
-
-#define OSC_CNT_VAL_OFFSET 0x824
-#define PWR_CNT_VAL_OFFSET 0x828
-#define FPC_CNT_VAL_OFFSET 0x82C
-#define MTC_CNT_VAL_OFFSET 0x830
-
-#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
-#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
-#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
-#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
-#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
-#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
-#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
-#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
-#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
-#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
-#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
-#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
-#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
-#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
-#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
-#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
-#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
-#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
-#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- SELECT_DMA_OFFSET)
-#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
-#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
-#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- MEM_SYS_CFG_OFFSET)
-#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- QOS_OVERRIDE0_OFFSET)
-#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- QOS_OVERRIDE1_OFFSET)
-#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- MEM_CFG_STAT_OFFSET)
-#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
-#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
-#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
-#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
-#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
-#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
-#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- OSC_CNT_VAL_OFFSET)
-#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- PWR_CNT_VAL_OFFSET)
-#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- FPC_CNT_VAL_OFFSET)
-#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- MTC_CNT_VAL_OFFSET)
-#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
-#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
-#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- WAKEUP_STAT_OFFSET)
-#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- BLK_PWR_STAT_OFFSET)
-#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
-#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
-#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
-#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
-#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
-#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
-#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
-#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
-
-#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
-#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
-#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
-#define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
-#define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
-#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
-#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
-#define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
-#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
-#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
-#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
-#define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
-#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
-#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
-#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
-#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
-#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
-#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
-#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET)
-#define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
-#define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
-#define MEM_SYS_CFG (OTHERS_REGISTER_BASE + MEM_SYS_CFG_OFFSET)
-#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET)
-#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET)
-#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET)
-#define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
-#define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
-#define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
-#define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
-#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
-#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
-#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET)
-#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET)
-#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET)
-#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET)
-#define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
-#define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
-#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
-#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET)
-#define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
-#define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
-#define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
-#define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
-#define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
-#define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
-#define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
-#define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
-
-
-/*
- * GPIO
- */
-#define ELFIN_GPIO_BASE 0xE0300000
-
-#define GPx_OFFSET(x) (x * 0x20)
-
-#define CON_OFFSET(x) (GPx_OFFSET(x) + 0x00)
-#define DAT_OFFSET(x) (GPx_OFFSET(x) + 0x04)
-#define PUD_OFFSET(x) (GPx_OFFSET(x) + 0x08)
-#define DRV_OFFSET(x) (GPx_OFFSET(x) + 0x0C)
-#define PDNCON_OFFSET(x) (GPx_OFFSET(x) + 0x10)
-#define PDNPULL_OFFSET(x) (GPx_OFFSET(x) + 0x14)
-
-#define GPx_CON(x) (ELFIN_GPIO_BASE + CON_OFFSET(x))
-#define GPx_DAT(x) (ELFIN_GPIO_BASE + DAT_OFFSET(x))
-#define GPx_PUD(x) (ELFIN_GPIO_BASE + PUD_OFFSET(x))
-#define GPx_PDNCON(x) (ELFIN_GPIO_BASE + PDNCON_OFFSET(x))
-#define GPx_PDNPULL(x) (ELFIN_GPIO_BASE + PDNPULL_OFFSET(x))
-
-#define GPA0CON_OFFSET CON_OFFSET(0x0)
-#define GPA0DAT_OFFSET DAT_OFFSET(0x0)
-#define GPA0PUD_OFFSET PUD_OFFSET(0x0)
-#define GPA0DRV_OFFSET DRV_OFFSET(0x0)
-#define GPA0PDNCON_OFFSET PDNCON_OFFSET(0x0)
-#define GPA0PDNPULL_OFFSET PDNPULL_OFFSET(0x0)
-#define GPA1CON_OFFSET CON_OFFSET(0x1)
-#define GPA1DAT_OFFSET DAT_OFFSET(0x1)
-#define GPA1PUD_OFFSET PUD_OFFSET(0x1)
-#define GPA1DRV_OFFSET DRV_OFFSET(0x1)
-#define GPA1PDNCON_OFFSET PDNCON_OFFSET(0x1)
-#define GPA1PDNPULL_OFFSET PDNPULL_OFFSET(0x1)
-#define GPBCON_OFFSET CON_OFFSET(0x2)
-#define GPBDAT_OFFSET DAT_OFFSET(0x2)
-#define GPBPUD_OFFSET PUD_OFFSET(0x2)
-#define GPBDRV_OFFSET DRV_OFFSET(0x2)
-#define GPBPDNCON_OFFSET PDNCON_OFFSET(0x2)
-#define GPBPDNPULL_OFFSET PDNPULL_OFFSET(0x2)
-#define GPCCON_OFFSET CON_OFFSET(0x3)
-#define GPCDAT_OFFSET DAT_OFFSET(0x3)
-#define GPCPUD_OFFSET PUD_OFFSET(0x3)
-#define GPCDRV_OFFSET DRV_OFFSET(0x3)
-#define GPCPDNCON_OFFSET PDNCON_OFFSET(0x3)
-#define GPCPDNPULL_OFFSET PDNPULL_OFFSET(0x3)
-#define GPDCON_OFFSET CON_OFFSET(0x4)
-#define GPDDAT_OFFSET DAT_OFFSET(0x4)
-#define GPDPUD_OFFSET PUD_OFFSET(0x4)
-#define GPDDRV_OFFSET DRV_OFFSET(0x4)
-#define GPDPDNCON_OFFSET PDNCON_OFFSET(0x4)
-#define GPDPDNPULL_OFFSET PDNPULL_OFFSET(0x4)
-#define GPE0CON_OFFSET CON_OFFSET(0x5)
-#define GPE0DAT_OFFSET DAT_OFFSET(0x5)
-#define GPE0PUD_OFFSET PUD_OFFSET(0x5)
-#define GPE0DRV_OFFSET DRV_OFFSET(0x5)
-#define GPE0PDNCON_OFFSET PDNCON_OFFSET(0x5)
-#define GPE0PDNPULL_OFFSET PDNPULL_OFFSET(0x5)
-#define GPE1CON_OFFSET CON_OFFSET(0x6)
-#define GPE1DAT_OFFSET DAT_OFFSET(0x6)
-#define GPE1PUD_OFFSET PUD_OFFSET(0x6)
-#define GPE1DRV_OFFSET DRV_OFFSET(0x6)
-#define GPE1PDNCON_OFFSET PDNCON_OFFSET(0x6)
-#define GPE1PDNPULL_OFFSET PDNPULL_OFFSET(0x6)
-#define GPF0CON_OFFSET CON_OFFSET(0x7)
-#define GPF0DAT_OFFSET DAT_OFFSET(0x7)
-#define GPF0PUD_OFFSET PUD_OFFSET(0x7)
-#define GPF0DRV_OFFSET DRV_OFFSET(0x7)
-#define GPF0PDNCON_OFFSET PDNCON_OFFSET(0x7)
-#define GPF0PDNPULL_OFFSET PDNPULL_OFFSET(0x7)
-#define GPF1CON_OFFSET CON_OFFSET(0x8)
-#define GPF1DAT_OFFSET DAT_OFFSET(0x8)
-#define GPF1PUD_OFFSET PUD_OFFSET(0x8)
-#define GPF1DRV_OFFSET DRV_OFFSET(0x8)
-#define GPF1PDNCON_OFFSET PDNCON_OFFSET(0x8)
-#define GPF1PDNPULL_OFFSET PDNPULL_OFFSET(0x8)
-#define GPF2CON_OFFSET CON_OFFSET(0x9)
-#define GPF2DAT_OFFSET DAT_OFFSET(0x9)
-#define GPF2PUD_OFFSET PUD_OFFSET(0x9)
-#define GPF2DRV_OFFSET DRV_OFFSET(0x9)
-#define GPF2PDNCON_OFFSET PDNCON_OFFSET(0x9)
-#define GPF2PDNPULL_OFFSET PDNPULL_OFFSET(0x9)
-#define GPF3CON_OFFSET CON_OFFSET(0xA)
-#define GPF3DAT_OFFSET DAT_OFFSET(0xA)
-#define GPF3PUD_OFFSET PUD_OFFSET(0xA)
-#define GPF3DRV_OFFSET DRV_OFFSET(0xA)
-#define GPF3PDNCON_OFFSET PDNCON_OFFSET(0xA)
-#define GPF3PDNPULL_OFFSET PDNPULL_OFFSET(0xA)
-#define GPG0CON_OFFSET CON_OFFSET(0xB)
-#define GPG0DAT_OFFSET DAT_OFFSET(0xB)
-#define GPG0PUD_OFFSET PUD_OFFSET(0xB)
-#define GPG0DRV_OFFSET DRV_OFFSET(0xB)
-#define GPG0PDNCON_OFFSET PDNCON_OFFSET(0xB)
-#define GPG0PDNPULL_OFFSET PDNPULL_OFFSET(0xB)
-#define GPG1CON_OFFSET CON_OFFSET(0xC)
-#define GPG1DAT_OFFSET DAT_OFFSET(0xC)
-#define GPG1PUD_OFFSET PUD_OFFSET(0xC)
-#define GPG1DRV_OFFSET DRV_OFFSET(0xC)
-#define GPG1PDNCON_OFFSET PDNCON_OFFSET(0xC)
-#define GPG1PDNPULL_OFFSET PDNPULL_OFFSET(0xC)
-#define GPG2CON_OFFSET CON_OFFSET(0xD)
-#define GPG2DAT_OFFSET DAT_OFFSET(0xD)
-#define GPG2PUD_OFFSET PUD_OFFSET(0xD)
-#define GPG2DRV_OFFSET DRV_OFFSET(0xD)
-#define GPG2PDNCON_OFFSET PDNCON_OFFSET(0xD)
-#define GPG2PDNPULL_OFFSET PDNPULL_OFFSET(0xD)
-#define GPG3CON_OFFSET CON_OFFSET(0xE)
-#define GPG3DAT_OFFSET DAT_OFFSET(0xE)
-#define GPG3PUD_OFFSET PUD_OFFSET(0xE)
-#define GPG3DRV_OFFSET DRV_OFFSET(0xE)
-#define GPG3PDNCON_OFFSET PDNCON_OFFSET(0xE)
-#define GPG3PDNPULL_OFFSET PDNPULL_OFFSET(0xE)
-#define GPICON_OFFSET CON_OFFSET(0xF)
-#define GPIDAT_OFFSET DAT_OFFSET(0xF)
-#define GPIPUD_OFFSET PUD_OFFSET(0xF)
-#define GPIDRV_OFFSET DRV_OFFSET(0xF)
-#define GPIPDNCON_OFFSET PDNCON_OFFSET(0xF)
-#define GPIPDNPULL_OFFSET PDNPULL_OFFSET(0xF)
-#define GPJ0CON_OFFSET CON_OFFSET(0x10)
-#define GPJ0DAT_OFFSET DAT_OFFSET(0x10)
-#define GPJ0PUD_OFFSET PUD_OFFSET(0x10)
-#define GPJ0DRV_OFFSET DRV_OFFSET(0x10)
-#define GPJ0PDNCON_OFFSET PDNCON_OFFSET(0x11)
-#define GPJ0PDNPULL_OFFSET PDNPULL_OFFSET(0x11)
-#define GPJ1CON_OFFSET CON_OFFSET(0x11)
-#define GPJ1DAT_OFFSET DAT_OFFSET(0x11)
-#define GPJ1PUD_OFFSET PUD_OFFSET(0x11)
-#define GPJ1DRV_OFFSET DRV_OFFSET(0x11)
-#define GPJ1PDNCON_OFFSET PDNCON_OFFSET(0x11)
-#define GPJ1PDNPULL_OFFSET PDNPULL_OFFSET(0x11)
-#define GPJ2CON_OFFSET CON_OFFSET(0x12)
-#define GPJ2DAT_OFFSET DAT_OFFSET(0x12)
-#define GPJ2PUD_OFFSET PUD_OFFSET(0x12)
-#define GPJ2DRV_OFFSET DRV_OFFSET(0x12)
-#define GPJ2PDNCON_OFFSET PDNCON_OFFSET(0x12)
-#define GPJ2PDNPULL_OFFSET PDNPULL_OFFSET(0x12)
-#define GPJ3CON_OFFSET CON_OFFSET(0x13)
-#define GPJ3DAT_OFFSET DAT_OFFSET(0x13)
-#define GPJ3PUD_OFFSET PUD_OFFSET(0x13)
-#define GPJ3DRV_OFFSET DRV_OFFSET(0x13)
-#define GPJ3PDNCON_OFFSET PDNCON_OFFSET(0x13)
-#define GPJ3PDNPULL_OFFSET PDNPULL_OFFSET(0x13)
-#define GPJ4CON_OFFSET CON_OFFSET(0x14)
-#define GPJ4DAT_OFFSET DAT_OFFSET(0x14)
-#define GPJ4PUD_OFFSET PUD_OFFSET(0x14)
-#define GPJ4DRV_OFFSET DRV_OFFSET(0x14)
-#define GPJ4PDNCON_OFFSET PDNCON_OFFSET(0x14)
-#define GPJ4PDNPULL_OFFSET PDNPULL_OFFSET(0x14)
-#define GPK0CON_OFFSET CON_OFFSET(0x15)
-#define GPK0DAT_OFFSET DAT_OFFSET(0x15)
-#define GPK0PUD_OFFSET PUD_OFFSET(0x15)
-#define GPK0DRV_OFFSET DRV_OFFSET(0x15)
-#define GPK0PDNCON_OFFSET PDNCON_OFFSET(0x15)
-#define GPK0PDNPULL_OFFSET PDNPULL_OFFSET(0x15)
-#define GPK1CON_OFFSET CON_OFFSET(0x16)
-#define GPK1DAT_OFFSET DAT_OFFSET(0x16)
-#define GPK1PUD_OFFSET PUD_OFFSET(0x16)
-#define GPK1DRV_OFFSET DRV_OFFSET(0x16)
-#define GPK1PDNCON_OFFSET PDNCON_OFFSET(0x16)
-#define GPK1PDNPULL_OFFSET PDNPULL_OFFSET(0x16)
-#define GPK2CON_OFFSET CON_OFFSET(0x17)
-#define GPK2DAT_OFFSET DAT_OFFSET(0x17)
-#define GPK2PUD_OFFSET PUD_OFFSET(0x17)
-#define GPK2DRV_OFFSET DRV_OFFSET(0x17)
-#define GPK2PDNCON_OFFSET PDNCON_OFFSET(0x17)
-#define GPK2PDNPULL_OFFSET PDNPULL_OFFSET(0x17)
-#define GPK3CON_OFFSET CON_OFFSET(0x18)
-#define GPK3DAT_OFFSET DAT_OFFSET(0x18)
-#define GPK3PUD_OFFSET PUD_OFFSET(0x18)
-#define GPK3DRV_OFFSET DRV_OFFSET(0x18)
-#define GPK3PDNCON_OFFSET PDNCON_OFFSET(0x18)
-#define GPK3PDNPULL_OFFSET PDNPULL_OFFSET(0x18)
-#define GPL0CON_OFFSET CON_OFFSET(0x19)
-#define GPL0DAT_OFFSET DAT_OFFSET(0x19)
-#define GPL0PUD_OFFSET PUD_OFFSET(0x19)
-#define GPL0DRV_OFFSET DRV_OFFSET(0x19)
-#define GPL0PDNCON_OFFSET PDNCON_OFFSET(0x19)
-#define GPL0PDNPULL_OFFSET PDNPULL_OFFSET(0x19)
-#define GPL1CON_OFFSET CON_OFFSET(0x1A)
-#define GPL1DAT_OFFSET DAT_OFFSET(0x1A)
-#define GPL1PUD_OFFSET PUD_OFFSET(0x1A)
-#define GPL1DRV_OFFSET DRV_OFFSET(0x1A)
-#define GPL1PDNCON_OFFSET PDNCON_OFFSET(0x1A)
-#define GPL1PDNPULL_OFFSET PDNPULL_OFFSET(0x1A)
-#define GPL2CON_OFFSET CON_OFFSET(0x1B)
-#define GPL2DAT_OFFSET DAT_OFFSET(0x1B)
-#define GPL2PUD_OFFSET PUD_OFFSET(0x1B)
-#define GPL2DRV_OFFSET DRV_OFFSET(0x1B)
-#define GPL2PDNCON_OFFSET PDNCON_OFFSET(0x1B)
-#define GPL2PDNPULL_OFFSET PDNPULL_OFFSET(0x1B)
-#define GPL3CON_OFFSET CON_OFFSET(0x1C)
-#define GPL3DAT_OFFSET DAT_OFFSET(0x1C)
-#define GPL3PUD_OFFSET PUD_OFFSET(0x1C)
-#define GPL3DRV_OFFSET DRV_OFFSET(0x1C)
-#define GPL3PDNCON_OFFSET PDNCON_OFFSET(0x1C)
-#define GPL3PDNPULL_OFFSET PDNPULL_OFFSET(0x1C)
-#define GPL4CON_OFFSET CON_OFFSET(0x1D)
-#define GPL4DAT_OFFSET DAT_OFFSET(0x1D)
-#define GPL4PUD_OFFSET PUD_OFFSET(0x1D)
-#define GPL4DRV_OFFSET DRV_OFFSET(0x1D)
-#define GPL4PDNCON_OFFSET PDNCON_OFFSET(0x1D)
-#define GPL4PDNPULL_OFFSET PDNPULL_OFFSET(0x1D)
-
-#define MP_0PULL_OFFSET 0x3C8
-#define MP_0DRV_OFFSET 0x3CC
-#define MP_0DNPULL_OFFSET 0x3D4
-#define MP_1PULL_OFFSET 0x3E8
-#define MP_1DRV_OFFSET 0x3EC
-#define MP_1DNPULL_OFFSET 0x3F4
-#define MP_2PULL_OFFSET 0x408
-#define MP_2DRV_OFFSET 0x40C
-#define MP_2DNPULL_OFFSET 0x414
-#define MP_3DRV_OFFSET 0x42C
-#define MP_4DRV_OFFSET 0x44C
-#define MP_5DRV_OFFSET 0x46C
-#define MP_6DRV_OFFSET 0x48C
-#define MP_7DRV_OFFSET 0x4AC
-#define MP_8DRV_OFFSET 0x4CC
-
-#define EINTPEND_OFFSET 0xA00
-
-/*
- * Bus Matrix
- */
-#define ELFIN_MEM_SYS_CFG 0xE0200200
-
-#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12)
-
-#define S3C64XX_MEM_SYS_CFG_NAND 0x0008
-#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT
-
-#define GPA0CON GPx_CON(0x0)
-#define GPA0DAT GPx_DAT(0x0)
-#define GPA0PUD GPx_PUD(0x0)
-#define GPA0DRV GPx_DRV(0x0)
-#define GPA0PDNCON GPx_PDNCON(0x0)
-#define GPA0PDNPULL GPx_PDNPULL(0x0)
-#define GPA1CON GPx_CON(0x1)
-#define GPA1DAT GPx_DAT(0x1)
-#define GPA1PUD GPx_PUD(0x1)
-#define GPA1DRV GPx_DRV(0x1)
-#define GPA1PDNCON GPx_PDNCON(0x1)
-#define GPA1PDNPULL GPx_PDNPULL(0x1)
-#define GPBCON GPx_CON(0x2)
-#define GPBDAT GPx_DAT(0x2)
-#define GPBPUD GPx_PUD(0x2)
-#define GPBDRV GPx_DRV(0x2)
-#define GPBPDNCON GPx_PDNCON(0x2)
-#define GPBPDNPULL GPx_PDNPULL(0x2)
-#define GPCCON GPx_CON(0x3)
-#define GPCDAT GPx_DAT(0x3)
-#define GPCPUD GPx_PUD(0x3)
-#define GPCDRV GPx_DRV(0x3)
-#define GPCPDNCON GPx_PDNCON(0x3)
-#define GPCPDNPULL GPx_PDNPULL(0x3)
-#define GPDCON GPx_CON(0x4)
-#define GPDDAT GPx_DAT(0x4)
-#define GPDPUD GPx_PUD(0x4)
-#define GPDDRV GPx_DRV(0x4)
-#define GPDPDNCON GPx_PDNCON(0x4)
-#define GPDPDNPULL GPx_PDNPULL(0x4)
-#define GPE0CON GPx_CON(0x5)
-#define GPE0DAT GPx_DAT(0x5)
-#define GPE0PUD GPx_PUD(0x5)
-#define GPE0DRV GPx_DRV(0x5)
-#define GPE0PDNCON GPx_PDNCON(0x5)
-#define GPE0PDNPULL GPx_PDNPULL(0x5)
-#define GPE1CON GPx_CON(0x6)
-#define GPE1DAT GPx_DAT(0x6)
-#define GPE1PUD GPx_PUD(0x6)
-#define GPE1DRV GPx_DRV(0x6)
-#define GPE1PDNCON GPx_PDNCON(0x6)
-#define GPE1PDNPULL GPx_PDNPULL(0x6)
-#define GPF0CON GPx_CON(0x7)
-#define GPF0DAT GPx_DAT(0x7)
-#define GPF0PUD GPx_PUD(0x7)
-#define GPF0DRV GPx_DRV(0x7)
-#define GPF0PDNCON GPx_PDNCON(0x7)
-#define GPF0PDNPULL GPx_PDNPULL(0x7)
-#define GPF1CON GPx_CON(0x8)
-#define GPF1DAT GPx_DAT(0x8)
-#define GPF1PUD GPx_PUD(0x8)
-#define GPF1DRV GPx_DRV(0x8)
-#define GPF1PDNCON GPx_PDNCON(0x8)
-#define GPF1PDNPULL GPx_PDNPULL(0x8)
-#define GPF2CON GPx_CON(0x9)
-#define GPF2DAT GPx_DAT(0x9)
-#define GPF2PUD GPx_PUD(0x9)
-#define GPF2DRV GPx_DRV(0x9)
-#define GPF2PDNCON GPx_PDNCON(0x9)
-#define GPF2PDNPULL GPx_PDNPULL(0x9)
-#define GPF3CON GPx_CON(0xA)
-#define GPF3DAT GPx_DAT(0xA)
-#define GPF3PUD GPx_PUD(0xA)
-#define GPF3DRV GPx_DRV(0xA)
-#define GPF3PDNCON GPx_PDNCON(0xA)
-#define GPF3PDNPULL GPx_PDNPULL(0xA)
-#define GPG0CON GPx_CON(0xB)
-#define GPG0DAT GPx_DAT(0xB)
-#define GPG0PUD GPx_PUD(0xB)
-#define GPG0DRV GPx_DRV(0xB)
-#define GPG0PDNCON GPx_PDNCON(0xB)
-#define GPG0PDNPULL GPx_PDNPULL(0xB)
-#define GPG1CON GPx_CON(0xC)
-#define GPG1DAT GPx_DAT(0xC)
-#define GPG1PUD GPx_PUD(0xC)
-#define GPG1DRV GPx_DRV(0xC)
-#define GPG1PDNCON GPx_PDNCON(0xC)
-#define GPG1PDNPULL GPx_PDNPULL(0xC)
-#define GPG2CON GPx_CON(0xD)
-#define GPG2DAT GPx_DAT(0xD)
-#define GPG2PUD GPx_PUD(0xD)
-#define GPG2DRV GPx_DRV(0xD)
-#define GPG2PDNCON GPx_PDNCON(0xD)
-#define GPG2PDNPULL GPx_PDNPULL(0xD)
-#define GPG3CON GPx_CON(0xE)
-#define GPG3DAT GPx_DAT(0xE)
-#define GPG3PUD GPx_PUD(0xE)
-#define GPG3DRV GPx_DRV(0xE)
-#define GPG3PDNCON GPx_PDNCON(0xE)
-#define GPG3PDNPULL GPx_PDNPULL(0xE)
-#define GPICON GPx_CON(0xF)
-#define GPIDAT GPx_DAT(0xF)
-#define GPIPUD GPx_PUD(0xF)
-#define GPIDRV GPx_DRV(0xF)
-#define GPIPDNCON GPx_PDNCON(0xF)
-#define GPIPDNPULL GPx_PDNPULL(0xF)
-#define GPJ0CON GPx_CON(0x10)
-#define GPJ0DAT GPx_DAT(0x10)
-#define GPJ0PUD GPx_PUD(0x10)
-#define GPJ0DRV GPx_DRV(0x10)
-#define GPJ0PDNCON GPx_PDNCON(0x11)
-#define GPJ0PDNPULL GPx_PDNPULL(0x11)
-#define GPJ1CON GPx_CON(0x11)
-#define GPJ1DAT GPx_DAT(0x11)
-#define GPJ1PUD GPx_PUD(0x11)
-#define GPJ1DRV GPx_DRV(0x11)
-#define GPJ1PDNCON GPx_PDNCON(0x11)
-#define GPJ1PDNPULL GPx_PDNPULL(0x11)
-#define GPJ2CON GPx_CON(0x12)
-#define GPJ2DAT GPx_DAT(0x12)
-#define GPJ2PUD GPx_PUD(0x12)
-#define GPJ2DRV GPx_DRV(0x12)
-#define GPJ2PDNCON GPx_PDNCON(0x12)
-#define GPJ2PDNPULL GPx_PDNPULL(0x12)
-#define GPJ3CON GPx_CON(0x13)
-#define GPJ3DAT GPx_DAT(0x13)
-#define GPJ3PUD GPx_PUD(0x13)
-#define GPJ3DRV GPx_DRV(0x13)
-#define GPJ3PDNCON GPx_PDNCON(0x13)
-#define GPJ3PDNPULL GPx_PDNPULL(0x13)
-#define GPJ4CON GPx_CON(0x14)
-#define GPJ4DAT GPx_DAT(0x14)
-#define GPJ4PUD GPx_PUD(0x14)
-#define GPJ4DRV GPx_DRV(0x14)
-#define GPJ4PDNCON GPx_PDNCON(0x14)
-#define GPJ4PDNPULL GPx_PDNPULL(0x14)
-#define GPK0CON GPx_CON(0x15)
-#define GPK0DAT GPx_DAT(0x15)
-#define GPK0PUD GPx_PUD(0x15)
-#define GPK0DRV GPx_DRV(0x15)
-#define GPK0PDNCON GPx_PDNCON(0x15)
-#define GPK0PDNPULL GPx_PDNPULL(0x15)
-#define GPK1CON GPx_CON(0x16)
-#define GPK1DAT GPx_DAT(0x16)
-#define GPK1PUD GPx_PUD(0x16)
-#define GPK1DRV GPx_DRV(0x16)
-#define GPK1PDNCON GPx_PDNCON(0x16)
-#define GPK1PDNPULL GPx_PDNPULL(0x16)
-#define GPK2CON GPx_CON(0x17)
-#define GPK2DAT GPx_DAT(0x17)
-#define GPK2PUD GPx_PUD(0x17)
-#define GPK2DRV GPx_DRV(0x17)
-#define GPK2PDNCON GPx_PDNCON(0x17)
-#define GPK2PDNPULL GPx_PDNPULL(0x17)
-#define GPK3CON GPx_CON(0x18)
-#define GPK3DAT GPx_DAT(0x18)
-#define GPK3PUD GPx_PUD(0x18)
-#define GPK3DRV GPx_DRV(0x18)
-#define GPK3PDNCON GPx_PDNCON(0x18)
-#define GPK3PDNPULL GPx_PDNPULL(0x18)
-#define GPL0CON GPx_CON(0x19)
-#define GPL0DAT GPx_DAT(0x19)
-#define GPL0PUD GPx_PUD(0x19)
-#define GPL0DRV GPx_DRV(0x19)
-#define GPL0PDNCON GPx_PDNCON(0x19)
-#define GPL0PDNPULL GPx_PDNPULL(0x19)
-#define GPL1CON GPx_CON(0x1A)
-#define GPL1DAT GPx_DAT(0x1A)
-#define GPL1PUD GPx_PUD(0x1A)
-#define GPL1DRV GPx_DRV(0x1A)
-#define GPL1PDNCON GPx_PDNCON(0x1A)
-#define GPL1PDNPULL GPx_PDNPULL(0x1A)
-#define GPL2CON GPx_CON(0x1B)
-#define GPL2DAT GPx_DAT(0x1B)
-#define GPL2PUD GPx_PUD(0x1B)
-#define GPL2DRV GPx_DRV(0x1B)
-#define GPL2PDNCON GPx_PDNCON(0x1B)
-#define GPL2PDNPULL GPx_PDNPULL(0x1B)
-#define GPL3CON GPx_CON(0x1C)
-#define GPL3DAT GPx_DAT(0x1C)
-#define GPL3PUD GPx_PUD(0x1C)
-#define GPL3DRV GPx_DRV(0x1C)
-#define GPL3PDNCON GPx_PDNCON(0x1C)
-#define GPL3PDNPULL GPx_PDNPULL(0x1C)
-#define GPL4CON GPx_CON(0x1D)
-#define GPL4DAT GPx_DAT(0x1D)
-#define GPL4PUD GPx_PUD(0x1D)
-#define GPL4DRV GPx_DRV(0x1D)
-#define GPL4PDNCON GPx_PDNCON(0x1D)
-#define GPL4PDNPULL GPx_PDNPULL(0x1D)
-
-/*
- * Memory controller
- */
-#define ELFIN_SROM_BASE 0xE7000000
-
-#define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0)
-#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4)
-#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8)
-#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC)
-#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10)
-#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14)
-#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18)
-
-/*
- * SDRAM Controller
- */
-#define ELFIN_DMC0_BASE 0x7e000000
-#define ELFIN_DMC1_BASE 0x7e001000
-
-#define INDEX_DMC_MEMC_STATUS 0x00
-#define INDEX_DMC_MEMC_CMD 0x04
-#define INDEX_DMC_DIRECT_CMD 0x08
-#define INDEX_DMC_MEMORY_CFG 0x0C
-#define INDEX_DMC_REFRESH_PRD 0x10
-#define INDEX_DMC_CAS_LATENCY 0x14
-#define INDEX_DMC_T_DQSS 0x18
-#define INDEX_DMC_T_MRD 0x1C
-#define INDEX_DMC_T_RAS 0x20
-#define INDEX_DMC_T_RC 0x24
-#define INDEX_DMC_T_RCD 0x28
-#define INDEX_DMC_T_RFC 0x2C
-#define INDEX_DMC_T_RP 0x30
-#define INDEX_DMC_T_RRD 0x34
-#define INDEX_DMC_T_WR 0x38
-#define INDEX_DMC_T_WTR 0x3C
-#define INDEX_DMC_T_XP 0x40
-#define INDEX_DMC_T_XSR 0x44
-#define INDEX_DMC_T_ESR 0x48
-#define INDEX_DMC_MEMORY_CFG2 0x4C
-#define INDEX_DMC_CHIP_0_CFG 0x200
-#define INDEX_DMC_CHIP_1_CFG 0x204
-#define INDEX_DMC_CHIP_2_CFG 0x208
-#define INDEX_DMC_CHIP_3_CFG 0x20C
-#define INDEX_DMC_USER_STATUS 0x300
-#define INDEX_DMC_USER_CONFIG 0x304
-
-/*
- * Memory Chip direct command
- */
-#define DMC_NOP0 0x0c0000
-#define DMC_NOP1 0x1c0000
-#define DMC_PA0 0x000000 /* Precharge all */
-#define DMC_PA1 0x100000
-#define DMC_AR0 0x040000 /* Autorefresh */
-#define DMC_AR1 0x140000
-#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */
-#define DMC_SDR_MR1 0x180032
-#define DMC_DDR_MR0 0x080162
-#define DMC_DDR_MR1 0x180162
-#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */
-#define DMC_mDDR_MR1 0x180032
-#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */
-#define DMC_mSDR_EMR1 0x1a0000
-#define DMC_DDR_EMR0 0x090000
-#define DMC_DDR_EMR1 0x190000
-#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */
-#define DMC_mDDR_EMR1 0x1a0000
-
-/*
- * Definitions for memory configuration
- * Set memory configuration
- * active_chips = 1'b0 (1 chip)
- * qos_master_chip = 3'b000(ARID[3:0])
- * memory burst = 3'b010(burst 4)
- * stop_mem_clock = 1'b0(disable dynamical stop)
- * auto_power_down = 1'b0(disable auto power-down mode)
- * power_down_prd = 6'b00_0000(0 cycle for auto power-down)
- * ap_bit = 1'b0 (bit position of auto-precharge is 10)
- * row_bits = 3'b010(# row address 13)
- * column_bits = 3'b010(# column address 10 )
- *
- * Set user configuration
- * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR
- *
- * Set chip select for chip [n]
- * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff
- * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24]
- */
-
-/*
- * Nand flash controller
- */
-#define ELFIN_NAND_BASE 0x70200000
-
-#define NFCONF_OFFSET 0x00
-#define NFCONT_OFFSET 0x04
-#define NFCMMD_OFFSET 0x08
-#define NFADDR_OFFSET 0x0c
-#define NFDATA_OFFSET 0x10
-#define NFMECCDATA0_OFFSET 0x14
-#define NFMECCDATA1_OFFSET 0x18
-#define NFSECCDATA0_OFFSET 0x1c
-#define NFSBLK_OFFSET 0x20
-#define NFEBLK_OFFSET 0x24
-#define NFSTAT_OFFSET 0x28
-#define NFESTAT0_OFFSET 0x2c
-#define NFESTAT1_OFFSET 0x30
-#define NFMECC0_OFFSET 0x34
-#define NFMECC1_OFFSET 0x38
-#define NFSECC_OFFSET 0x3c
-#define NFMLCBITPT_OFFSET 0x40
-
-#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET)
-#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET)
-#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET)
-#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET)
-#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
-#define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
-#define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
-#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET)
-#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET)
-#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET)
-#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET)
-#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET)
-#define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET)
-#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET)
-#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET)
-#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
-
-#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET)
-#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET)
-#define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET)
-#define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET)
-#define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
-#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
-#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
-#define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET)
-#define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET)
-#define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET)
-#define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET)
-#define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET)
-#define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET)
-#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET)
-#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET)
-#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
-
-#define NFCONF_ECC_4BIT (1<<24)
-
-#define NFCONT_ECC_ENC (1<<18)
-#define NFCONT_WP (1<<16)
-#define NFCONT_MECCLOCK (1<<7)
-#define NFCONT_SECCLOCK (1<<6)
-#define NFCONT_INITMECC (1<<5)
-#define NFCONT_INITSECC (1<<4)
-#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC)
-#define NFCONT_CS_ALT (1<<2)
-#define NFCONT_CS (1<<1)
-#define NFCONT_ENABLE (1<<0)
-
-#define NFSTAT_ECCENCDONE (1<<7)
-#define NFSTAT_ECCDECDONE (1<<6)
-#define NFSTAT_RnB (1<<0)
-
-#define NFESTAT0_ECCBUSY (1<<31)
-
-/*
- * Interrupt
- */
-#define ELFIN_VIC0_BASE_ADDR 0xE4000000
-#define ELFIN_VIC1_BASE_ADDR 0xE4100000
-#define ELFIN_VIC2_BASE_ADDR 0xE4200000
-
-#define oINTMOD 0x0C /* VIC INT SELECT (IRQ or FIQ) */
-#define oINTUNMSK 0x10 /* VIC INT EN (write 1 to unmask) */
-#define oINTMSK 0x14 /* VIC INT EN CLEAR (write 1 to mask) */
-#define oINTSUBMSK 0x1C /* VIC SOFT INT CLEAR */
-#define oVECTADDR 0xF00 /* VIC ADDRESS */
-
-/*
- * Watchdog timer
- */
-#define ELFIN_WATCHDOG_BASE 0x7E004000
-
-#define WTCON_REG __REG(0x7E004004)
-#define WTDAT_REG __REG(0x7E004008)
-#define WTCNT_REG __REG(0x7E00400C)
-
-
-/*
- * UART
- */
-#define ELFIN_UART_BASE 0xEC000000
-
-#define ELFIN_UARTx_OFFSET(x) (ELFIN_UART_BASE + x * 0x400)
-
-#define ULCON_OFFSET 0x00
-#define UCON_OFFSET 0x04
-#define UFCON_OFFSET 0x08
-#define UMCON_OFFSET 0x0C
-#define UTRSTAT_OFFSET 0x10
-#define UERSTAT_OFFSET 0x14
-#define UFSTAT_OFFSET 0x18
-#define UMSTAT_OFFSET 0x1C
-#define UTXH_OFFSET 0x20
-#define URXH_OFFSET 0x24
-#define UBRDIV_OFFSET 0x28
-#define UDIVSLOT_OFFSET 0x2C
-#define UINTP_OFFSET 0x30
-#define UINTSP_OFFSET 0x34
-#define UINTM_OFFSET 0x38
-
-#define UTRSTAT_TX_EMPTY (1 << 2)
-#define UTRSTAT_RX_READY (1 << 0)
-#define UART_ERR_MASK 0xF
-
-/*
- * PWM timer
- */
-#define ELFIN_TIMER_BASE 0xEA000000
-
-#define TCFG0_REG __REG(0x7F006000)
-#define TCFG1_REG __REG(0x7F006004)
-#define TCON_REG __REG(0x7F006008)
-#define TCNTB0_REG __REG(0x7F00600c)
-#define TCMPB0_REG __REG(0x7F006010)
-#define TCNTO0_REG __REG(0x7F006014)
-#define TCNTB1_REG __REG(0x7F006018)
-#define TCMPB1_REG __REG(0x7F00601c)
-#define TCNTO1_REG __REG(0x7F006020)
-#define TCNTB2_REG __REG(0x7F006024)
-#define TCMPB2_REG __REG(0x7F006028)
-#define TCNTO2_REG __REG(0x7F00602c)
-#define TCNTB3_REG __REG(0x7F006030)
-#define TCMPB3_REG __REG(0x7F006034)
-#define TCNTO3_REG __REG(0x7F006038)
-#define TCNTB4_REG __REG(0x7F00603c)
-#define TCNTO4_REG __REG(0x7F006040)
-
-/* Fields */
-#define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */
-#define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */
-#define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */
-#define fTCFG1_MUX4 Fld(4, 16)
-/* bits */
-#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE)
-#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1)
-#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0)
-#define TCFG1_MUX4(x) FInsrt((x), fTCFG1_MUX4)
-#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */
-#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */
-#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */
-#define COUNT_4_ON (TCON_4_ONOFF * 1)
-#define COUNT_4_OFF (TCON_4_ONOFF * 0)
-#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */
-#define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1)
-#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO)
-#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */
-#define TIMER3_IVT_ON (TCON_3_INVERT * 1)
-#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT))
-#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */
-#define TIMER3_MANUP (TCON_3_MAN*1)
-#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN))
-#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */
-#define TIMER3_ON (TCON_3_ONOFF * 1)
-#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF))
-
-#if defined(CONFIG_CLK_400_100_50)
-#define STARTUP_AMDIV 400
-#define STARTUP_MDIV 400
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#elif defined(CONFIG_CLK_400_133_66)
-#define STARTUP_AMDIV 400
-#define STARTUP_MDIV 533
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#elif defined(CONFIG_CLK_533_133_66)
-#define STARTUP_AMDIV 533
-#define STARTUP_MDIV 533
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#elif defined(CONFIG_CLK_667_133_66)
-#define STARTUP_AMDIV 667
-#define STARTUP_MDIV 533
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#endif
-
-#define STARTUP_PCLKDIV 3
-#define STARTUP_HCLKX2DIV 1
-#define STARTUP_HCLKDIV 1
-#define STARTUP_MPLLDIV 1
-#define STARTUP_APLLDIV 0
-
-#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \
- (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV)
-#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
- (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
- STARTUP_PDIV) * STARTUP_MDIV)
-
-#if defined(CONFIG_SYNC_MODE)
-#define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
- (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
- STARTUP_PDIV) * STARTUP_MDIV)
-#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
- (STARTUP_HCLKDIV + 1))
-#else
-#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \
- (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
- STARTUP_PDIV) * STARTUP_AMDIV)
-#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
- (STARTUP_HCLKDIV + 1))
-#endif
-
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */
-#define DMC1_MEM_CFG2 0xB45
-#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */
-#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
-
-/* Memory Parameters */
-/* DDR Parameters */
-#define DDR_tREFRESH 7800 /* ns */
-#define DDR_tRAS 45 /* ns (min: 45ns)*/
-#define DDR_tRC 68 /* ns (min: 67.5ns)*/
-#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
-#define DDR_tRFC 80 /* ns (min: 80ns)*/
-#define DDR_tRP 23 /* ns (min: 22.5ns)*/
-#define DDR_tRRD 15 /* ns (min: 15ns)*/
-#define DDR_tWR 15 /* ns (min: 15ns)*/
-#define DDR_tXSR 120 /* ns (min: 120ns)*/
-#define DDR_CASL 3 /* CAS Latency 3 */
-
-/*
- * mDDR memory configuration
- */
-
-#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000)
-
-#define DMC_DDR_BA_EMRS 2
-#define DMC_DDR_MEM_CASLAT 3
-/* 6 Set Cas Latency to 3 */
-#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1)
-/* Min 0.75 ~ 1.25 */
-#define DMC_DDR_t_DQSS 1
-/* Min 2 tck */
-#define DMC_DDR_t_MRD 2
-/* 7, Min 45ns */
-#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1)
-/* 10, Min 67.5ns */
-#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1)
-/* 4,5(TRM), Min 22.5ns */
-#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1)
-#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3)
-/* 11,18(TRM) Min 80ns */
-#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1)
-#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5)
-/* 4, 5(TRM) Min 22.5ns */
-#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1)
-#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3)
-/* 3, Min 15ns */
-#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1)
-/* Min 15ns */
-#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1)
-#define DMC_DDR_t_WTR 2
-/* 1tck + tIS(1.5ns) */
-#define DMC_DDR_t_XP 2
-/* 17, Min 120ns */
-#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1)
-#define DMC_DDR_t_ESR DMC_DDR_t_XSR
-/* TRM 2656 */
-#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH))
-/* 2b01 : mDDR */
-#define DMC_DDR_USER_CONFIG 1
-
-#ifndef __ASSEMBLY__
-enum s5pc1xx_uarts_nr {
- S5PC1XX_UART0,
- S5PC1XX_UART1,
- S5PC1XX_UART2,
- S5PC1XX_UART3,
-};
-
-#include "s5pc1x0.h"
-
-static inline s5pc1xx_uart *s5pc1xx_get_base_uart(enum s5pc1xx_uarts_nr nr)
-{
- return (s5pc1xx_uart *)(ELFIN_UART_BASE + (nr * 0x400));
-}
-#endif
-
-#endif
-
-
-
-
projects / kernel / u-boot.git / commitdiff