return PTR_ERR(dc->vout_top_lcd);
}
- dc->init_finished = false;
+ dc->init_count = 0;
/*
ret = clk_prepare_enable(dc->vout_top_lcd);
struct dc_hw_display display;
int ret;
-
- if (dc->init_finished == false) {
+ if (dc->init_count == 0) {
ret = dc_vout_clk_enable(dev, dc);
if (ret)
dev_err(dev, "failed to enable clock\n");
if (ret)
dev_err(dev, "failed to init DC HW\n");
- dc->init_finished = true;
}
+ dc->init_count++;
+
display.bus_format = crtc_state->output_fmt;
display.h_active = mode->hdisplay;
display.h_total = mode->htotal;
display.enable = true;
- clk_set_rate(dc->dc8200_pix0, mode->clock * 1000);
- dc->pix_clk_rate = mode->clock;
+ if(display.id == 1)
+ {
+ clk_set_rate(dc->dc8200_pix0, mode->clock * 1000);
+ clk_set_parent(dc->dc8200_clk_pix1, dc->dc8200_pix0);
+ clk_set_parent(dc->vout_top_lcd, dc->dc8200_clk_pix1_out);
+ }else{
+ clk_set_parent(dc->dc8200_clk_pix0, dc->hdmitx0_pixelclk);
+ }
if (crtc_state->encoder_type == DRM_MODE_ENCODER_DSI){
- /*
- if (dc->pix_clk_rate != mode->clock) {
- clk_set_rate(dc->dc8200_pix0, mode->clock * 1000);
- dc->pix_clk_rate = mode->clock;
- }
- */
-
- clk_set_parent(dc->dc8200_clk_pix1, dc->dc8200_pix0);
- udelay(1000);
dc_hw_set_out(&dc->hw, OUT_DPI, display.id);
} else {
- /*
- if (dc->pix_clk_rate != mode->clock) {
- clk_set_rate(dc->dc8200_pix0, mode->clock * 1000);
- dc->pix_clk_rate = mode->clock;
- }
- */
-
- clk_set_parent(dc->dc8200_clk_pix1, dc->dc8200_pix0);
- clk_set_parent(dc->vout_top_lcd, dc->dc8200_clk_pix1_out);
- clk_set_parent(dc->dc8200_clk_pix0, dc->hdmitx0_pixelclk);
dc_hw_set_out(&dc->hw, OUT_DP, display.id);
}
dc_hw_enable_mmu_prefetch(&dc->hw, false);
#endif
- //regmap_update_bits(dc->dss_regmap, 0x4, BIT(20), 1 << 20);
-
- //regmap_update_bits(dc->dss_regmap, 0x8, BIT(3), 1 << 3);
-
dc_hw_setup_display(&dc->hw, &display);
-
}
static void vs_dc_disable(struct device *dev, struct drm_crtc *crtc)
display.id = to_vs_display_id(dc, crtc);
display.enable = false;
- if (dc->init_finished == true) {
+ dc->init_count--;
+ dc_hw_setup_display(&dc->hw, &display);
- dc_hw_setup_display(&dc->hw, &display);
+ if (dc->init_count == 0) {
- clk_disable_unprepare(dc->vout_top_lcd);
- /*dc8200 asrt*/
vs_dc8200_reset_assert(dc);
/*dc8200 clk disable*/
/*297000000 reset the pixclk channel*/
clk_set_rate(dc->dc8200_pix0, 1000);
-
/*reset the parent pixclk channel*/
clk_set_parent(dc->dc8200_clk_pix1, dc->hdmitx0_pixelclk);
clk_set_parent(dc->vout_top_lcd, dc->dc8200_clk_pix0_out);
clk_set_parent(dc->dc8200_clk_pix0, dc->dc8200_pix0);
- dc->init_finished = false;
}
}
if (IS_ERR(dc->hw.reg_base))
return PTR_ERR(dc->hw.reg_base);
- dc->pmu_base = ioremap(0x17030000, 0x10000);
- if (IS_ERR(dc->pmu_base))
- return PTR_ERR(dc->pmu_base);
-
#ifdef CONFIG_VERISILICON_MMU
dc->hw.mmu_base = devm_platform_ioremap_resource(pdev, 2);
if (IS_ERR(dc->hw.mmu_base))
struct dc_dec400l dec400l;
#endif
- void __iomem *pmu_base;
-
- unsigned int pix_clk_rate; /* in KHz */
-
- struct reset_control *resets;
- struct clk_bulk_data *clks;
- int num_clks;
-
-
bool first_frame;
struct vs_dc_plane planes[PLANE_NUM];
struct clk *axicfg0_axi;
struct clk *disp_axi;
struct clk *stg_axi;
-
struct clk *vout_src;
struct clk *vout_axi;
struct clk *ahb1;
struct clk *vout_ahb;
struct clk *hdmitx0_mclk;
struct clk *bclk_mst;
-
struct clk *dc8200_clk_pix0;
struct clk *dc8200_clk_pix1;
struct clk *dc8200_axi;
struct clk *dc8200_core;
struct clk *dc8200_ahb;
-
struct clk *vout_top_axi;
struct clk *vout_top_lcd;
-
struct clk *hdmitx0_pixelclk;
struct clk *dc8200_pix0;
struct clk *dc8200_clk_pix0_out;
struct clk *dc8200_clk_pix1_out;
-
struct reset_control *vout_resets;
-
-//20221014
struct reset_control *dc8200_rst_axi;
struct reset_control *dc8200_rst_core;
struct reset_control *dc8200_rst_ahb;
-
struct reset_control *rst_vout_src;
struct reset_control *noc_disp;
-//20221014
-
struct regmap *dss_regmap;
- bool init_finished;
+ int init_count;
};
extern struct platform_driver dc_platform_driver;
-extern struct platform_driver starfive_dsi_platform_driver;
-extern int init_seeed_panel(void);
-extern void exit_seeed_panel(void);
+
#endif /* __VS_DC_H__ */
&vs_obj->dma_addr, GFP_KERNEL,
vs_obj->dma_attrs);
- printk("Allocated coherent memory, vaddr: 0x%0llX, paddr: 0x%0llX\n", (u64)vs_obj->cookie, vs_obj->dma_addr);
+ DRM_DEV_DEBUG(dev->dev,"Allocated coherent memory, vaddr: 0x%0llX, paddr: 0x%0llX, size: %d\n",
+ (u64)vs_obj->cookie,vs_obj->dma_addr,vs_obj->size);
if (!vs_obj->cookie) {
#ifdef CONFIG_VERISILICON_MMU
ret = get_pages(nr_pages, vs_obj);
vs_obj->iova = vs_obj->dma_addr;
#endif
- printk("====> %s, %d.vs_obj->get_pages = %d\n", __func__, __LINE__, vs_obj->get_pages);
-
if (!vs_obj->get_pages) {
ret = dma_get_sgtable_attrs(to_dma_dev(dev), &sgt,
vs_obj->cookie, vs_obj->dma_addr,
/* for costum 10bit format with no bit gaps */
args->pitch = pitch;
args->size = PAGE_ALIGN(args->pitch * args->height);
- printk("vs_gem_dumb_create size = %llx\n", args->size);
vs_obj = vs_gem_create_with_handle(dev, file, args->size,
&args->handle);
return PTR_ERR_OR_ZERO(vs_obj);