if (quirks & MIDGARD_BROKEN_LOD)
NIR_PASS_V(nir, midgard_nir_lod_errata);
+ NIR_PASS_V(nir, nir_lower_legacy_atomics);
+
/* Midgard image ops coordinates are 16-bit instead of 32-bit */
NIR_PASS_V(nir, midgard_nir_lower_image_bitsize);
NIR_PASS(progress, nir, nir_copy_prop);
NIR_PASS(progress, nir, nir_opt_dce);
- NIR_PASS(progress, nir, nir_lower_legacy_atomics);
/* Backend scheduler is purely local, so do some global optimizations
* to reduce register pressure. */
switch (intr->intrinsic) {
case nir_intrinsic_image_load:
case nir_intrinsic_image_store:
- case nir_intrinsic_image_atomic_add:
- case nir_intrinsic_image_atomic_and:
- case nir_intrinsic_image_atomic_comp_swap:
- case nir_intrinsic_image_atomic_exchange:
- case nir_intrinsic_image_atomic_imax:
- case nir_intrinsic_image_atomic_imin:
- case nir_intrinsic_image_atomic_or:
- case nir_intrinsic_image_atomic_umax:
- case nir_intrinsic_image_atomic_umin:
- case nir_intrinsic_image_atomic_xor:
+ case nir_intrinsic_image_atomic:
+ case nir_intrinsic_image_atomic_swap:
break;
default:
return false;