Fixes an assertion:
llc: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2200: llvm::KnownBits llvm::SelectionDAG::computeKnownBits(llvm::SDValue, const llvm::APInt&, unsigned int) const: Assertion `(!Op.getValueType().isVector() || NumElts == Op.getValueType().getVectorNumElements()) && "Unexpected vector size"' failed.
Committed on behalf of: @pendingchaos (Rhys Perry)
Differential Revision: https://reviews.llvm.org/D55223
llvm-svn: 348574
break;
SDValue N0 = Op.getOperand(0);
- Known = computeKnownBits(N0, DemandedElts, Depth + 1);
+ Known = computeKnownBits(N0, Depth + 1);
if (N0.getValueSizeInBits() != BitWidth)
Known = Known.trunc(BitWidth);
--- /dev/null
+; RUN: llc -march=amdgcn -mcpu=gfx802 -verify-machineinstrs < %s | FileCheck %s
+
+; CHECK: s_waitcnt
+define <2 x i16> @main(<2 x float>) #0 {
+ %2 = bitcast <2 x float> %0 to <4 x i16>
+ %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <2 x i32> <i32 0, i32 undef>
+ %4 = extractelement <4 x i16> %2, i32 0
+ %5 = insertelement <2 x i16> %3, i16 %4, i32 0
+ ret <2 x i16> %5
+}
+