riscv: dts: microchip: add a devicetree for aries' m100pfsevp

Add device trees for both configs used by the Aries Embedded
M100PFSEVP. The M100OFSEVP consists of a MPFS250T on a SOM,
featuring:
- 2GB DDR4 SDRAM dedicated to the HMS
- 512MB DDR4 SDRAM dedicated to the FPGA
- 32 MB SPI NOR Flash
- 4 GByte eMMC

and a carrier board with:
- 2x Gigabit Ethernet
- USB
- 2x UART
- 2x CAN
- TFT connector
- HSMC extension connector
- 3x PMOD extension connectors
- microSD-card slot

Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes
Link: https://www.aries-embedded.com/evaluation-kit/fpga/polarfire-microchip-soc-fpga-m100pfsevp-riscv-hsmc-pmod
Link: https://downloads.aries-embedded.de/products/M100PFS/Hardware/M100PFSEVP-Schematics.pdf
Co-developed-by: Wolfgang Grandegger <wg@aries-embedded.de>
Signed-off-by: Wolfgang Grandegger <wg@aries-embedded.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index f18477b..7427a20 100644 (file)
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb
 obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
new file mode 100644 (file)
index 0000000..7b9ee13
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2022 Microchip Technology Inc */
+
+/ {
+       fabric_clk3: fabric-clk3 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <62500000>;
+       };
+
+       fabric_clk1: fabric-clk1 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <125000000>;
+       };
+
+       pcie: pcie@2000000000 {
+               compatible = "microchip,pcie-host-1.0";
+               #address-cells = <0x3>;
+               #interrupt-cells = <0x1>;
+               #size-cells = <0x2>;
+               device_type = "pci";
+               reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+               reg-names = "cfg", "apb";
+               bus-range = <0x0 0x7f>;
+               interrupt-parent = <&plic>;
+               interrupts = <119>;
+               interrupt-map = <0 0 0 1 &pcie_intc 0>,
+                               <0 0 0 2 &pcie_intc 1>,
+                               <0 0 0 3 &pcie_intc 2>,
+                               <0 0 0 4 &pcie_intc 3>;
+               interrupt-map-mask = <0 0 0 7>;
+               clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
+               clock-names = "fic0", "fic1", "fic3";
+               ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+               msi-parent = <&pcie>;
+               msi-controller;
+               status = "disabled";
+               pcie_intc: interrupt-controller {
+                       #address-cells = <0>;
+                       #interrupt-cells = <1>;
+                       interrupt-controller;
+               };
+       };
+};

diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
new file mode 100644 (file)
index 0000000..184cb36
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Original all-in-one devicetree:
+ * Copyright (C) 2021-2022 - Wolfgang Grandegger <wg@aries-embedded.de>
+ * Rewritten to use includes:
+ * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
+ */
+/dts-v1/;
+
+#include "mpfs.dtsi"
+#include "mpfs-m100pfs-fabric.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define MTIMER_FREQ    1000000
+
+/ {
+       model = "Aries Embedded M100PFEVPS";
+       compatible = "aries,m100pfsevp", "microchip,mpfs";
+
+       aliases {
+               ethernet0 = &mac0;
+               ethernet1 = &mac1;
+               serial0 = &mmuart0;
+               serial1 = &mmuart1;
+               serial2 = &mmuart2;
+               serial3 = &mmuart3;
+               serial4 = &mmuart4;
+               gpio0 = &gpio0;
+               gpio1 = &gpio2;
+       };
+
+       chosen {
+               stdout-path = "serial1:115200n8";
+       };
+
+       cpus {
+               timebase-frequency = <MTIMER_FREQ>;
+       };
+
+       ddrc_cache_lo: memory@80000000 {
+               device_type = "memory";
+               reg = <0x0 0x80000000 0x0 0x40000000>;
+       };
+       ddrc_cache_hi: memory@1040000000 {
+               device_type = "memory";
+               reg = <0x10 0x40000000 0x0 0x40000000>;
+       };
+};
+
+&can0 {
+       status = "okay";
+};
+
+&i2c0 {
+       status = "okay";
+};
+
+&i2c1 {
+       status = "okay";
+};
+
+&gpio0 {
+       interrupts = <13>, <14>, <15>, <16>,
+                    <17>, <18>, <19>, <20>,
+                    <21>, <22>, <23>, <24>,
+                    <25>, <26>;
+       ngpios = <14>;
+       status = "okay";
+
+       pmic-irq-hog {
+               gpio-hog;
+               gpios = <13 0>;
+               input;
+       };
+
+       /* Set to low for eMMC, high for SD-card */
+       mmc-sel-hog {
+               gpio-hog;
+               gpios = <12 0>;
+               output-high;
+       };
+};
+
+&gpio2 {
+       interrupts = <13>, <14>, <15>, <16>,
+                    <17>, <18>, <19>, <20>,
+                    <21>, <22>, <23>, <24>,
+                    <25>, <26>, <27>, <28>,
+                    <29>, <30>, <31>, <32>,
+                    <33>, <34>, <35>, <36>,
+                    <37>, <38>, <39>, <40>,
+                    <41>, <42>, <43>, <44>;
+       status = "okay";
+};
+
+&mac0 {
+       status = "okay";
+       phy-mode = "gmii";
+       phy-handle = <&phy0>;
+       phy0: ethernet-phy@0 {
+               reg = <0>;
+       };
+};
+
+&mac1 {
+       status = "okay";
+       phy-mode = "gmii";
+       phy-handle = <&phy1>;
+       phy1: ethernet-phy@0 {
+               reg = <0>;
+       };
+};
+
+&mbox {
+       status = "okay";
+};
+
+&mmc {
+       max-frequency = <50000000>;
+       bus-width = <4>;
+       cap-mmc-highspeed;
+       cap-sd-highspeed;
+       no-1-8-v;
+       sd-uhs-sdr12;
+       sd-uhs-sdr25;
+       sd-uhs-sdr50;
+       sd-uhs-sdr104;
+       disable-wp;
+       status = "okay";
+};
+
+&mmuart1 {
+       status = "okay";
+};
+
+&mmuart2 {
+       status = "okay";
+};
+
+&mmuart3 {
+       status = "okay";
+};
+
+&mmuart4 {
+       status = "okay";
+};
+
+&pcie {
+       status = "okay";
+};
+
+&qspi {
+       status = "okay";
+};
+
+&refclk {
+       clock-frequency = <125000000>;
+};
+
+&rtc {
+       status = "okay";
+};
+
+&spi0 {
+       status = "okay";
+};
+
+&spi1 {
+       status = "okay";
+};
+
+&syscontroller {
+       status = "okay";
+};
+
+&usb {
+       status = "okay";
+       dr_mode = "host";
+};