expectPattern({SPF_FMINNUM, SPNB_RETURNS_OTHER, true});
}
+TEST_F(MatchSelectPatternTest, VectorFMinNaN) {
+ parseAssembly(
+ "define <4 x float> @test(<4 x float> %a) {\n"
+ " %1 = fcmp ule <4 x float> %a, \n"
+ " <float 5.0, float 5.0, float 5.0, float 5.0>\n"
+ " %A = select <4 x i1> %1, <4 x float> %a,\n"
+ " <4 x float> <float 5.0, float 5.0, float 5.0, float 5.0>\n"
+ " ret <4 x float> %A\n"
+ "}\n");
+ // Check that pattern matching works on vectors where each lane has the same
+ // unordered pattern.
+ expectPattern({SPF_FMINNUM, SPNB_RETURNS_NAN, false});
+}
+
+TEST_F(MatchSelectPatternTest, VectorFMinOtherOrdered) {
+ parseAssembly(
+ "define <4 x float> @test(<4 x float> %a) {\n"
+ " %1 = fcmp ole <4 x float> %a, \n"
+ " <float 5.0, float 5.0, float 5.0, float 5.0>\n"
+ " %A = select <4 x i1> %1, <4 x float> %a,\n"
+ " <4 x float> <float 5.0, float 5.0, float 5.0, float 5.0>\n"
+ " ret <4 x float> %A\n"
+ "}\n");
+ // Check that pattern matching works on vectors where each lane has the same
+ // ordered pattern.
+ expectPattern({SPF_FMINNUM, SPNB_RETURNS_OTHER, true});
+}
+
+TEST_F(MatchSelectPatternTest, VectorNotFMinNaN) {
+ parseAssembly(
+ "define <4 x float> @test(<4 x float> %a) {\n"
+ " %1 = fcmp ule <4 x float> %a, \n"
+ " <float 5.0, float 0x7ff8000000000000, float 5.0, float 5.0>\n"
+ " %A = select <4 x i1> %1, <4 x float> %a,\n"
+ " <4 x float> <float 5.0, float 0x7ff8000000000000, float 5.0, float "
+ "5.0>\n"
+ " ret <4 x float> %A\n"
+ "}\n");
+ // The lane that contains a NaN (0x7ff80...) behaves like a
+ // non-NaN-propagating min and the other lines behave like a NaN-propagating
+ // min, so check that neither is returned.
+ expectPattern({SPF_UNKNOWN, SPNB_NA, false});
+}
+
+TEST_F(MatchSelectPatternTest, VectorNotFMinZero) {
+ parseAssembly(
+ "define <4 x float> @test(<4 x float> %a) {\n"
+ " %1 = fcmp ule <4 x float> %a, \n"
+ " <float 5.0, float -0.0, float 5.0, float 5.0>\n"
+ " %A = select <4 x i1> %1, <4 x float> %a,\n"
+ " <4 x float> <float 5.0, float 0.0, float 5.0, float 5.0>\n"
+ " ret <4 x float> %A\n"
+ "}\n");
+ // Always selects the second lane of %a if it is positive or negative zero, so
+ // this is stricter than a min.
+ expectPattern({SPF_UNKNOWN, SPNB_NA, false});
+}
+
TEST_F(MatchSelectPatternTest, DoubleCastU) {
parseAssembly(
"define i32 @test(i8 %a, i8 %b) {\n"