M: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
F: drivers/amlogic/clk/sm1/*
-AMLOGIC SM1 AND AXG DTS
++AMLOGIC AXG DTS
+ M: shaochan.liu <shaochan.liu@amlogic.com>
-F: arch/arm64/boot/dts/amlogic/mesonsm1_skt-panel.dtsi
-F: arch/arm/boot/dts/amlogic/mesonsm1_skt-panel.dtsi
+ F: arch/arm64/boot/dts/amlogic/mesonaxg_skt-panel.dtsi
+ F: arch/arm/boot/dts/amlogic/mesonaxg_skt-panel.dtsi
+
-
AMLOGIC SM1 POWER CTRL DRIVERS
M: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
F: drivers/amlogic/power/power_ctrl.c
F: include/linux/amlogic/power_ctrl.h
+AMLOGIC SM1 DTS
+M: shaochan.liu <shaochan.liu@amlogic.com>
+F: arch/arm64/boot/dts/amlogic/mesonsm1_skt-panel.dtsi
+F: arch/arm/boot/dts/amlogic/mesonsm1_skt-panel.dtsi
+
+AMLOGIC TL1 VAD
+M: Wenbiao Zhang <wenbiao.zhang@amlogic.com>
+F: include/linux/amlogic/vad_api.h
+
+ AMLOGIC MESONAXG S400 GVA SBR DTS
+ M: Yeping Miao <yeping.miao@amlogic.com>
+ F: arch/arm64/boot/dts/amlogic/axg_s400_v03gva_sbr.dts
+ F: arch/arm/boot/dts/amlogic/axg_s400_v03gva_sbr.dts
+
+ AMLOGIC TL1 DTS
+ M: Huijie Huang <huijie.huang@amlogic.com>
+ F: arch/arm/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
+ F: arch/arm/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
+ F: arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
+ F: arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
+
+ AMLOGIC TM2 PINCTRL DRIVER
+ M: Qianggui Song <qianggui.song@amlogic.com>
+ F: drivers/amlogic/pinctrl/pinctrl-meson-tm2.c
+ F: include/dt-bindings/gpio/meson-tm2-gpio.h
+
+ AMLOGIC MESON TM2 CLOCK DRIVER
+ M: Jian Hu <jian.hu@amlogic.com>
+ F: driver/amlogic/clk/tm2/*
+
+ AMLOGIC MESON TM2 LCD DTS
+ M: Shaochan Liu <shaochan.liu@amlogic.com>
+ F: arch/arm64/boot/dts/amlogic/mesontm2_t962x3_ab301-panel.dtsi
+ F: arch/arm64/boot/dts/amlogic/mesontm2_t962x3_ab309-panel.dtsi
+ F: arch/arm/boot/dts/amlogic/mesontm2_t962x3_ab301-panel.dtsi
+ F: arch/arm/boot/dts/amlogic/mesontm2_t962x3_ab309-panel.dtsi
+
AMLOGIC SM1 S905X3 DTS
M: Xiaoliang Wang <xiaoliang.wang@amlogic.com>
F: arch/arm/boot/dts/amlogic/g12a_s905x2_u212.dts
M: XINLIANG ZHANG <xinliang.zhang@amlogic.com>
F: drivers/amlogic/input/touchscreen/hyn_cst2xx/*
-M: Shuyu Li <Shuyu.Li@amlogic.com>
-F: drivers/amlogic/hifi4dsp/*
+ AMLOGIC WEEKLY CHANGE GENERATOR
+ M: JIAMIN MA <jiamin.ma@amlogic.com>
+ F: scripts/amlogic/weekly_change.py
+
+ ANLOGIC HIFI4DSP
-M: Guofeang Tang <guofeng.tang@amlogic.com>
-F: arch/arm/boot/dts/amlogic/sm1_s905d3_ac200_buildroot.dts
-F: arch/arm/boot/dts/amlogic/sm1_s905x3_ac213_buildroot.dts
-F: arch/arm/boot/dts/amlogic/sm1_s905x3_ac214_buildroot.dts
-F: arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200_buildroot.dts
-F: arch/arm64/boot/dts/amlogic/sm1_s905x3_ac213_buildroot.dts
-F: arch/arm64/boot/dts/amlogic/sm1_s905x3_ac214_buildroot.dts
++M: Shuyu Li <Shuyu.Li@amlogic.com>
++F: drivers/amlogic/hifi4dsp/*
+
+ AMLOGIC SM1 AC200/AC213/AC214 BUILDROOT DTS
-M: Guofeang Tang <guofeng.tang@amlogic.com>
-F: arch/arm/boot/dts/amlogic/g12b_a311d_w400_drm_buildroot.dts
-F: arch/arm/boot/dts/amlogic/g12b_a311d_w400_drm_buildroot_a.dts
-F: arch/arm64/boot/dts/amlogic/g12b_a311d_w400_drm_buildroot.dts
-F: arch/arm64/boot/dts/amlogic/g12b_a311d_w400_drm_buildroot_a.dts
++M: Guofeang Tang <guofeng.tang@amlogic.com>
++F: arch/arm/boot/dts/amlogic/sm1_s905d3_ac200_buildroot.dts
++F: arch/arm/boot/dts/amlogic/sm1_s905x3_ac213_buildroot.dts
++F: arch/arm/boot/dts/amlogic/sm1_s905x3_ac214_buildroot.dts
++F: arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200_buildroot.dts
++F: arch/arm64/boot/dts/amlogic/sm1_s905x3_ac213_buildroot.dts
++F: arch/arm64/boot/dts/amlogic/sm1_s905x3_ac214_buildroot.dts
+
+ AMLOGIC G12B W400 DRM BUILDROOT DTS
++M: Guofeang Tang <guofeng.tang@amlogic.com>
++F: arch/arm/boot/dts/amlogic/g12b_a311d_w400_drm_buildroot.dts
++F: arch/arm/boot/dts/amlogic/g12b_a311d_w400_drm_buildroot_a.dts
++F: arch/arm64/boot/dts/amlogic/g12b_a311d_w400_drm_buildroot.dts
++F: arch/arm64/boot/dts/amlogic/g12b_a311d_w400_drm_buildroot_a.dts
+
AMLOGIC GXL P281 DTS
--M: Luan Yuan <luan.yuan@amlogic.com>
--F: arch/arm/boot/dts/amlogic/gxl_p281_1g.dts
--F: arch/arm/boot/dts/amlogic/gxl_p281_2g.dts
--F: arch/arm64/boot/dts/amlogic/gxl_p281_1g.dts
--F: arch/arm64/boot/dts/amlogic/gxl_p281_2g.dts
++M: Luan Yuan <luan.yuan@amlogic.com>
++F: arch/arm/boot/dts/amlogic/gxl_p281_1g.dts
++F: arch/arm/boot/dts/amlogic/gxl_p281_2g.dts
++F: arch/arm64/boot/dts/amlogic/gxl_p281_1g.dts
++F: arch/arm64/boot/dts/amlogic/gxl_p281_2g.dts
AMLOGIC CAMERA GC2145 MIPI DRIVER
--M: Guosong Zhou <guosong.zhou@amlogic.com>
--F: arch/arm/boot/dts/amlogic/sm1_s905d3_ac202.dts
--F: arch/arm/boot/dts/amlogic/sm1_s905d3_ac202_1g.dts
--F: arch/arm/configs/meson64_a32_defconfig
--F: arch/arm64/boot/dts/amlogic/sm1_s905d3_ac202.dts
--F: arch/arm64/boot/dts/amlogic/sm1_s905d3_ac202_1g.dts
--F: arch/arm64/configs/meson64_defconfig
--F: drivers/amlogic/media/camera/gc2145_mipi.c
++M: Guosong Zhou <guosong.zhou@amlogic.com>
++F: arch/arm/boot/dts/amlogic/sm1_s905d3_ac202.dts
++F: arch/arm/boot/dts/amlogic/sm1_s905d3_ac202_1g.dts
++F: arch/arm/configs/meson64_a32_defconfig
++F: arch/arm64/boot/dts/amlogic/sm1_s905d3_ac202.dts
++F: arch/arm64/boot/dts/amlogic/sm1_s905d3_ac202_1g.dts
++F: arch/arm64/configs/meson64_defconfig
++F: drivers/amlogic/media/camera/gc2145_mipi.c
+
+ AMLOGIC GDC DRIVER
+ M: Pengcheng Chen <pengcheng.chen@amlogic.com>
+ F: drivers/amlogic/media/gdc/app/gdc_wq.c
+ F: drivers/amlogic/media/gdc/app/gdc_wq.h
+
+ LAB126 PRIVACY
+ M: LAB126
+ F: drivers/misc/amz_priv*
+
+ LAB126 lifecycle and log
+ M: LAB126
+ F: drivers/staging/amazon/*
+
+ LAB126 tmp103
+ M: LAB126
+ F: drivers/hwmon/tmp103.c
+
+ LAB126 RAVEN DTS
+ M: Yong Yu <yonyu@lab126.com>
+ F: arch/arm64/boot/dts/amlogic/raven.dts
+ F: arch/arm64/boot/dts/amlogic/raven_proto.dts
+ F: Documentation/devicetree/bindings/iio/light/tsl2540.txt
+
+ LAB126 RAVEN DEFCONFIG
+ M: Yong Yu <yonyu@lab126.com>
+ F: arch/arm64/configs/raven_defconfig
+ F: arch/arm64/configs/raven_debug_defconfig
+
+ LAB126 RAVEN THERMISTOR
+ M: Kevin Ow <krow@amazon.com>
+ F: Documentation/devicetree/bindings/thermal/ntc-bts-thermistor.txt
+ F: drivers/amlogic/iio/adc/saradc_ntc_bts.c
+ F: drivers/amlogic/iio/adc/Makefile
+ F: drivers/amlogic/iio/adc/Kconfig
+
+ LAB126 RAVEN VIRTUAL THERMAL SENSOR
+ M: Kevin Ow <krow@amazon.com>
+ F: arch/arm64/boot/dts/amlogic/raven_thermal_zones.dtsi
+ F: Documentation/devicetree/bindings/thermal/virtual_sensor_thermal.txt
+ F: drivers/thermal/Kconfig
+ F: drivers/thermal/Makefile
+ F: drivers/thermal/trip_step_wise.c
+ F: drivers/thermal/virtual_sensor_thermal.c
+ F: include/linux/virtual_sensor_thermal.h
+
+ LAB126 RAVEN WIFI_COOLING
+ M: Kevin Ow <krow@amazon.com>
+ F: Documentation/devicetree/bindings/thermal/wifi-temp-sensor.txt
+ F: drivers/thermal/wifi_cooling.c
+ F: drivers/amlogic/thermal/aml_thermal_cooling.c
+ F: drivers/amlogic/thermal/aml_thermal_hw.c
+ F: include/linux/amlogic/aml_thermal_cooling.h
+ F: include/linux/amlogic/aml_thermal_hw.h
+
+ THIRD PARTY AUDIO CODEC TLV320DAC3203
+ M: Xing Fang <xing.fang@amlogic.com>
+ F: sound/soc/codecs/tlv320dac3203.c
+ F: sound/soc/codecs/tlv320dac3203.h
+
+ LAB126 PERFORMANCE BOOST DRIVER
+ M: Yong Yu <yonyu@lab126.com>
+ F: drivers/amlogic/cpufreq/cpufreq-boost.c
+ F: include/linux/cpufreq-boost.h
+
+ ADD OSD SW_SYNC DRIVER
+ M: Pengcheng Chen <pengcheng.chen@amlogic.com>
+ F: drivers/amlogic/media/osd/osd_sw_sync.c
+ F: drivers/amlogic/media/osd/osd_sw_sync.h
+
+ AMLOGIC VIRTUAL_FB DRIVER
+ M: Pengcheng Chen <pengcheng.chen@amlogic.com>
+ F: drivers/amlogic/media/osd/osd_virtual.c
+ F: drivers/amlogic/media/osd/osd_virtual.h
+
+ AMLOGIC TL1 PIXEL PROBE
+ M: Yan Wang <yan.wang@amlogic.com>
+ F: drivers/amlogic/pixel_probe/*
+ F: include/linux/amlogic/pixel_probe.h
+
+ AMLOGIC ADD HDR10+ TO SDR FUNCTION
+ M: Cheng Wang <cheng.wang@amlogic.com>
+ F: drivers/amlogic/media/enhancement/amvecm/hdr/am_hdr10_plus_ootf.c
+ F: drivers/amlogic/media/enhancement/amvecm/hdr/am_hdr10_plus_ootf.h
+
+ AMLOGIC PATTERN DETECTION FUNCTION
+ M: Xihai ZHu <xihai.zhu@amlogic.com>
+ F: drivers/amlogic/media/enhancement/amvecm/pattern_detection.c
+ F: drivers/amlogic/media/enhancement/amvecm/pattern_detection.h
+ F: drivers/amlogic/media/enhancement/amvecm/pattern_detection_bar_settings.h
+ F: drivers/amlogic/media/enhancement/amvecm/pattern_detection_corn_settings.h
+ F: drivers/amlogic/media/enhancement/amvecm/pattern_detection_face_settings.h
+
+ AMLOGIC DRM
+ M: Ao Xu <ao.xu@amlogic.com>
+ M: Dezhi Kong <dezhi.kong@amlogic.com>
+ F: include/linux/meson_ion.h
+ F: include/uapi/drm/meson_drm.h
+ F: include/uapi/drm/drm_fourcc.c
+ F: drivers/gpu/Makefile
+ F: drivers/amlogic/Kconfig
+ F: drivers/amlogic/Makefile
+ F: drivers/amlogic/drm/*
+ F: drivers/staging/android/ion/ion.h
+ F: drivers/staging/android/ion/ion_cma_heap.c
+ F: drivers/amlogic/media/osd/osd_fb.c
+ F: drivers/amlogic/media/common/ion_dev/dev_ion.c
+ F: drivers/amlogic/media/common/ion_dev/dev_ion.h
+ F: arch/arm/boot/dts/amlogic/meson-g12a-u200.dts
+ F: arch/arm/boot/dts/amlogic/mesong12a_drm.dtsi
+ F: arch/arm/boot/dts/amlogic/sm1_s905d3_ac200.dts
+ F: arch/arm/boot/dts/amlogic/sm1_s905x3_ac213.dts
+ F: arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
+ F: arch/arm64/boot/dts/amlogic/mesong12a_drm.dtsi
+ F: arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200.dts
+ F: arch/arm64/boot/dts/amlogic/sm1_s905x3_ac213.dts
+ F: arch/arm/configs/meson64_a32_defconfig
+ F: arch/arm64/configs/meson64_a64_defconfig
+ F: arch/arm/boot/dts/amlogic/Makefile
+ F: arch/arm64/boot/dts/amlogic/Makefile
+
+ AMLOGIC VDAC
+ M: Evoke Zhang <evoke.zhang@amlogic.com>
+ F: drivers/amlogic/media/vout/vdac/vdac_dev.h
+ F: drivers/amlogic/media/vout/vdac/vdac_config.c
+
+ AMLOGIC DRM
+ M: Dezhi Kong <dezhi.kong@amlogic.com>
+ F: arch/arm/boot/dts/amlogic/mesonsm1_drm.dtsi
+ F: arch/arm64/boot/dts/amlogic/mesonsm1_drm.dtsi
+ F: arch/arm/boot/dts/amlogic/sm1_s905d3_ac200_drm_buildroot.dts
+ F: arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200_drm_buildroot.dts
+ F: drivers/amlogic/drm/meson_vpu.c
+
+ AMLOGIC ADD DTS FOR T312 PLATFORM
+ M: hualing chen <hualing.chen@amlogic.com>
+ F: arch/arm64/boot/dts/amlogic/mesontm2_t962x3_t312-panel.dtsi
+ F: arch/arm/boot/dts/amlogic/mesontm2_t962x3_t312-panel.dtsi
+
+ AMLOGIC ADD DRM FOR P212
+ M: lingjie li <lingjie.li@amlogic.com>
+ F: arch/arm/boot/dts/amlogic/gxl_p212_2g_drm_buildroot.dts
+
+ AMLOGIC ADD DTS FOR AC223 PLATFORM
+ M: huijie huang <huijie.huang@amlogic.com>
+ F: arch/arm/boot/dts/amlogic/sm1_s905y3_ac223.dts
+ F: arch/arm64/boot/dts/amlogic/sm1_s905y3_ac223.dts
+
+ AMLOGIC TVAFE DRIVER
+ M: Evoke Zhang <evoke.zhang@amlogic.com>
+ F: drivers/amlogic/media/vin/tvin/tvafe/tvafe_pq_table.c
+
+ AMLOGIC DEINTERLACE DRIVER
+ M: Jihong Sui <jihong.sui@amlogic.com>
+ F: drivers/amlogic/media/deinterlace/di_pqa.h
+ F: drivers/amlogic/media/di_local/*
+
+ AMLOGIC ADD DI_MULTI DRIVER
+ M: Jihong Sui <jihong.sui@amlogic.com>
+ F: drivers/amlogic/media/di_multi/*
+
+ AMLOGIC DRM
+ M: Ao Xu <ao.xu@amlogic.com>
+ F: drivers/amlogic/drm/meson_debugfs.c
+
+ AMLOGIC DRM
+ M: Dezhi Kong <dezhi.kong@amlogic.com>
+ F: arch/arm/boot/dts/amlogic/mesontl1_drm.dtsi
+ F: arch/arm/boot/dts/amlogic/tl1_t962x2_x301_1g_drm.dts
+ F: arch/arm/boot/dts/amlogic/tl1_t962x2_x301_2g_drm.dts
+ F: arch/arm64/boot/dts/amlogic/mesontl1_drm.dtsi
+ F: arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g_drm.dts
+ F: arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g_drm.dts
+ F: drivers/amlogic/drm/meson_lcd.c
+ F: drivers/amlogic/drm/meson_vpu.c
+ F: drivers/amlogic/drm/meson_vpu_pipeline.c
+ F: drivers/amlogic/drm/meson_vpu_pipeline_traverse.c
+ F: include/dt-bindings/display/meson-drm-ids.h
+
+ AMLOGIC LCD EXTERN DRIVER
+ M: Shaochan Liu <shaochan.liu@amlogic.com>
+ F: drivers/amlogic/media/vout/lcd/lcd_extern/i2c_CS602.c
+
+ AMLOGIC SM1/G12A BL40 BOOTUP DRIVER
+ M: shunzhou jiang <shunzhou.jiang@amlogic.com>
+ F: drivers/amlogic/firmware/bl40_module.c
+ F: drivers/amlogic/firmware/Makefile
+ F: drivers/amlogic/firmware/Kconfig
+
+ AMLOGIC VAD WAKEUP POWER
+ M: Zhiqiang Liang <zhiqiang.liang@amlogic.com>
+ F: drivers/amlogic/pm/vad_power.c
+ F: drivers/amlogic/pm/vad_power.h
+
+ AMLOGIC T962E2 SBR DTS
+ M: Bing Jiang <Bing.Jiang@amlogic.com>
+ F: arch/arm/boot/dts/amlogic/tm2_t962e2_ab311_sbr.dts
+ F: arch/arm64/boot/dts/amlogic/tm2_t962e2_ab311_sbr.dts
+
+ AMLOGIC S805Y DTS
+ M: Luan Yuan <luan.yuan@amlogic.com>
+ F: arch/arm/boot/dts/amlogic/gxl_p244_1g.dts
+ F: arch/arm/boot/dts/amlogic/gxl_p244_2g.dts
+ F: arch/arm64/boot/dts/amlogic/gxl_p244_1g.dts
+ F: arch/arm64/boot/dts/amlogic/gxl_p244_2g.dts
+
+ HARDKERNEL S922D odroidn2
+ M: Joy Cho <joy.cho@hardkernel.com>
+ F: arch/arm64/configs/odroidn2_defconfig
+ F: arch/arm64/boot/dts/amlogic/s922d_odroidn2.dts
+
+ HARDKERNEL S922D odroidn2
+ M: Kevin Kim <ckkim@hardkernel.com>
+ F: drivers/char/aml-gpiomem.c
+
+ HARDKERNEL S922D odroidn2
+ M: Pierluigi Passaro <info@phoenixsoftware.it>
+ F: drivers/input/touchscreen/sx8650.c
+
+ HARDKERNEL S922D odroidn2
+ M: charles park <charles.park@hardkernel.com>
+ F: Documentation/devicetree/binding/input/touchscreen/sx8650.txt
+
+ DWAV TOUCHSCREEN DRIVER
+ M: codewalker@hardkernel.com>
+ S: Maintained
+ F: drivers/input/touchscreen/dwav-usb-mt.c
+
+ HARDKERNEL S905X3 odroidc4
+ M: Kevin Kim <ckkim@hardkernel.com>
+ F: arch/arm64/configs/odroidc4_defconfig
+ F: arch/arm64/boot/dts/amlogic/mesong12_odroid_common.dtsi
+
+ HARDKERNEL S922D odroidn2
+ M: Kevin Kim <ckkim@hardkernel.com>
+ F: arch/arm64/boot/dts/amlogic/meson64_odroidn2_plus.dts
+ F: arch/arm64/boot/dts/amlogic/meson64_odroidn2.dtsi
+
+ HARDKERNEL odroidc4 DTS
+ M: Kevin Kim <ckkim@hardkernel.com>
+ F: arch/arm64/boot/dts/amlogic/overlays/odroidc4/lineout.dts
KBUILD_CFLAGS += $(stackp-flag)
ifeq ($(cc-name),clang)
- ifneq ($(CROSS_COMPILE),)
- CLANG_TARGET := -target $(notdir $(CROSS_COMPILE:%-=%))
- GCC_TOOLCHAIN := $(realpath $(dir $(shell which $(LD)))/..)
- endif
- ifneq ($(GCC_TOOLCHAIN),)
- CLANG_GCC_TC := -gcc-toolchain $(GCC_TOOLCHAIN)
- endif
- KBUILD_CFLAGS += $(CLANG_TARGET) $(CLANG_GCC_TC)
- KBUILD_AFLAGS += $(CLANG_TARGET) $(CLANG_GCC_TC)
KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
- KBUILD_CFLAGS += $(call cc-disable-warning, unused-variable)
KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)
KBUILD_CFLAGS += $(call cc-disable-warning, gnu)
- KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member)
+KBUILD_CFLAGS += $(call cc-disable-warning, duplicate-decl-specifier)
-
# Quiet clang warning: comparison of unsigned expression < 0 is always false
KBUILD_CFLAGS += $(call cc-disable-warning, tautological-compare)
# CLANG uses a _MergedGlobals as optimization, but this breaks modpost, as the
reserve_mem_size = <0x00300000>;
};
- securitykey {
- compatible = "amlogic, securitykey";
- status = "okay";
- storage_query = <0x82000060>;
- storage_read = <0x82000061>;
- storage_write = <0x82000062>;
- storage_tell = <0x82000063>;
- storage_verify = <0x82000064>;
- storage_status = <0x82000065>;
- storage_list = <0x82000067>;
- storage_remove = <0x82000068>;
- storage_in_func = <0x82000023>;
- storage_out_func = <0x82000024>;
- storage_block_func = <0x82000025>;
- storage_size_func = <0x82000027>;
- storage_set_enctype = <0x8200006A>;
- storage_get_enctype = <0x8200006B>;
- storage_version = <0x8200006C>;
+ pixel_probe: pixel_probe {
+ compatible = "amlogic, pixel_probe";
+ vpp_probe_func = <0x820000f1>;
+ vdin_probe_func = <0x820000f2>;
};
- securitykey {
- compatible = "amlogic, securitykey";
- status = "okay";
- storage_query = <0x82000060>;
- storage_read = <0x82000061>;
- storage_write = <0x82000062>;
- storage_tell = <0x82000063>;
- storage_verify = <0x82000064>;
- storage_status = <0x82000065>;
- storage_list = <0x82000067>;
- storage_remove = <0x82000068>;
- storage_in_func = <0x82000023>;
- storage_out_func = <0x82000024>;
- storage_block_func = <0x82000025>;
- storage_size_func = <0x82000027>;
- storage_set_enctype = <0x8200006A>;
- storage_get_enctype = <0x8200006B>;
- storage_version = <0x8200006C>;
- };
-
mailbox: mhu@ff63c400 {
compatible = "amlogic, meson_mhu";
reg = <0xff63c400 0x4c>, /* MHU registers */
+dtb-$(CONFIG_ARM64) += kvim_linux.dtb
+dtb-$(CONFIG_ARM64) += kvim2_linux.dtb
+dtb-$(CONFIG_ARM64) += kvim3l_linux.dtb
+dtb-$(CONFIG_ARM64) += kvim3_linux.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+subdir-y += overlays/kvim
+subdir-y += overlays/kvim2
+subdir-y += overlays/kvim3
+subdir-y += overlays/kvim3l
++
+ ifndef CONFIG_ARCH_MESON64_ODROID_COMMON
+ dtb-y += g12a_s905d2_skt.dtb
+ dtb-y += g12a_s905d2_skt_buildroot.dtb
+ dtb-y += g12a_s905d2_u200.dtb
+ dtb-y += g12a_s905d2_u200_buildroot.dtb
+ dtb-y += g12a_s905d2_u200_drm_buildroot.dtb
+ dtb-y += g12b_a311d_w400.dtb
+ dtb-y += g12b_a311d_w400_buildroot.dtb
+ endif
++
+ dtb-$(CONFIG_ARCH_MESON64_ODROIDC4) += meson64_odroidc4.dtb
+ dtb-$(CONFIG_ARCH_MESON64_ODROIDC4) += meson64_odroidhc4.dtb
+ dtb-$(CONFIG_ARCH_MESON64_ODROIDN2) += meson64_odroidn2.dtb
+ dtb-$(CONFIG_ARCH_MESON64_ODROIDN2) += meson64_odroidn2_plus.dtb
+ dtb-$(CONFIG_ARCH_MESON64_ODROIDN2) += meson64_odroidn2_drm.dtb
+
+ subdir-$(CONFIG_ARCH_MESON64_ODROIDC4) += overlays/odroidc4
+ subdir-$(CONFIG_ARCH_MESON64_ODROIDN2) += overlays/odroidn2
++
+clean-files := *.dtb *.dtbo
unifykey-index-4 = <&keysn_4>;
unifykey-index-5 = <&keysn_5>;
unifykey-index-6 = <&keysn_6>;
+ unifykey-index-7 = <&keysn_7>;
+ unifykey-index-8 = <&keysn_8>;
+ unifykey-index-9 = <&keysn_9>;
+ unifykey-index-10 = <&keysn_10>;
-
keysn_0: key_0{
key-name = "usid";
key-device = "normal";
--- /dev/null
- earc:earc {
- compatible = "amlogic, sm1-snd-earc";
- #sound-dai-cells = <0>;
-
- clocks = <&clkaudio CLKID_AUDIO_GATE_EARCRX
- &clkaudio CLKID_EARCRX_CMDC
- &clkaudio CLKID_EARCRX_DMAC
- &clkc CLKID_FCLK_DIV5
- &clkc CLKID_FCLK_DIV3
- >;
- clock-names = "rx_gate",
- "rx_cmdc",
- "rx_dmac",
- "rx_cmdc_srcpll",
- "rx_dmac_srcpll";
-
- interrupts = <
- GIC_SPI 88 IRQ_TYPE_EDGE_RISING
- GIC_SPI 87 IRQ_TYPE_EDGE_RISING
- >;
- interrupt-names = "rx_cmdc", "rx_dmac";
-
- status = "okay";
- };
-
+/*
+ * arch/arm64/boot/dts/amlogic/kvim3l_linux.dts
+ *
+ * Copyright (C) 2019 Wesion, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+/dts-v1/;
+
+#include "mesonsm1.dtsi"
+#include "partition_linux.dtsi"
+#include "khadas-ts050-panel.dtsi"
+
+/ {
+ model = "Khadas VIM3L";
+ amlogic-dt-id = "sm1_kvim3l";
+ compatible = "amlogic, g12a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ aliases {
+ serial0 = &uart_AO;
+ serial1 = &uart_A;
+ serial2 = &uart_B;
+ serial3 = &uart_C;
+ serial4 = &uart_AO_B;
+ tsensor0 = &p_tsensor;
+ tsensor1 = &d_tsensor;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c_AO;
+ spi1 = &spicc1;
+ };
+
+// memory@00000000 {
+// device_type = "memory";
+// linux,usable-memory = <0x0 0x000000 0x0 0x80000000>;
+// };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ /* global autoconfigured region for contiguous allocations */
+ ramoops@0x07400000 {
+ compatible = "ramoops";
+ reg = <0x0 0x07400000 0x0 0x00100000>;
+ record-size = <0x8000>;
+ console-size = <0x8000>;
+ ftrace-size = <0x40000>;
+ };
+
+ secmon_reserved:linux,secmon {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x400000>;
+ alignment = <0x0 0x400000>;
+ alloc-ranges = <0x0 0x05000000 0x0 0x400000>;
+ };
+ secos_reserved:linux,secos {
+ status = "disable";
+ compatible = "amlogic, aml_secos_memory";
+ reg = <0x0 0x05300000 0x0 0x2000000>;
+ no-map;
+ };
+ logo_reserved:linux,meson-fb {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x800000>;
+ alignment = <0x0 0x400000>;
+ alloc-ranges = <0x0 0x7f800000 0x0 0x800000>;
+ };
+ ion_cma_reserved:linux,ion-dev {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x400000>;
+ };
+ //di_reserved:linux,di {
+ //compatible = "amlogic, di-mem";
+ /* buffer_size = 3621952(yuv422 8bit) */
+ /* 4179008(yuv422 10bit full pack mode) */
+ /** 10x3621952=34.6M(0x23) support 8bit **/
+ /** 10x4736064=45.2M(0x2e) support 12bit **/
+ /** 10x4179008=40M(0x28) support 10bit **/
+ //size = <0x0 0x2800000>;
+ //no-map;
+ //};
+ /*di CMA pool */
+ di_cma_reserved:linux,di_cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ /* buffer_size = 3621952(yuv422 8bit)
+ * | 4736064(yuv422 10bit)
+ * | 4074560(yuv422 10bit full pack mode)
+ * 10x3621952=34.6M(0x23) support 8bit
+ * 10x4736064=45.2M(0x2e) support 12bit
+ * 10x4074560=40M(0x28) support 10bit
+ */
+ size = <0x0 0x02800000>;
+ alignment = <0x0 0x400000>;
+ };
+ /* POST PROCESS MANAGER */
+ ppmgr_reserved:linux,ppmgr {
+ compatible = "shared-dma-pool";
+ size = <0x0 0x0>;
+ };
+
+ codec_mm_cma:linux,codec_mm_cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ /* ion_codec_mm max can alloc size 80M*/
+ size = <0x0 0x13400000>;
+ alignment = <0x0 0x400000>;
+ linux,contiguous-region;
+ };
+ /* codec shared reserved */
+ codec_mm_reserved:linux,codec_mm_reserved {
+ compatible = "amlogic, codec-mm-reserved";
+ size = <0x0 0x0>;
+ alignment = <0x0 0x100000>;
+ //no-map;
+ };
+ /* vdin0 CMA pool */
+ //vdin0_cma_reserved:linux,vdin0_cma {
+ // compatible = "shared-dma-pool";
+ // reusable;
+ /* 1920x1080x2x4 =16+4 M */
+ // size = <0x0 0x04000000>;
+ // alignment = <0x0 0x400000>;
+ //};
+ /* vdin1 CMA pool */
+ vdin1_cma_reserved:linux,vdin1_cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ /* 1920x1080x2x4 =16 M */
+ size = <0x0 0x04000000>;
+ alignment = <0x0 0x400000>;
+ };
+ vm0_cma_reserved:linux,vm0_cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x2000000>;
+ alignment = <0x0 0x400000>;
+ };
+ };
+
+ galcore {
+ status = "okay";
+ };
+ gpioleds {
+ compatible = "gpio-leds";
+ status = "okay";
+
+ sys_led {
+ label="sys_led";
+ gpios=<&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>;
+ default-state ="on";
+ retain-state-suspended;
+ linux,default-trigger="default-on";
+ };
+
+ red_led {
+ label = "red_red";
+ gpios = <&gpio_expander 5 GPIO_ACTIVE_HIGH>;
+ default-state ="off";
+ linux,default-trigger="none";
+ };
+ };
+
+ cvbsout {
+ compatible = "amlogic, cvbsout-sm1";
+ dev_name = "cvbsout";
+ status = "disabled";
+ clocks = <&clkc CLKID_VCLK2_ENCI
+ &clkc CLKID_VCLK2_VENCI0
+ &clkc CLKID_VCLK2_VENCI1
+ &clkc CLKID_DAC_CLK>;
+ clock-names = "venci_top_gate",
+ "venci_0_gate",
+ "venci_1_gate",
+ "vdac_clk_gate";
+ /* clk path */
+ /* 0:vid_pll vid2_clk */
+ /* 1:gp0_pll vid2_clk */
+ /* 2:vid_pll vid1_clk */
+ /* 3:gp0_pll vid1_clk */
+ clk_path = <2>;
+
+ /* performance: reg_address, reg_value */
+ /* sm1 */
+ performance = <0x1bf0 0x9
+ 0x1b56 0x333
+ 0x1b12 0x8080
+ 0x1b05 0xfd
+ 0x1c59 0xf850
+ 0xffff 0x0>; /* ending flag */
+ performance_sarft = <0x1bf0 0x9
+ 0x1b56 0x333
+ 0x1b12 0x0
+ 0x1b05 0x9
+ 0x1c59 0xfc48
+ 0xffff 0x0>; /* ending flag */
+ performance_revB_telecom = <0x1bf0 0x9
+ 0x1b56 0x546
+ 0x1b12 0x8080
+ 0x1b05 0x9
+ 0x1c59 0xf850
+ 0xffff 0x0>; /* ending flag */
+ };
+
+ bt-dev{
+ compatible = "amlogic, bt-dev";
+ dev_name = "bt-dev";
+ status = "okay";
+ gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
+ };
+
+ wifi{
+ compatible = "amlogic, aml_wifi";
+ dev_name = "aml_wifi";
+ status = "okay";
+ interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>;
+ irq_trigger_type = "GPIO_IRQ_LOW";
+ power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>;
+ dhd_static_buf; //if use bcm wifi, config dhd_static_buf
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_e_pins>;
+ pwm_config = <&wifi_pwm_conf>;
+ };
+
+ wifi_pwm_conf:wifi_pwm_conf{
+ pwm_channel1_conf {
+ pwms = <&pwm_ef MESON_PWM_0 30541 0>;
+ duty-cycle = <15270>;
+ times = <10>;
+ };
+ pwm_channel2_conf {
+ pwms = <&pwm_ef MESON_PWM_2 30500 0>;
+ duty-cycle = <15250>;
+ times = <12>;
+ };
+ };
+
+ codec_mm {
+ compatible = "amlogic, codec, mm";
+ memory-region = <&codec_mm_cma &codec_mm_reserved>;
+ dev_name = "codec_mm";
+ status = "okay";
+ };
+
+ picdec_cma_reserved:linux,picdec {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0>;
+ alignment = <0x0>;
+ linux,contiguous-region;
+ };
+
+ picdec {
+ compatible = "amlogic, picdec";
+ memory-region = <&picdec_cma_reserved>;
+ dev_name = "picdec";
+ status = "okay";
+ };
+
+ ppmgr {
+ compatible = "amlogic, ppmgr";
+ memory-region = <&ppmgr_reserved>;
+ dev_name = "ppmgr";
+ status = "okay";
+ };
+
+ gpiomem {
+ compatible = "amlogic, gpiomem";
+ reg = <0x0 0xff634000 0x0 0x1000>;
+ dev_name = "gpiomem";
+ status = "okay";
+ };
+
+ gpiomem_ao {
+ compatible = "amlogic, gpiomem";
+ reg = <0x0 0xff800000 0x0 0x1000>;
+ dev_name = "gpiomem-ao";
+ status = "okay";
+ };
+
+ deinterlace {
+ compatible = "amlogic, deinterlace";
+ status = "okay";
+ /* 0:use reserved; 1:use cma; 2:use cma as reserved */
+ flag_cma = <1>;
+ //memory-region = <&di_reserved>;
+ memory-region = <&di_cma_reserved>;
+ interrupts = <0 46 1
+ 0 40 1>;
+ interrupt-names = "pre_irq", "post_irq";
+ clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>,
+ <&clkc CLKID_VPU_CLKB_COMP>;
+ clock-names = "vpu_clkb_tmp_composite",
+ "vpu_clkb_composite";
+ clock-range = <334 667>;
+ /* buffer-size = <3621952>;(yuv422 8bit) */
+ buffer-size = <4074560>;/*yuv422 fullpack*/
+ /* reserve-iomap = "true"; */
+ /* if enable nr10bit, set nr10bit-support to 1 */
+ post-wr-support = <1>;
+ nr10bit-support = <1>;
+ nrds-enable = <1>;
+ pps-enable = <1>;
+ };
+ ionvideo {
+ compatible = "amlogic, ionvideo";
+ dev_name = "ionvideo";
+ status = "okay";
+ };
+
+ amlvideo2_0 {
+ compatible = "amlogic, amlvideo2";
+ dev_name = "amlvideo2";
+ status = "okay";
+ amlvideo2_id = <0>;
+ cma_mode = <1>;
+ };
+
+ amlvideo2_1 {
+ compatible = "amlogic, amlvideo2";
+ dev_name = "amlvideo2";
+ status = "okay";
+ amlvideo2_id = <1>;
+ cma_mode = <1>;
+ };
+
+ vm0 {
+ compatible = "amlogic, vm";
+ memory-region = <&vm0_cma_reserved>;
+ dev_name = "vm0";
+ status = "disabled";
+ vm_id = <0>;
+ };
+
+ amvdec_656in {
+ /*bt656 gpio conflict with i2c0*/
+ compatible = "amlogic, amvdec_656in";
+ dev_name = "amvdec_656in";
+ status = "disabled";
+ reg = <0x0 0xffe02000 0x0 0x7c>;
+ clocks = <&clkc CLKID_BT656_COMP>,
+ <&clkc CLKID_BT656>;
+ clock-names = "cts_bt656_clk1",
+ "clk_gate_bt656";
+ /* bt656in1, bt656in2 */
+ bt656in1 {
+ bt656_id = <1>;
+ status = "disabled";
+ };
+ };
+
+ aml_cams {
+ compatible = "amlogic, cams_prober";
+ status = "disabled";
+ pinctrl-names="default";
+ pinctrl-0=<&gen_clk_ee_z>;
+ clocks = <&clkc CLKID_GEN_CLK>;
+ clock-names = "g12a_24m";
+ cam_0{
+ cam_name = "gc2145_mipi";
+ front_back = <0>;
+ camera-i2c-bus = <&i2c0>;
+ gpio_pwdn-gpios = <&gpio GPIOZ_2 GPIO_ACTIVE_HIGH>;
+ gpio_rst-gpios = <&gpio GPIOZ_12 GPIO_ACTIVE_HIGH>;
+ mirror_flip = <1>;
+ vertical_flip = <1>;
+ spread_spectrum = <0>;
+ bt_path = "csi";
+ interface = "mipi";
+ clk_channel = "a";
+ bt_path_count = <1>;
+ status = "okay";
+ };
+ };
+
+ amvdec_csi {
+ compatible = "amlogic, amvdec_csi";
+ status = "disabled";
+ csi_id = <0>;
+ reg = <0x0 0xff650000 0x0 0x00000100>,
+ <0x0 0xffe0c000 0x0 0x00000100>,
+ <0x0 0xffe0d000 0x0 0x00000100>;
+ reg-names = "csi_phy", "csi_host", "csi_adapt";
+ clocks = <&clkc CLKID_CSI_ADAPT_CLK_COMP>,
+ <&clkc CLKID_MIPI_CSI_PHY_CLK_COMP>;
+ clock-names = "cts_csi_adapt_clk_composite",
+ "cts_csi_phy_clk_composite";
+ interrupts = <0 1 0>;
+ interrupt-names = "csi_phy";
+ };
+
+ gpio_keypad{
+ compatible = "amlogic, gpio_keypad";
+ status = "okay";
+ scan_period = <20>;
+ key_num = <1>;
+ key_name = "power";
+ key_code = <116>;
+ key-gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>; /* GPIOAO_7 */
+ detect_mode = <0>;/*0:polling mode, 1:irq mode*/
+ };
+
+ adc_keypad {
+ compatible = "amlogic, adc_keypad";
+ status = "okay";
+ key_name = "home";
+ key_num = <1>;
+ io-channels = <&saradc SARADC_CH2>;
+ io-channel-names = "key-chan-2";
+ key_chan = <SARADC_CH2 SARADC_CH2 SARADC_CH2>;
+ key_code = <102>;
+ key_val = <108>; //val=voltage/1800mV*1023
+ key_tolerance = <40>;
+ };
+
+ unifykey{
+ compatible = "amlogic, unifykey";
+ status = "ok";
+ unifykey-num = <18>;
+ unifykey-index-0 = <&keysn_0>;
+ unifykey-index-1 = <&keysn_1>;
+ unifykey-index-2 = <&keysn_2>;
+ unifykey-index-3 = <&keysn_3>;
+ unifykey-index-4 = <&keysn_4>;
+ unifykey-index-5 = <&keysn_5>;
+ unifykey-index-6 = <&keysn_6>;
+ unifykey-index-7 = <&keysn_7>;
+ unifykey-index-8 = <&keysn_8>;
+ unifykey-index-9 = <&keysn_9>;
+ unifykey-index-10= <&keysn_10>;
+ unifykey-index-11= <&keysn_11>;
+ unifykey-index-12= <&keysn_12>;
+ unifykey-index-13= <&keysn_13>;
+ unifykey-index-14= <&keysn_14>;
+ unifykey-index-15= <&keysn_15>;
+ unifykey-index-16= <&keysn_16>;
+ unifykey-index-17= <&keysn_17>;
+
+ keysn_0: key_0{
+ key-name = "usid";
+ key-device = "normal";
+ key-permit = "read","write","del";
+ };
+ keysn_1:key_1{
+ key-name = "mac";
+ key-device = "normal";
+ key-permit = "read","write","del";
+ };
+ keysn_2:key_2{
+ key-name = "hdcp";
+ key-device = "secure";
+ key-type = "sha1";
+ key-permit = "read","write","del";
+ };
+ keysn_3:key_3{
+ key-name = "secure_boot_set";
+ key-device = "efuse";
+ key-permit = "write";
+ };
+ keysn_4:key_4{
+ key-name = "mac_bt";
+ key-device = "normal";
+ key-permit = "read","write","del";
+ key-type = "mac";
+ };
+ keysn_5:key_5{
+ key-name = "mac_wifi";
+ key-device = "normal";
+ key-permit = "read","write","del";
+ key-type = "mac";
+ };
+ keysn_6:key_6{
+ key-name = "hdcp2_tx";
+ key-device = "normal";
+ key-permit = "read","write","del";
+ };
+ keysn_7:key_7{
+ key-name = "hdcp2_rx";
+ key-device = "normal";
+ key-permit = "read","write","del";
+ };
+ keysn_8:key_8{
+ key-name = "widevinekeybox";
+ key-device = "secure";
+ key-permit = "read","write","del";
+ };
+ keysn_9:key_9{
+ key-name = "deviceid";
+ key-device = "normal";
+ key-permit = "read","write","del";
+ };
+ keysn_10:key_10{
+ key-name = "hdcp22_fw_private";
+ key-device = "secure";
+ key-permit = "read","write","del";
+ };
+ keysn_11:key_11{
+ key-name = "PlayReadykeybox25";
+ key-device = "secure";
+ key-permit = "read","write","del";
+ };
+ keysn_12:key_12{
+ key-name = "prpubkeybox";// PlayReady
+ key-device = "secure";
+ key-permit = "read","write","del";
+ };
+ keysn_13:key_13{
+ key-name = "prprivkeybox";// PlayReady
+ key-device = "secure";
+ key-permit = "read","write","del";
+ };
+ keysn_14:key_14{
+ key-name = "attestationkeybox";// attestation key
+ key-device = "secure";
+ key-permit = "read","write","del";
+ };
+ keysn_15:key_15{
+ key-name = "region_code";
+ key-device = "normal";
+ key-permit = "read","write","del";
+ };
+ keysn_16:key_16{
+ key-name = "netflix_mgkid";
+ key-device = "secure";
+ key-permit = "read","write","del";
+ };
+ keysn_17:key_17{
+ key-name = "eth_exphy_para";
+ key-device = "normal";
+ key-permit = "read","write","del";
+ };
+ };//End unifykey
+
+ efuse: efuse{
+ compatible = "amlogic, efuse";
+ read_cmd = <0x82000030>;
+ write_cmd = <0x82000031>;
+ get_max_cmd = <0x82000033>;
+ key = <&efusekey>;
+ status = "okay";
+ };
+
+ efusekey:efusekey{
+ keynum = <1>;
+ key0 = <&key_0>;
+ key_0:key_0{
+ keyname = "mac";
+ offset = <0>;
+ size = <6>;
+ };
+ };//End efusekey
+
+ amlvecm {
+ compatible = "amlogic, vecm";
+ dev_name = "aml_vecm";
+ status = "okay";
+ gamma_en = <1>;/*1:enabel ;0:disable*/
+ wb_en = <0>;/*1:enabel ;0:disable*/
+ cm_en = <0>;/*1:enabel ;0:disable*/
+ /*0: 709/601 1: bt2020*/
+ tx_op_color_primary = <0>;
+
+ interrupts = <0 56 1>;
+ interrupt-names = "vsync2";
+ };
+
+ amdolby_vision {
+ compatible = "amlogic, dolby_vision_sm1";
+ dev_name = "aml_amdolby_vision_driver";
+ status = "okay";
+ tv_mode = <0>;/*1:enabel ;0:disable*/
+ };
+
+ /* Audio Related start */
+ spdif_codec:spdif_dummy{
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ status = "okay";
+ };
+ dummy_codec:dummy{
+ #sound-dai-cells = <0>;
+ compatible = "amlogic, aml_dummy_codec";
+ status = "okay";
+ };
+ amlogic_codec:t9015{
+ #sound-dai-cells = <0>;
+ compatible = "amlogic, aml_codec_T9015";
+ reg = <0x0 0xFF632000 0x0 0x2000>;
+ is_auge_used = <1>; /* meson or auge chipset used */
+ tocodec_inout = <1>;
+ tdmout_index = <1>;
+ ch0_sel = <0>;
+ ch1_sel = <1>;
+
+ status = "okay";
+ };
+
+ auge_sound {
+ compatible = "amlogic, g12a-sound-card";
+ aml-audio-card,name = "AML-AUGESOUND";
+
+ aml-audio-card,dai-link@0 {
+ mclk-fs = <128>;
+ /* suffix-name, sync with android audio hal
+ * what's the dai link used for
+ */
+ suffix-name = "alsaPORT-spdifb";
+ cpu {
+ sound-dai = <&spdifb>;
+ system-clock-frequency = <6144000>;
+ };
+ codec {
+ sound-dai = <&spdif_codec>;
+ };
+ };
+
+ aml-audio-card,dai-link@1 {
+ format = "dsp_a";
+ mclk-fs = <512>;
+ //continuous-clock;
+ //bitclock-inversion;
+ //frame-inversion;
+ /* master mode */
+ bitclock-master = <&tdma>;
+ frame-master = <&tdma>;
+ /* slave mode */
+ /*
+ * bitclock-master = <&tdmacodec>;
+ * frame-master = <&tdmacodec>;
+ */
+ suffix-name = "alsaPORT-pcm";
+ tdmacpu: cpu {
+ sound-dai = <&tdma>;
+ dai-tdm-slot-tx-mask =
+ <1>;
+ dai-tdm-slot-rx-mask =
+ <1>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <16>;
+ system-clock-frequency = <256000>;
+ };
+ tdmacodec: codec {
+ sound-dai = <&dummy_codec>;
+ };
+ };
+
+ aml-audio-card,dai-link@2 {
+ format = "i2s";// "dsp_a";
+ mclk-fs = <256>;
+ //continuous-clock;
+ //bitclock-inversion;
+ //frame-inversion;
+ /* master mode */
+ bitclock-master = <&tdmb>;
+ frame-master = <&tdmb>;
+ /* slave mode */
+ //bitclock-master = <&tdmbcodec>;
+ //frame-master = <&tdmbcodec>;
+ /* suffix-name, sync with android audio hal
+ * what's the dai link used for
+ */
+ suffix-name = "alsaPORT-i2s";
+ cpu {
+ sound-dai = <&tdmb>;
+ dai-tdm-slot-tx-mask = <1 1>;
+ dai-tdm-slot-rx-mask = <1 1>;
+ dai-tdm-slot-num = <2>;
+ /*
+ * dai-tdm-slot-tx-mask =
+ * <1 1 1 1 1 1 1 1>;
+ * dai-tdm-slot-rx-mask =
+ * <1 1 1 1 1 1 1 1>;
+ * dai-tdm-slot-num = <8>;
+ */
+ dai-tdm-slot-width = <32>;
+ system-clock-frequency = <12288000>;
+ };
+ tdmbcodec: codec {
+ sound-dai = <&dummy_codec &dummy_codec
+ &amlogic_codec>;
+ };
+ };
+
+ aml-audio-card,dai-link@3 {
+ format = "i2s";
+ mclk-fs = <256>;
+ //continuous-clock;
+ //bitclock-inversion;
+ //frame-inversion;
+ /* master mode */
+ bitclock-master = <&tdmc>;
+ frame-master = <&tdmc>;
+ /* slave mode */
+ //bitclock-master = <&tdmccodec>;
+ //frame-master = <&tdmccodec>;
+ /* suffix-name, sync with android audio hal used for */
+ //suffix-name = "alsaPORT-tdm";
+ cpu {
+ sound-dai = <&tdmc>;
+ dai-tdm-slot-tx-mask = <1 1>;
+ dai-tdm-slot-rx-mask = <1 1>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <32>;
+ system-clock-frequency = <12288000>;
+ };
+ tdmccodec: codec {
+ sound-dai = <&dummy_codec>;
+ };
+ };
+
+ aml-audio-card,dai-link@4 {
+ mclk-fs = <128>;
+ /* suffix-name, sync with android audio hal used for */
+ suffix-name = "alsaPORT-spdif";
+ cpu {
+ sound-dai = <&spdifa>;
+ system-clock-frequency = <6144000>;
+ };
+ codec {
+ sound-dai = <&spdif_codec>;
+ };
+ };
+
+ aml-audio-card,dai-link@5 {
+ mclk-fs = <256>;
+ suffix-name = "alsaPORT-earc";
+ cpu {
+ sound-dai = <&earc>;
+ system-clock-frequency = <12288000>;
+ };
+ codec {
+ sound-dai = <&dummy_codec>;
+ };
+ };
+ };
+ audiolocker: locker {
+ compatible = "amlogic, audiolocker";
+ clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT
+ &clkaudio CLKID_AUDIO_LOCKER_IN
+ &clkaudio CLKID_AUDIO_MCLK_D
+ &clkaudio CLKID_AUDIO_MCLK_E
+ &clkc CLKID_MPLL1
+ &clkc CLKID_MPLL2>;
+ clock-names = "lock_out", "lock_in", "out_src",
+ "in_src", "out_calc", "in_ref";
+ interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "irq";
+ frequency = <49000000>; /* pll */
+ dividor = <49>; /* locker's parent */
+ status = "disabled";
+ };
+ /* Audio Related end */
+ dvb {
+ compatible = "amlogic, dvb";
+ dev_name = "dvb";
+ status = "okay";
+// fe0_mode = "internal";
+// fe0_tuner = <&tuner>;
+ /*"parallel","serial","disable"*/
+// ts2 = "parallel";
+// ts2_control = <0>;
+// ts2_invert = <0>;
+ interrupts = <0 23 1
+ 0 5 1
+ 0 53 1
+ 0 19 1
+ 0 25 1
+ 0 18 1
+ 0 24 1>;
+ interrupt-names = "demux0_irq",
+ "demux1_irq",
+ "demux2_irq",
+ "dvr0_irq",
+ "dvr1_irq",
+ "dvrfill0_fill",
+ "dvrfill1_flush";
+ clocks = <&clkc CLKID_DEMUX
+ &clkc CLKID_AHB_ARB0
+ &clkc CLKID_DOS_PARSER>;
+ clock-names = "demux", "ahbarb0", "uparsertop";
+ };
+ tuner: tuner {
+ compatible = "amlogic, tuner";
+ status = "okay";
+ tuner_name = "mxl661_tuner";
+ tuner_i2c_adap = <&i2c1>;
+ tuner_i2c_addr = <0x60>;
+ tuner_xtal = <0>; /* 0: 16MHz, 1: 24MHz */
+ tuner_xtal_mode = <0>;
+ /* NO_SHARE_XTAL(0)
+ * SLAVE_XTAL_SHARE(1)
+ */
+ tuner_xtal_cap = <30>; /* when tuner_xtal_mode = 1, set 25 */
+ };
+
+
+ p_tsensor: p_tsensor@ff634800 {
+ compatible = "amlogic, r1p1-tsensor";
+ device_name = "meson-pthermal";
+ status = "okay";
+ reg = <0x0 0xff634800 0x0 0x50>,
+ <0x0 0xff800268 0x0 0x4>;
+ cal_type = <0x1>;
+ cal_a = <324>;
+ cal_b = <424>;
+ cal_c = <3159>;
+ cal_d = <9411>;
+ rtemp = <115000>;
+ interrupts = <0 35 0>;
+ clocks = <&clkc CLKID_TS_COMP>; /* CLKID_TS_COMP>;*/
+ clock-names = "ts_comp";
+ #thermal-sensor-cells = <1>;
+ };
+
+ d_tsensor: d_tsensor@ff634c00 {
+ compatible = "amlogic, r1p1-tsensor";
+ device_name = "meson-dthermal";
+ status = "okay";
+ reg = <0x0 0xff634c00 0x0 0x50>,
+ <0x0 0xff800230 0x0 0x4>;
+ cal_type = <0x1>;
+ cal_a = <324>;
+ cal_b = <424>;
+ cal_c = <3159>;
+ cal_d = <9411>;
+ rtemp = <115000>;
+ interrupts = <0 36 0>;
+ clocks = <&clkc CLKID_TS_COMP>; /* CLKID_TS_COMP>;*/
+ clock-names = "ts_comp";
+ #thermal-sensor-cells = <1>;
+ };
+
+ meson_cooldev: meson-cooldev@0 {
+ status = "okay";
+ compatible = "amlogic, meson-cooldev";
+ device_name = "mcooldev";
+ cooling_devices {
+ cpufreq_cool_cluster0 {
+ min_state = <1000000>;
+ dyn_coeff = <125>;
+ cluster_id = <0>;
+ node_name = "cpufreq_cool0";
+ device_type = "cpufreq";
+ };
+ cpucore_cool_cluster0 {
+ min_state = <1>;
+ dyn_coeff = <0>;
+ cluster_id = <0>;
+ node_name = "cpucore_cool0";
+ device_type = "cpucore";
+ };
+ gpufreq_cool {
+ min_state = <400>;
+ dyn_coeff = <215>;
+ gpu_pp = <2>;
+ cluster_id = <0>;
+ node_name = "gpufreq_cool0";
+ device_type = "gpufreq";
+ };
+ gpucore_cool {
+ min_state = <1>;
+ dyn_coeff = <0>;
+ cluster_id = <0>;
+ node_name = "gpucore_cool0";
+ device_type = "gpucore";
+ };
+ };
+ cpufreq_cool0:cpufreq_cool0 {
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ cpucore_cool0:cpucore_cool0 {
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ gpufreq_cool0:gpufreq_cool0 {
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ gpucore_cool0:gpucore_cool0 {
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ };
+ /*meson cooling devices end*/
+
+ thermal-zones {
+ soc_thermal: soc_thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ sustainable-power = <1410>;
+ thermal-sensors = <&p_tsensor 0>;
+ trips {
+ pswitch_on: trip-point@0 {
+ temperature = <65000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ pcontrol: trip-point@1 {
+ temperature = <80000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ phot: trip-point@2 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+ pcritical: trip-point@3 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpufreq_cooling_map {
+ trip = <&pcontrol>;
+ cooling-device = <&cpufreq_cool0 0 14>;
+ contribution = <1024>;
+ };
+ cpucore_cooling_map {
+ trip = <&pcontrol>;
+ cooling-device = <&cpucore_cool0 0 3>;
+ contribution = <1024>;
+ };
+ gpufreq_cooling_map {
+ trip = <&pcontrol>;
+ cooling-device = <&gpufreq_cool0 0 4>;
+ contribution = <1024>;
+ };
+ gpucore_cooling_map {
+ trip = <&pcontrol>;
+ cooling-device = <&gpucore_cool0 0 2>;
+ contribution = <1024>;
+ };
+ };
+ };
+ ddr_thermal: ddr_thermal {
+ polling-delay = <2000>;
+ polling-delay-passive = <1000>;
+ sustainable-power = <1410>;
+ thermal-sensors = <&d_tsensor 1>;
+ trips {
+ dswitch_on: trip-point@0 {
+ temperature = <60000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ dcontrol: trip-point@1 {
+ temperature = <75000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ dhot: trip-point@2 {
+ temperature = <85000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+ dcritical: trip-point@3 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+
+ };
+ };
+ /*thermal zone end*/
+
+ cpu_opp_table0: cpu_opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <760000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <250000000>;
+ opp-microvolt = <760000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <760000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <667000000>;
+ opp-microvolt = <780000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <800000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <810000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1404000000>;
+ opp-microvolt = <820000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <830000>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <860000>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <1704000000>;
+ opp-microvolt = <900000>;
+ };
+ opp10 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <940000>;
+ };
+ opp11 {
+ opp-hz = /bits/ 64 <1908000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp12 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <1010000>;
+ };
+ opp13 {
+ opp-hz = /bits/ 64 <2100000000>;
+ opp-microvolt = <1030000>;
+ };
+ opp14 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-microvolt = <1040000>;
+ };
+ };
+
+ cpufreq-meson {
+ compatible = "amlogic, cpufreq-meson";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_ao_d_pins3>;
+ status = "okay";
+ };
+
+ onewire:onewire {
+ compatible = "w1-gpio";
+ gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+}; /* end of / */
+
+&meson_fb {
+ status = "okay";
+ display_size_default = <1920 1080 1920 2160 32>;
+ mem_size = <0x00800000 0x4b80000 0x100000 0x100000 0x800000>;
+ logo_addr = "0x7f800000";
+ mem_alloc = <1>;
+ pxp_mode = <0>; /** 0:normal mode 1:pxp mode */
+ 4k2k_fb = <1>;
+};
+
+&pwm_AO_cd {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "disabled";
+ pinctrl-names="default";
+ pinctrl-0=<&i2c3_master_pins2>;
+ clock-frequency = <100000>; /* default 100k */
+
+ ft5336@38 {
+ compatible = "edt,edt-ft5336", "ft5x06";
+ reg = <0x38>;
+ interrupt_pin = <&gpio GPIOA_5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio_expander 6 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+};
+
+&i2c_AO {
+ status = "okay";
+ pinctrl-names="default";
+ pinctrl-0=<&ao_i2c_master_pins1>;
+ clock-frequency = <400000>; /* default 100k */
+
+ gpio_expander: gpio-controller@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "okay";
+ };
+
+ hym8563: hym8563@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+
+ #clock-cells = <0>;
+ };
+
+ khadas-mcu {
+ compatible = "khadas-mcu";
+ reg = <0x18>;
+ fan,trig_temp_level0 = <50>;
+ fan,trig_temp_level1 = <60>;
+ fan,trig_temp_level2 = <70>;
+ hwver = "VIM3.V11"; /* Will be updated in uboot. */
+ };
+};
+
+&audiobus {
+ tdma: tdm@0 {
+ compatible = "amlogic, sm1-snd-tdma";
+ #sound-dai-cells = <0>;
+ dai-tdm-lane-slot-mask-in = <0 1>;
+ dai-tdm-lane-slot-mask-out = <1 0>;
+ dai-tdm-clk-sel = <0>;
+ clocks = <&clkaudio CLKID_AUDIO_MCLK_A
+ &clkc CLKID_MPLL0>;
+ clock-names = "mclk", "clk_srcpll";
+ pinctrl-names = "tdm_pins";
+ pinctrl-0 = <&tdmout_a &tdmin_a>;
+
+ status = "okay";
+ };
+
+ tdmb: tdm@1 {
+ compatible = "amlogic, sm1-snd-tdmb";
+ #sound-dai-cells = <0>;
+ dai-tdm-lane-slot-mask-in = <0 1 0 0>;
+ dai-tdm-lane-slot-mask-out = <1 0 0 0>;
+ //dai-tdm-lane-slot-mask-in = <0 0 0 0 0 0 0 0>;
+ //dai-tdm-lane-slot-mask-out = <1 1 1 1 1 1 1 1>;
+ dai-tdm-clk-sel = <1>;
+ clocks = <&clkaudio CLKID_AUDIO_MCLK_B
+ &clkc CLKID_MPLL1
+ &clkc CLKID_MPLL0
+ &clkaudio CLKID_AUDIO_SPDIFOUT_A>;
+ clock-names = "mclk", "clk_srcpll",
+ "samesource_srcpll", "samesource_clk";
+ pinctrl-names = "tdm_pins";
+ /*pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>;*/
+ pinctrl-0 = < &tdmout_b &tdmin_b>;
+ mclk_pad = <0>; /* 0: mclk_0; 1: mclk_1 */
+
+ /*
+ * 0: tdmout_a;
+ * 1: tdmout_b;
+ * 2: tdmout_c;
+ * 3: spdifout;
+ * 4: spdifout_b;
+ */
+ samesource_sel = <3>;
+
+ /*enable default mclk(12.288M), before extern codec start*/
+ start_clk_enable = <1>;
+
+ /*tdm clk tuning enable*/
+ clk_tuning_enable = <1>;
+
+ status = "okay";
+ };
+
+ tdmc: tdm@2 {
+ compatible = "amlogic, sm1-snd-tdmc";
+ #sound-dai-cells = <0>;
+ dai-tdm-lane-slot-mask-in = <1 0 0 0>;
+ #dai-tdm-lane-slot-mask-out = <1 0 1 1>;
+ #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>;
+ #dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>;
+ dai-tdm-clk-sel = <2>;
+
+ clocks = <&clkaudio CLKID_AUDIO_MCLK_C
+ &clkc CLKID_MPLL2>;
+ clock-names = "mclk", "clk_srcpll";
+ pinctrl-names = "tdm_pins";
+ pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>;
+ mclk_pad = <0>; /* 0: mclk_0; 1: mclk_1 */
+
+ status = "okay";
+ };
+
+ tdmlb:tdm@3 {
+ compatible = "amlogic, sm1-snd-tdmlb";
+ #sound-dai-cells = <0>;
+
+ dai-tdm-lane-lb-slot-mask-in = <1 0 0 0>;
+ dai-tdm-clk-sel = <1>;
+
+ clocks = <&clkaudio CLKID_AUDIO_MCLK_B
+ &clkc CLKID_MPLL1>;
+ clock-names = "mclk", "clk_srcpll";
+
+ /*
+ * select tdmin_lb src;
+ * AXG
+ * 0: TDMOUTA
+ * 1: TDMOUTB
+ * 2: TDMOUTC
+ * 3: PAD_TDMINA
+ * 4: PAD_TDMINB
+ * 5: PAD_TDMINC
+ *
+ * G12A/G12B
+ * 0: TDMOUTA
+ * 1: TDMOUTB
+ * 2: TDMOUTC
+ * 3: PAD_TDMINA_DIN*
+ * 4: PAD_TDMINB_DIN*
+ * 5: PAD_TDMINC_DIN*
+ * 6: PAD_TDMINA_D*, oe pin
+ * 7: PAD_TDMINB_D*, oe pin
+ *
+ * TL1/SM1
+ * 0: TDMOUTA
+ * 1: TDMOUTB
+ * 2: TDMOUTC
+ * 3: PAD_TDMINA_DIN*
+ * 4: PAD_TDMINB_DIN*
+ * 5: PAD_TDMINC_DIN*
+ * 6: PAD_TDMINA_D*
+ * 7: PAD_TDMINB_D*
+ * 8: PAD_TDMINC_D*
+ * 9: HDMIRX_I2S
+ * 10: ACODEC_ADC
+ */
+ lb-src-sel = <1>;
+
+ status = "disabled";
+ };
+
+ spdifa: spdif@0 {
+ compatible = "amlogic, sm1-snd-spdif-a";
+ #sound-dai-cells = <0>;
+ clocks = <&clkc CLKID_MPLL0
+ &clkc CLKID_FCLK_DIV4
+ &clkaudio CLKID_AUDIO_GATE_SPDIFIN
+ &clkaudio CLKID_AUDIO_GATE_SPDIFOUT_A
+ &clkaudio CLKID_AUDIO_SPDIFIN
+ &clkaudio CLKID_AUDIO_SPDIFOUT_A>;
+ clock-names = "sysclk", "fixed_clk", "gate_spdifin",
+ "gate_spdifout", "clk_spdifin", "clk_spdifout";
+ interrupts =
+ <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "irq_spdifin";
+ pinctrl-names = "spdif_pins",
+ "spdif_pins_mute";
+ pinctrl-0 = <&spdifout>;/* bob remove &spdifin*/
+ pinctrl-1 = <&spdifout_a_mute>;
+
+ /*spdif clk tuning enable*/
+ clk_tuning_enable = <1>;
+
+ status = "okay";
+ };
+ spdifb: spdif@1 {
+ compatible = "amlogic, sm1-snd-spdif-b";
+ #sound-dai-cells = <0>;
+ clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/
+ &clkaudio CLKID_AUDIO_GATE_SPDIFOUT_B
+ &clkaudio CLKID_AUDIO_SPDIFOUT_B>;
+ clock-names = "sysclk",
+ "gate_spdifout", "clk_spdifout";
+
+ status = "okay";
+ };
+
+ asrca: resample@0 {
+ compatible = "amlogic, sm1-resample";
+ clocks = <&clkc CLKID_MPLL3
+ &clkaudio CLKID_AUDIO_MCLK_F
+ &clkaudio CLKID_AUDIO_RESAMPLE_A>;
+ clock-names = "resample_pll", "resample_src", "resample_clk";
+ /*same with toddr_src
+ * TDMIN_A, 0
+ * TDMIN_B, 1
+ * TDMIN_C, 2
+ * SPDIFIN, 3
+ * PDMIN, 4
+ * NONE,
+ * TDMIN_LB, 6
+ * LOOPBACK, 7
+ */
+ resample_module = <4>;
+ status = "disabled";
+ };
+
+ vad:vad {
+ compatible = "amlogic, snd-vad";
+ #sound-dai-cells = <0>;
+
+ clocks = <&clkaudio CLKID_AUDIO_GATE_TOVAD
+ &clkc CLKID_FCLK_DIV5
+ &clkaudio CLKID_AUDIO_VAD>;
+ clock-names = "gate", "pll", "clk";
+
+ interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING
+ GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "irq_wakeup", "irq_frame_sync";
+
+ /*
+ * Data src sel:
+ * 0: tdmin_a;
+ * 1: tdmin_b;
+ * 2: tdmin_c;
+ * 3: spdifin;
+ * 4: pdmin;
+ * 5: loopback_b;
+ * 6: tdmin_lb;
+ * 7: loopback_a;
+ */
+ src = <4>;
+
+ /*
+ * deal with hot word in user space or kernel space
+ * 0: in user space
+ * 1: in kernel space
+ */
+ level = <1>;
+
+ status = "okay";
+ };
+
+ loopbacka:loopback@0 {
+ compatible = "amlogic, sm1-loopbacka";
+ #sound-dai-cells = <0>;
+
+ clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
+ &clkc CLKID_FCLK_DIV3
+ &clkc CLKID_MPLL3
+ &clkaudio CLKID_AUDIO_PDMIN0
+ &clkaudio CLKID_AUDIO_PDMIN1
+ &clkc CLKID_MPLL0
+ &clkaudio CLKID_AUDIO_MCLK_A>;
+ clock-names = "pdm_gate",
+ "pdm_sysclk_srcpll",
+ "pdm_dclk_srcpll",
+ "pdm_dclk",
+ "pdm_sysclk",
+ "tdminlb_mpll",
+ "tdminlb_mclk";
+
+ /* datain src
+ * 0: tdmin_a;
+ * 1: tdmin_b;
+ * 2: tdmin_c;
+ * 3: spdifin;
+ * 4: pdmin;
+ */
+ datain_src = <4>;
+ datain_chnum = <4>;
+ datain_chmask = <0xf>;
+ /* config which data pin for loopback */
+ datain-lane-mask-in = <1 1 0 0>;
+
+ /* calc mclk for datalb */
+ mclk-fs = <256>;
+
+ /* tdmin_lb src
+ * 0: tdmoutA
+ * 1: tdmoutB
+ * 2: tdmoutC
+ * 3: PAD_TDMINA_DIN*, refer to core pinmux
+ * 4: PAD_TDMINB_DIN*, refer to core pinmux
+ * 5: PAD_TDMINC_DIN*, refer to core pinmux
+ * 6: PAD_TDMINA_D*, oe, refer to core pinmux
+ * 7: PAD_TDMINB_D*, oe, refer to core pinmux
+ */
+ /* if tdmin_lb >= 3, use external loopback */
+ datalb_src = <1>;
+ datalb_chnum = <2>;
+ datalb_chmask = <0x3>;
+ /* config which data pin as loopback */
+ datalb-lane-mask-in = <1 0 0 0>;
+
+ status = "disabled";
+ };
+
+ loopbackb:loopback@1 {
+ compatible = "amlogic, sm1-loopbackb";
+ #sound-dai-cells = <0>;
+
+ clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
+ &clkc CLKID_FCLK_DIV3
+ &clkc CLKID_MPLL3
+ &clkaudio CLKID_AUDIO_PDMIN0
+ &clkaudio CLKID_AUDIO_PDMIN1
+ &clkc CLKID_MPLL0
+ &clkaudio CLKID_AUDIO_MCLK_A>;
+ clock-names = "pdm_gate",
+ "pdm_sysclk_srcpll",
+ "pdm_dclk_srcpll",
+ "pdm_dclk",
+ "pdm_sysclk",
+ "tdminlb_mpll",
+ "tdminlb_mclk";
+
+ /* calc mclk for datain_lb */
+ mclk-fs = <256>;
+
+ /* datain src
+ * 0: tdmin_a;
+ * 1: tdmin_b;
+ * 2: tdmin_c;
+ * 3: spdifin;
+ * 4: pdmin;
+ */
+ datain_src = <4>;
+ datain_chnum = <4>;
+ datain_chmask = <0xf>;
+ /* config which data pin for loopback */
+ datain-lane-mask-in = <1 0 1 0>;
+
+ /* tdmin_lb src
+ * 0: tdmoutA
+ * 1: tdmoutB
+ * 2: tdmoutC
+ * 3: PAD_TDMINA_DIN*, refer to core pinmux
+ * 4: PAD_TDMINB_DIN*, refer to core pinmux
+ * 5: PAD_TDMINC_DIN*, refer to core pinmux
+ * 6: PAD_TDMINA_D*, oe, refer to core pinmux
+ * 7: PAD_TDMINB_D*, oe, refer to core pinmux
+ */
+ /* if tdmin_lb >= 3, use external loopback */
+ datalb_src = <1>;
+ datalb_chnum = <2>;
+ datalb_chmask = <0x3>;
+ /* config which data pin as loopback */
+ datalb-lane-mask-in = <1 0 0 0>;
+
+ status = "disabled";
+ };
+ aed:effect {
+ compatible = "amlogic, snd-effect-v3";
+ #sound-dai-cells = <0>;
+
+ clocks = <&clkaudio CLKID_AUDIO_GATE_EQDRC
+ &clkc CLKID_FCLK_DIV5
+ &clkaudio CLKID_AUDIO_EQDRC>;
+ clock-names = "gate", "srcpll", "eqdrc";
+
+ /*
+ * 0:tdmout_a
+ * 1:tdmout_b
+ * 2:tdmout_c
+ * 3:spdifout
+ * 4:spdifout_b
+ */
+ eqdrc_module = <1>;
+ /* max 0xf, each bit for one lane, usually one lane */
+ lane_mask = <0x1>;
+ /* max 0xff, each bit for one channel */
+ channel_mask = <0x3>;
+ status = "disabled";
+ };
+}; /* end of audiobus */
+
++&earc {
++ status = "okay";
++};
++
+&pinctrl_periphs {
+ tdmout_a: tdmout_a {
+ mux { /* GPIOX_11, GPIOX_10, GPIOX_9 */
+ groups = "tdma_sclk",
+ "tdma_fs",
+ "tdma_dout0";
+ function = "tdma_out";
+ };
+ };
+
+ tdmin_a: tdmin_a {
+ mux { /* GPIOX_8 */
+ groups = "tdma_din1";
+ function = "tdma_in";
+ };
+ };
+
+ //tdmb_mclk: tdmb_mclk {
+ // mux {
+ // groups = "mclk0_a";
+ // function = "mclk0";
+ // drive-strength = <2>;
+ // };
+ //};
+ tdmout_b: tdmout_b {
+ mux { /* GPIOA_1, GPIOA_2, GPIOA_3, GPIOA_4, */
+ /* GPIOA_5, GPIOA_6, GPIOA_7, GPIOA_8, */
+ /* GPIOA_9, GPIOA_0*/
+ groups = "tdmb_sclk",
+ "tdmb_fs",
+ "tdmb_dout0";
+ //"tdmb_dout1",
+ //"tdmb_dout2",
+ //"tdmb_dout3_a",
+ //"tdmb_dout4_a",
+ //"tdmb_dout5_a",
+ //"tdmb_dout6_a",
+ //"tdmb_dout7_a0";
+ function = "tdmb_out";
+ drive-strength = <2>;
+ };
+ };
+
+ tdmin_b:tdmin_b {
+ mux { /* GPIOA_4 */
+ groups = "tdmb_din1"
+ /*,"tdmb_slv_sclk", "tdmb_slv_fs"*/;
+ function = "tdmb_in";
+ drive-strength = <2>;
+ };
+ };
+
+ tdmc_mclk: tdmc_mclk {
+ mux { /* GPIOA_11 */
+ groups = "mclk1_a";
+ function = "mclk1";
+ };
+ };
+
+ tdmout_c:tdmout_c {
+ mux { /* GPIOA_12, GPIOA_13, GPIOA_8, GPIOA_7*/
+ groups = "tdmc_sclk_a",
+ "tdmc_fs_a",
+ "tdmc_dout0_a"
+ /*, "tdmc_dout2",
+ * "tdmc_dout3"
+ */;
+ function = "tdmc_out";
+ };
+ };
+
+ tdmin_c:tdmin_c {
+ mux { /* GPIOA_10 */
+ groups = "tdmc_din0_a";
+ function = "tdmc_in";
+ };
+ };
+
+ /*GPIOH_5 */
+ /*bob remove spdifin
+ *spdifin: spdifin {
+ * mux {/* GPIOH_5
+ * groups = "spdif_in_h";
+ * function = "spdif_in";
+ * };
+ *};
+ */
+
+ clk12_24_z_pins:clk12_24_z_pins {
+ mux {
+ groups = "clk12_24_z";
+ function = "clk12_24_ee";
+ drive-strength = <3>;
+ };
+ };
+
+ gen_clk_ee_z: gen_clk_ee_z {
+ mux {
+ groups="gen_clk_ee_z";
+ function="gen_clk_ee";
+ drive-strength = <3>;
+ };
+ };
+
+ cam_dvp_pins:cam_dvp_pins {
+ mux {
+ groups = "bt656_a_vs", "bt656_a_hs", "bt656_a_clk",
+ "bt656_a_din0", "bt656_a_din1", "bt656_a_din2",
+ "bt656_a_din3", "bt656_a_din4", "bt656_a_din5",
+ "bt656_a_din6", "bt656_a_din7";
+ function = "bt656";
+ };
+ };
+
+
+}; /* end of pinctrl_periphs */
+
+&pinctrl_aobus {
+ spdifout: spdifout {
+ mux { /* GPIOAO_10 */
+ groups = "spdif_out_ao";
+ function = "spdif_out_ao";
+ };
+ };
+ spdifout_a_mute: spdifout_a_mute {
+ mux { /* gpiao_10 */
+ groups = "GPIOAO_10";
+ function = "gpio_aobus";
+ };
+ };
+
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ pins = "GPIOAO_6";
+ function = "gpio_aobus";
+ output-low;
+ };
+ };
+}; /* end of pinctrl_aobus */
+
+&audio_data {
+ status = "okay";
+};
+
+&irblaster {
+ status = "disabled";
+};
+
+/* Audio Related End */
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_f_pins2>;
+};
+
+&dwc3 {
+ status = "okay";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <2>;
+ gpio-vbus-power = "GPIOA_6";
+ gpios = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+ otg = <1>;
+};
+
+&dwc2_a {
+ status = "okay";
+ /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/
+ controller-type = <3>;
+};
+
+ðmac {
+ status = "okay";
+ pinctrl-names = "external_eth_pins";
+ pinctrl-0 = <&external_eth_pins>;
+ mc_val = <0x1629>;
+
+ cali_val = <0x60000>;
+ rx_delay = <1>;
+ auto_cali_idx = <0>;
+ internal_phy=<0>;
+};
+
+&uart_A {
+ status = "okay";
+};
+
+/*if you want to use vdin just modify status to "ok"*/
+&vdin0 {
+ /*memory-region = <&vdin0_cma_reserved>;*/
+ status = "okay";
+ /*vdin write mem color depth support:
+ *bit0:support 8bit
+ *bit1:support 9bit
+ *bit2:support 10bit
+ *bit3:support 12bit
+ *bit4:support yuv422 10bit full pack mode (from txl new add)
+ */
+ tv_bit_mode = <0x15>;
+};
+&vdin1 {
+ memory-region = <&vdin1_cma_reserved>;
+ status = "okay";
+ /*vdin write mem color depth support:
+ *bit0:support 8bit
+ *bit1:support 9bit
+ *bit2:support 10bit
+ *bit3:support 12bit
+ */
+ tv_bit_mode = <1>;
+};
+
+
+&sd_emmc_c {
+ status = "okay";
+ emmc {
+ caps = "MMC_CAP_8_BIT_DATA",
+ "MMC_CAP_MMC_HIGHSPEED",
+ "MMC_CAP_SD_HIGHSPEED",
+ "MMC_CAP_NONREMOVABLE",
+ /* "MMC_CAP_1_8V_DDR", */
+ "MMC_CAP_HW_RESET",
+ "MMC_CAP_ERASE",
+ "MMC_CAP_CMD23",
+ "MMC_CAP_DRIVER_TYPE_D";
+ caps2 = "MMC_CAP2_HS200";
+ /*MMC_CAP2_HS400"*/
+ f_min = <400000>;
+ f_max = <200000000>;
+ };
+};
+
+&sd_emmc_b {
+ status = "okay";
+ sd {
+ caps = "MMC_CAP_4_BIT_DATA",
+ "MMC_CAP_MMC_HIGHSPEED",
+ "MMC_CAP_SD_HIGHSPEED";
+ f_min = <400000>;
+ f_max = <50000000>;
+ };
+};
+
+
+&sd_emmc_a {
+ status = "okay";
+ sdio {
+ caps = "MMC_CAP_4_BIT_DATA",
+ "MMC_CAP_MMC_HIGHSPEED",
+ "MMC_CAP_SD_HIGHSPEED",
+ "MMC_CAP_NONREMOVABLE",
+ "MMC_CAP_UHS_SDR12",
+ "MMC_CAP_UHS_SDR25",
+ "MMC_CAP_UHS_SDR50",
+ "MMC_CAP_UHS_SDR104",
+ "MMC_PM_KEEP_POWER",
+ "MMC_CAP_SDIO_IRQ";
+ f_min = <400000>;
+ f_max = <200000000>;
+ };
+};
+
+&remote{
+ status = "okay";
+};
+
+&pcie_A {
+ reset-gpio = <&gpio GPIOA_8 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+};
+
+&meson_cooldev {
+ status = "okay";
+};
+
+&defendkey {
+ status = "okay";
+};
+
+&lcd {
+ clk_path = <1>;
+
+ lcd_cpu-gpios = <&gpio_expander 0 GPIO_ACTIVE_HIGH
+ &gpio_expander 1 GPIO_ACTIVE_HIGH>;
+ lcd_cpu_gpio_names = "GPIO_EXPANDER_0","GPIO_EXPANDER_1";
+};
+
+&gpu{
+ tbl = <&dvfs285_cfg
+ &dvfs400_cfg
+ &dvfs500_cfg
+ &dvfs666_cfg
+ &dvfs800_cfg
+ &dvfs800_cfg>;
+};
+
+&saradc {
+ status = "okay";
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins>;
+ cs-gpios = <&gpio GPIOH_6 0>;
+
+ spidev@0 {
+ status = "okay";
+
+ compatible = "linux,spidev";
+ /* spi default max clock 100Mhz */
+ spi-max-frequency = <100000000>;
+ reg = <0>;
+ };
+};
max_frame_time = <200>; /*set software decoder max frame time*/
};
- map_0: map_0{
- mapname = "khadas-ir";
- customcode = <0xff00>;
- release_delay = <80>;
- size = <13>; /*keymap size*/
- keymap = <REMOTE_KEY(0x14, 116)
- REMOTE_KEY(0x13,139)
- REMOTE_KEY(0x03,103)
- REMOTE_KEY(0x02,108)
- REMOTE_KEY(0x0e,105)
- REMOTE_KEY(0x1a,106)
- REMOTE_KEY(0x07,232)
- REMOTE_KEY(0x58,114)
- REMOTE_KEY(0x5c,63)
- REMOTE_KEY(0x5b,63)
- REMOTE_KEY(0x0b,115)
- REMOTE_KEY(0x01,158)
- REMOTE_KEY(0x48,102)>;
- };
- };
++#ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
+ custom_maps:custom_maps {
+ mapnum = <3>;
+ map0 = <&map_0>;
+ map1 = <&map_1>;
+ map2 = <&map_2>;
+ map_0: map_0{
+ mapname = "amlogic-remote-1";
+ customcode = <0xfb04>;
+ release_delay = <80>;
+ size = <50>; /*keymap size*/
+ keymap = <REMOTE_KEY(0x47, KEY_0)
+ REMOTE_KEY(0x13, KEY_1)
+ REMOTE_KEY(0x10, KEY_2)
+ REMOTE_KEY(0x11, KEY_3)
+ REMOTE_KEY(0x0F, KEY_4)
+ REMOTE_KEY(0x0C, KEY_5)
+ REMOTE_KEY(0x0D, KEY_6)
+ REMOTE_KEY(0x0B, KEY_7)
+ REMOTE_KEY(0x08, KEY_8)
+ REMOTE_KEY(0x09, KEY_9)
+ REMOTE_KEY(0x5C, KEY_RIGHTCTRL)
+ REMOTE_KEY(0x51, KEY_F3)
+ REMOTE_KEY(0x50, KEY_F4)
+ REMOTE_KEY(0x40, KEY_F5)
+ REMOTE_KEY(0x4d, KEY_F6)
+ REMOTE_KEY(0x43, KEY_F7)
+ REMOTE_KEY(0x17, KEY_F8)
+ REMOTE_KEY(0x00, KEY_F9)
+ REMOTE_KEY(0x01, KEY_F10)
+ REMOTE_KEY(0x16, KEY_F11)
+ REMOTE_KEY(0x49, KEY_BACKSPACE)
+ REMOTE_KEY(0x06, KEY_PROPS)
+ REMOTE_KEY(0x14, KEY_UNDO)
+ REMOTE_KEY(0x44, KEY_UP)
+ REMOTE_KEY(0x1D, KEY_DOWN)
+ REMOTE_KEY(0x1C, KEY_LEFT)
+ REMOTE_KEY(0x48, KEY_RIGHT)
+ REMOTE_KEY(0x53, KEY_LEFTMETA)
+ REMOTE_KEY(0x45, KEY_PAGEUP)
+ REMOTE_KEY(0x19, KEY_PAGEDOWN)
+ REMOTE_KEY(0x52, KEY_PAUSE)
+ REMOTE_KEY(0x05, KEY_HANGEUL)
+ REMOTE_KEY(0x59, KEY_HANJA)
+ REMOTE_KEY(0x1b, KEY_SCALE)
+ REMOTE_KEY(0x04, KEY_KPCOMMA)
+ REMOTE_KEY(0x1A, KEY_POWER)
+ REMOTE_KEY(0x0A, KEY_TAB)
+ REMOTE_KEY(0x0e, KEY_MUTE)
+ REMOTE_KEY(0x1F, KEY_HOME)
+ REMOTE_KEY(0x1e, KEY_FRONT)
+ REMOTE_KEY(0x07, KEY_COPY)
+ REMOTE_KEY(0x12, KEY_OPEN)
+ REMOTE_KEY(0x54, KEY_PASTE)
+ REMOTE_KEY(0x02, KEY_FIND)
+ REMOTE_KEY(0x4f, KEY_A)
+ REMOTE_KEY(0x42, KEY_B)
+ REMOTE_KEY(0x5d, KEY_C)
+ REMOTE_KEY(0x4c, KEY_D)
+ REMOTE_KEY(0x58, KEY_CUT)
+ REMOTE_KEY(0x55, KEY_CALC)>;
+ };
+ map_1: map_1{
+ mapname = "amlogic-remote-2";
+ customcode = <0xfe01>;
+ release_delay = <80>;
+ size = <53>;
+ keymap = <REMOTE_KEY(0x01, KEY_1)
+ REMOTE_KEY(0x02, KEY_2)
+ REMOTE_KEY(0x03, KEY_3)
+ REMOTE_KEY(0x04, KEY_4)
+ REMOTE_KEY(0x05, KEY_5)
+ REMOTE_KEY(0x06, KEY_6)
+ REMOTE_KEY(0x07, KEY_7)
+ REMOTE_KEY(0x08, KEY_8)
+ REMOTE_KEY(0x09, KEY_9)
+ REMOTE_KEY(0x0a, KEY_0)
+ REMOTE_KEY(0x1F, KEY_FN_F1)
+ REMOTE_KEY(0x15, KEY_MENU)
+ REMOTE_KEY(0x16, KEY_TAB)
+ REMOTE_KEY(0x0c, KEY_CHANNELUP)
+ REMOTE_KEY(0x0d, KEY_CHANNELDOWN)
+ REMOTE_KEY(0x0e, KEY_VOLUMEUP)
+ REMOTE_KEY(0x0f, KEY_VOLUMEDOWN)
+ REMOTE_KEY(0x11, KEY_HOME)
+ REMOTE_KEY(0x1c, KEY_RIGHT)
+ REMOTE_KEY(0x1b, KEY_LEFT)
+ REMOTE_KEY(0x19, KEY_UP)
+ REMOTE_KEY(0x1a, KEY_DOWN)
+ REMOTE_KEY(0x1d, KEY_ENTER)
+ REMOTE_KEY(0x17, KEY_MUTE)
+ REMOTE_KEY(0x49, KEY_FINANCE)
+ REMOTE_KEY(0x43, KEY_BACK)
+ REMOTE_KEY(0x12, KEY_FN_F4)
+ REMOTE_KEY(0x14, KEY_FN_F5)
+ REMOTE_KEY(0x18, KEY_FN_F6)
+ REMOTE_KEY(0x59, KEY_INFO)
+ REMOTE_KEY(0x5a, KEY_STOPCD)
+ REMOTE_KEY(0x10, KEY_POWER)
+ REMOTE_KEY(0x42, KEY_PREVIOUSSONG)
+ REMOTE_KEY(0x44, KEY_NEXTSONG)
+ REMOTE_KEY(0x1e, KEY_REWIND)
+ REMOTE_KEY(0x4b, KEY_FASTFORWARD)
+ REMOTE_KEY(0x58, KEY_PLAYPAUSE)
+ REMOTE_KEY(0x46, KEY_PROPS)
+ REMOTE_KEY(0x40, KEY_UNDO)
+ REMOTE_KEY(0x38, KEY_SCROLLLOCK)
+ REMOTE_KEY(0x57, KEY_FN)
+ REMOTE_KEY(0x5b, KEY_FN_ESC)
+ REMOTE_KEY(0x54, KEY_RED)
+ REMOTE_KEY(0x4c, KEY_GREEN)
+ REMOTE_KEY(0x4e, KEY_YELLOW)
+ REMOTE_KEY(0x55, KEY_BLUE)
+ REMOTE_KEY(0x53, KEY_BLUETOOTH)
+ REMOTE_KEY(0x52, KEY_WLAN)
+ REMOTE_KEY(0x39, KEY_CAMERA)
+ REMOTE_KEY(0x41, KEY_SOUND)
+ REMOTE_KEY(0x0b, KEY_QUESTION)
+ REMOTE_KEY(0x00, KEY_CHAT)
+ REMOTE_KEY(0x13, KEY_SEARCH)>;
+ };
+ map_2: map_2{
+ mapname = "amlogic-remote-3";
+ customcode = <0xbd02>;
+ release_delay = <80>;
+ size = <17>;
+ keymap = <REMOTE_KEY(0xca,103)
+ REMOTE_KEY(0xd2,108)
+ REMOTE_KEY(0x99,105)
+ REMOTE_KEY(0xc1,106)
+ REMOTE_KEY(0xce,97)
+ REMOTE_KEY(0x45,116)
+ REMOTE_KEY(0xc5,133)
+ REMOTE_KEY(0x80,113)
+ REMOTE_KEY(0xd0,15)
+ REMOTE_KEY(0xd6,125)
+ REMOTE_KEY(0x95,102)
+ REMOTE_KEY(0xdd,104)
+ REMOTE_KEY(0x8c,109)
+ REMOTE_KEY(0x89,131)
+ REMOTE_KEY(0x9c,130)
+ REMOTE_KEY(0x9a,120)
+ REMOTE_KEY(0xcd,121)>;
+ };
+ };
++#else
+ custom_maps:custom_maps {
+ mapnum = <1>;
+ map0 = <&map_0>;
++ map_0: map_0{
++ mapname = "khadas-ir";
++ customcode = <0xff00>;
++ release_delay = <80>;
++ size = <13>; /*keymap size*/
++ keymap = <REMOTE_KEY(0x14, 116)
++ REMOTE_KEY(0x13,139)
++ REMOTE_KEY(0x03,103)
++ REMOTE_KEY(0x02,108)
++ REMOTE_KEY(0x0e,105)
++ REMOTE_KEY(0x1a,106)
++ REMOTE_KEY(0x07,232)
++ REMOTE_KEY(0x58,114)
++ REMOTE_KEY(0x5c,63)
++ REMOTE_KEY(0x5b,63)
++ REMOTE_KEY(0x0b,115)
++ REMOTE_KEY(0x01,158)
++ REMOTE_KEY(0x48,102)>;
++ };
++ };
++#endif
uart_A: serial@ffd24000 {
compatible = "amlogic, meson-uart";
max_frame_time = <200>; /*set software decoder max frame time*/
};
++#ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
+ custom_maps:custom_maps {
+ mapnum = <3>;
+ map0 = <&map_0>;
+ map1 = <&map_1>;
+ map2 = <&map_2>;
+ map_0: map_0{
+ mapname = "amlogic-remote-1";
+ customcode = <0xfb04>;
+ release_delay = <80>;
+ size = <50>; /*keymap size*/
+ keymap = <REMOTE_KEY(0x47, KEY_0)
+ REMOTE_KEY(0x13, KEY_1)
+ REMOTE_KEY(0x10, KEY_2)
+ REMOTE_KEY(0x11, KEY_3)
+ REMOTE_KEY(0x0F, KEY_4)
+ REMOTE_KEY(0x0C, KEY_5)
+ REMOTE_KEY(0x0D, KEY_6)
+ REMOTE_KEY(0x0B, KEY_7)
+ REMOTE_KEY(0x08, KEY_8)
+ REMOTE_KEY(0x09, KEY_9)
+ REMOTE_KEY(0x5C, KEY_RIGHTCTRL)
+ REMOTE_KEY(0x51, KEY_F3)
+ REMOTE_KEY(0x50, KEY_F4)
+ REMOTE_KEY(0x40, KEY_F5)
+ REMOTE_KEY(0x4d, KEY_F6)
+ REMOTE_KEY(0x43, KEY_F7)
+ REMOTE_KEY(0x17, KEY_F8)
+ REMOTE_KEY(0x00, KEY_F9)
+ REMOTE_KEY(0x01, KEY_F10)
+ REMOTE_KEY(0x16, KEY_F11)
+ REMOTE_KEY(0x49, KEY_BACKSPACE)
+ REMOTE_KEY(0x06, KEY_PROPS)
+ REMOTE_KEY(0x14, KEY_UNDO)
+ REMOTE_KEY(0x44, KEY_UP)
+ REMOTE_KEY(0x1D, KEY_DOWN)
+ REMOTE_KEY(0x1C, KEY_LEFT)
+ REMOTE_KEY(0x48, KEY_RIGHT)
+ REMOTE_KEY(0x53, KEY_LEFTMETA)
+ REMOTE_KEY(0x45, KEY_PAGEUP)
+ REMOTE_KEY(0x19, KEY_PAGEDOWN)
+ REMOTE_KEY(0x52, KEY_PAUSE)
+ REMOTE_KEY(0x05, KEY_HANGEUL)
+ REMOTE_KEY(0x59, KEY_HANJA)
+ REMOTE_KEY(0x1b, KEY_SCALE)
+ REMOTE_KEY(0x04, KEY_KPCOMMA)
+ REMOTE_KEY(0x1A, KEY_POWER)
+ REMOTE_KEY(0x0A, KEY_TAB)
+ REMOTE_KEY(0x0e, KEY_MUTE)
+ REMOTE_KEY(0x1F, KEY_HOME)
+ REMOTE_KEY(0x1e, KEY_FRONT)
+ REMOTE_KEY(0x07, KEY_COPY)
+ REMOTE_KEY(0x12, KEY_OPEN)
+ REMOTE_KEY(0x54, KEY_PASTE)
+ REMOTE_KEY(0x02, KEY_FIND)
+ REMOTE_KEY(0x4f, KEY_A)
+ REMOTE_KEY(0x42, KEY_B)
+ REMOTE_KEY(0x5d, KEY_C)
+ REMOTE_KEY(0x4c, KEY_D)
+ REMOTE_KEY(0x58, KEY_CUT)
+ REMOTE_KEY(0x55, KEY_CALC)>;
+ };
+ map_1: map_1{
+ mapname = "amlogic-remote-2";
+ customcode = <0xfe01>;
+ release_delay = <80>;
+ size = <53>;
+ keymap = <REMOTE_KEY(0x01, KEY_1)
+ REMOTE_KEY(0x02, KEY_2)
+ REMOTE_KEY(0x03, KEY_3)
+ REMOTE_KEY(0x04, KEY_4)
+ REMOTE_KEY(0x05, KEY_5)
+ REMOTE_KEY(0x06, KEY_6)
+ REMOTE_KEY(0x07, KEY_7)
+ REMOTE_KEY(0x08, KEY_8)
+ REMOTE_KEY(0x09, KEY_9)
+ REMOTE_KEY(0x0a, KEY_0)
+ REMOTE_KEY(0x1F, KEY_FN_F1)
+ REMOTE_KEY(0x15, KEY_MENU)
+ REMOTE_KEY(0x16, KEY_TAB)
+ REMOTE_KEY(0x0c, KEY_CHANNELUP)
+ REMOTE_KEY(0x0d, KEY_CHANNELDOWN)
+ REMOTE_KEY(0x0e, KEY_VOLUMEUP)
+ REMOTE_KEY(0x0f, KEY_VOLUMEDOWN)
+ REMOTE_KEY(0x11, KEY_HOME)
+ REMOTE_KEY(0x1c, KEY_RIGHT)
+ REMOTE_KEY(0x1b, KEY_LEFT)
+ REMOTE_KEY(0x19, KEY_UP)
+ REMOTE_KEY(0x1a, KEY_DOWN)
+ REMOTE_KEY(0x1d, KEY_ENTER)
+ REMOTE_KEY(0x17, KEY_MUTE)
+ REMOTE_KEY(0x49, KEY_FINANCE)
+ REMOTE_KEY(0x43, KEY_BACK)
+ REMOTE_KEY(0x12, KEY_FN_F4)
+ REMOTE_KEY(0x14, KEY_FN_F5)
+ REMOTE_KEY(0x18, KEY_FN_F6)
+ REMOTE_KEY(0x59, KEY_INFO)
+ REMOTE_KEY(0x5a, KEY_STOPCD)
+ REMOTE_KEY(0x10, KEY_POWER)
+ REMOTE_KEY(0x42, KEY_PREVIOUSSONG)
+ REMOTE_KEY(0x44, KEY_NEXTSONG)
+ REMOTE_KEY(0x1e, KEY_REWIND)
+ REMOTE_KEY(0x4b, KEY_FASTFORWARD)
+ REMOTE_KEY(0x58, KEY_PLAYPAUSE)
+ REMOTE_KEY(0x46, KEY_PROPS)
+ REMOTE_KEY(0x40, KEY_UNDO)
+ REMOTE_KEY(0x38, KEY_SCROLLLOCK)
+ REMOTE_KEY(0x57, KEY_FN)
+ REMOTE_KEY(0x5b, KEY_FN_ESC)
+ REMOTE_KEY(0x54, KEY_RED)
+ REMOTE_KEY(0x4c, KEY_GREEN)
+ REMOTE_KEY(0x4e, KEY_YELLOW)
+ REMOTE_KEY(0x55, KEY_BLUE)
+ REMOTE_KEY(0x53, KEY_BLUETOOTH)
+ REMOTE_KEY(0x52, KEY_WLAN)
+ REMOTE_KEY(0x39, KEY_CAMERA)
+ REMOTE_KEY(0x41, KEY_SOUND)
+ REMOTE_KEY(0x0b, KEY_QUESTION)
+ REMOTE_KEY(0x00, KEY_CHAT)
+ REMOTE_KEY(0x13, KEY_SEARCH)>;
+ };
+ map_2: map_2{
+ mapname = "amlogic-remote-3";
+ customcode = <0xbd02>;
+ release_delay = <80>;
+ size = <17>;
+ keymap = <REMOTE_KEY(0xca,103)
+ REMOTE_KEY(0xd2,108)
+ REMOTE_KEY(0x99,105)
+ REMOTE_KEY(0xc1,106)
+ REMOTE_KEY(0xce,97)
+ REMOTE_KEY(0x45,116)
+ REMOTE_KEY(0xc5,133)
+ REMOTE_KEY(0x80,113)
+ REMOTE_KEY(0xd0,15)
+ REMOTE_KEY(0xd6,125)
+ REMOTE_KEY(0x95,102)
+ REMOTE_KEY(0xdd,104)
+ REMOTE_KEY(0x8c,109)
+ REMOTE_KEY(0x89,131)
+ REMOTE_KEY(0x9c,130)
+ REMOTE_KEY(0x9a,120)
+ REMOTE_KEY(0xcd,121)>;
+ };
+ };
++#else
+ custom_maps:custom_maps {
+ mapnum = <1>;
+ map0 = <&map_0>;
+ map_0: map_0{
+ mapname = "khadas-ir";
+ customcode = <0xff00>;
+ release_delay = <80>;
+ size = <13>; /*keymap size*/
+ keymap = <REMOTE_KEY(0x14, 116)
+ REMOTE_KEY(0x13,139)
+ REMOTE_KEY(0x03,103)
+ REMOTE_KEY(0x02,108)
+ REMOTE_KEY(0x0e,105)
+ REMOTE_KEY(0x1a,106)
+ REMOTE_KEY(0x07,28)
+ REMOTE_KEY(0x58,114)
+ REMOTE_KEY(0x5c,63)
+ REMOTE_KEY(0x5b,63)
+ REMOTE_KEY(0x0b,115)
+ REMOTE_KEY(0x01,158)
+ REMOTE_KEY(0x48,102)>;
+ };
+ };
++#endif
uart_A: serial@ffd24000 {
compatible = "amlogic, meson-uart";
};
cpufreq_cooling_map1 {
trip = <&pcontrol>;
- cooling-device = <&cpufreq_cool1 0 9>;
+ cooling-device = <&cpufreq_cool1 0 14>;
contribution = <1024>;
};
- cpucore_cooling_map0 {
+ cpucore_cooling_map {
trip = <&pcontrol>;
- cooling-device = <&cpucore_cool0 0 1>;
- contribution = <1024>;
- };
- cpucore_cooling_map1 {
- trip = <&pcontrol>;
- cooling-device = <&cpucore_cool1 0 4>;
+ cooling-device = <&cpucore_cool 0 5>;
contribution = <1024>;
};
gpufreq_cooling_map {
max_frame_time = <200>; /*set software decoder max frame time*/
};
++#ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
+ custom_maps:custom_maps {
+ mapnum = <3>;
+ map0 = <&map_0>;
+ map1 = <&map_1>;
+ map2 = <&map_2>;
+ map_0: map_0{
+ mapname = "amlogic-remote-1";
+ customcode = <0xfb04>;
+ release_delay = <80>;
+ size = <50>; /*keymap size*/
+ keymap = <REMOTE_KEY(0x47, KEY_0)
+ REMOTE_KEY(0x13, KEY_1)
+ REMOTE_KEY(0x10, KEY_2)
+ REMOTE_KEY(0x11, KEY_3)
+ REMOTE_KEY(0x0F, KEY_4)
+ REMOTE_KEY(0x0C, KEY_5)
+ REMOTE_KEY(0x0D, KEY_6)
+ REMOTE_KEY(0x0B, KEY_7)
+ REMOTE_KEY(0x08, KEY_8)
+ REMOTE_KEY(0x09, KEY_9)
+ REMOTE_KEY(0x5C, KEY_RIGHTCTRL)
+ REMOTE_KEY(0x51, KEY_F3)
+ REMOTE_KEY(0x50, KEY_F4)
+ REMOTE_KEY(0x40, KEY_F5)
+ REMOTE_KEY(0x4d, KEY_F6)
+ REMOTE_KEY(0x43, KEY_F7)
+ REMOTE_KEY(0x17, KEY_F8)
+ REMOTE_KEY(0x00, KEY_F9)
+ REMOTE_KEY(0x01, KEY_F10)
+ REMOTE_KEY(0x16, KEY_F11)
+ REMOTE_KEY(0x49, KEY_BACKSPACE)
+ REMOTE_KEY(0x06, KEY_PROPS)
+ REMOTE_KEY(0x14, KEY_UNDO)
+ REMOTE_KEY(0x44, KEY_UP)
+ REMOTE_KEY(0x1D, KEY_DOWN)
+ REMOTE_KEY(0x1C, KEY_LEFT)
+ REMOTE_KEY(0x48, KEY_RIGHT)
+ REMOTE_KEY(0x53, KEY_LEFTMETA)
+ REMOTE_KEY(0x45, KEY_PAGEUP)
+ REMOTE_KEY(0x19, KEY_PAGEDOWN)
+ REMOTE_KEY(0x52, KEY_PAUSE)
+ REMOTE_KEY(0x05, KEY_HANGEUL)
+ REMOTE_KEY(0x59, KEY_HANJA)
+ REMOTE_KEY(0x1b, KEY_SCALE)
+ REMOTE_KEY(0x04, KEY_KPCOMMA)
+ REMOTE_KEY(0x1A, KEY_POWER)
+ REMOTE_KEY(0x0A, KEY_TAB)
+ REMOTE_KEY(0x0e, KEY_MUTE)
+ REMOTE_KEY(0x1F, KEY_HOME)
+ REMOTE_KEY(0x1e, KEY_FRONT)
+ REMOTE_KEY(0x07, KEY_COPY)
+ REMOTE_KEY(0x12, KEY_OPEN)
+ REMOTE_KEY(0x54, KEY_PASTE)
+ REMOTE_KEY(0x02, KEY_FIND)
+ REMOTE_KEY(0x4f, KEY_A)
+ REMOTE_KEY(0x42, KEY_B)
+ REMOTE_KEY(0x5d, KEY_C)
+ REMOTE_KEY(0x4c, KEY_D)
+ REMOTE_KEY(0x58, KEY_CUT)
+ REMOTE_KEY(0x55, KEY_CALC)>;
+ };
+ map_1: map_1{
+ mapname = "amlogic-remote-2";
+ customcode = <0xfe01>;
+ release_delay = <80>;
+ size = <53>;
+ keymap = <REMOTE_KEY(0x01, KEY_1)
+ REMOTE_KEY(0x02, KEY_2)
+ REMOTE_KEY(0x03, KEY_3)
+ REMOTE_KEY(0x04, KEY_4)
+ REMOTE_KEY(0x05, KEY_5)
+ REMOTE_KEY(0x06, KEY_6)
+ REMOTE_KEY(0x07, KEY_7)
+ REMOTE_KEY(0x08, KEY_8)
+ REMOTE_KEY(0x09, KEY_9)
+ REMOTE_KEY(0x0a, KEY_0)
+ REMOTE_KEY(0x1F, KEY_FN_F1)
+ REMOTE_KEY(0x15, KEY_MENU)
+ REMOTE_KEY(0x16, KEY_TAB)
+ REMOTE_KEY(0x0c, KEY_CHANNELUP)
+ REMOTE_KEY(0x0d, KEY_CHANNELDOWN)
+ REMOTE_KEY(0x0e, KEY_VOLUMEUP)
+ REMOTE_KEY(0x0f, KEY_VOLUMEDOWN)
+ REMOTE_KEY(0x11, KEY_HOME)
+ REMOTE_KEY(0x1c, KEY_RIGHT)
+ REMOTE_KEY(0x1b, KEY_LEFT)
+ REMOTE_KEY(0x19, KEY_UP)
+ REMOTE_KEY(0x1a, KEY_DOWN)
+ REMOTE_KEY(0x1d, KEY_ENTER)
+ REMOTE_KEY(0x17, KEY_MUTE)
+ REMOTE_KEY(0x49, KEY_FINANCE)
+ REMOTE_KEY(0x43, KEY_BACK)
+ REMOTE_KEY(0x12, KEY_FN_F4)
+ REMOTE_KEY(0x14, KEY_FN_F5)
+ REMOTE_KEY(0x18, KEY_FN_F6)
+ REMOTE_KEY(0x59, KEY_INFO)
+ REMOTE_KEY(0x5a, KEY_STOPCD)
+ REMOTE_KEY(0x10, KEY_POWER)
+ REMOTE_KEY(0x42, KEY_PREVIOUSSONG)
+ REMOTE_KEY(0x44, KEY_NEXTSONG)
+ REMOTE_KEY(0x1e, KEY_REWIND)
+ REMOTE_KEY(0x4b, KEY_FASTFORWARD)
+ REMOTE_KEY(0x58, KEY_PLAYPAUSE)
+ REMOTE_KEY(0x46, KEY_PROPS)
+ REMOTE_KEY(0x40, KEY_UNDO)
+ REMOTE_KEY(0x38, KEY_SCROLLLOCK)
+ REMOTE_KEY(0x57, KEY_FN)
+ REMOTE_KEY(0x5b, KEY_FN_ESC)
+ REMOTE_KEY(0x54, KEY_RED)
+ REMOTE_KEY(0x4c, KEY_GREEN)
+ REMOTE_KEY(0x4e, KEY_YELLOW)
+ REMOTE_KEY(0x55, KEY_BLUE)
+ REMOTE_KEY(0x53, KEY_BLUETOOTH)
+ REMOTE_KEY(0x52, KEY_WLAN)
+ REMOTE_KEY(0x39, KEY_CAMERA)
+ REMOTE_KEY(0x41, KEY_SOUND)
+ REMOTE_KEY(0x0b, KEY_QUESTION)
+ REMOTE_KEY(0x00, KEY_CHAT)
+ REMOTE_KEY(0x13, KEY_SEARCH)>;
+ };
+ map_2: map_2{
+ mapname = "amlogic-remote-3";
+ customcode = <0xbd02>;
+ release_delay = <80>;
+ size = <17>;
+ keymap = <REMOTE_KEY(0xca,103)
+ REMOTE_KEY(0xd2,108)
+ REMOTE_KEY(0x99,105)
+ REMOTE_KEY(0xc1,106)
+ REMOTE_KEY(0xce,97)
+ REMOTE_KEY(0x45,116)
+ REMOTE_KEY(0xc5,133)
+ REMOTE_KEY(0x80,113)
+ REMOTE_KEY(0xd0,15)
+ REMOTE_KEY(0xd6,125)
+ REMOTE_KEY(0x95,102)
+ REMOTE_KEY(0xdd,104)
+ REMOTE_KEY(0x8c,109)
+ REMOTE_KEY(0x89,131)
+ REMOTE_KEY(0x9c,130)
+ REMOTE_KEY(0x9a,120)
+ REMOTE_KEY(0xcd,121)>;
+ };
+ };
++#else
+ custom_maps:custom_maps {
+ mapnum = <1>;
+ map0 = <&map_0>;
+ map_0: map_0{
+ mapname = "khadas-ir";
+ customcode = <0xff00>;
+ release_delay = <80>;
+ size = <13>; /*keymap size*/
+ keymap = <REMOTE_KEY(0x14, 116)
+ REMOTE_KEY(0x13,139)
+ REMOTE_KEY(0x03,103)
+ REMOTE_KEY(0x02,108)
+ REMOTE_KEY(0x0e,105)
+ REMOTE_KEY(0x1a,106)
+ REMOTE_KEY(0x07,232)
+ REMOTE_KEY(0x58,114)
+ REMOTE_KEY(0x5c,63)
+ REMOTE_KEY(0x5b,63)
+ REMOTE_KEY(0x0b,115)
+ REMOTE_KEY(0x01,158)
+ REMOTE_KEY(0x48,102)>;
+ };
+ };
++#endif
uart_A: serial@ffd24000 {
compatible = "amlogic, meson-uart";
max_frame_time = <200>; /*set software decoder max frame time*/
};
++#ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
+ custom_maps:custom_maps {
+ mapnum = <3>;
+ map0 = <&map_0>;
+ map1 = <&map_1>;
+ map2 = <&map_2>;
+ map_0: map_0{
+ mapname = "amlogic-remote-1";
+ customcode = <0xfb04>;
+ release_delay = <80>;
+ size = <50>; /*keymap size*/
+ keymap = <REMOTE_KEY(0x47, KEY_0)
+ REMOTE_KEY(0x13, KEY_1)
+ REMOTE_KEY(0x10, KEY_2)
+ REMOTE_KEY(0x11, KEY_3)
+ REMOTE_KEY(0x0F, KEY_4)
+ REMOTE_KEY(0x0C, KEY_5)
+ REMOTE_KEY(0x0D, KEY_6)
+ REMOTE_KEY(0x0B, KEY_7)
+ REMOTE_KEY(0x08, KEY_8)
+ REMOTE_KEY(0x09, KEY_9)
+ REMOTE_KEY(0x5C, KEY_RIGHTCTRL)
+ REMOTE_KEY(0x51, KEY_F3)
+ REMOTE_KEY(0x50, KEY_F4)
+ REMOTE_KEY(0x40, KEY_F5)
+ REMOTE_KEY(0x4d, KEY_F6)
+ REMOTE_KEY(0x43, KEY_F7)
+ REMOTE_KEY(0x17, KEY_F8)
+ REMOTE_KEY(0x00, KEY_F9)
+ REMOTE_KEY(0x01, KEY_F10)
+ REMOTE_KEY(0x16, KEY_F11)
+ REMOTE_KEY(0x49, KEY_BACKSPACE)
+ REMOTE_KEY(0x06, KEY_PROPS)
+ REMOTE_KEY(0x14, KEY_UNDO)
+ REMOTE_KEY(0x44, KEY_UP)
+ REMOTE_KEY(0x1D, KEY_DOWN)
+ REMOTE_KEY(0x1C, KEY_LEFT)
+ REMOTE_KEY(0x48, KEY_RIGHT)
+ REMOTE_KEY(0x53, KEY_LEFTMETA)
+ REMOTE_KEY(0x45, KEY_PAGEUP)
+ REMOTE_KEY(0x19, KEY_PAGEDOWN)
+ REMOTE_KEY(0x52, KEY_PAUSE)
+ REMOTE_KEY(0x05, KEY_HANGEUL)
+ REMOTE_KEY(0x59, KEY_HANJA)
+ REMOTE_KEY(0x1b, KEY_SCALE)
+ REMOTE_KEY(0x04, KEY_KPCOMMA)
+ REMOTE_KEY(0x1A, KEY_POWER)
+ REMOTE_KEY(0x0A, KEY_TAB)
+ REMOTE_KEY(0x0e, KEY_MUTE)
+ REMOTE_KEY(0x1F, KEY_HOME)
+ REMOTE_KEY(0x1e, KEY_FRONT)
+ REMOTE_KEY(0x07, KEY_COPY)
+ REMOTE_KEY(0x12, KEY_OPEN)
+ REMOTE_KEY(0x54, KEY_PASTE)
+ REMOTE_KEY(0x02, KEY_FIND)
+ REMOTE_KEY(0x4f, KEY_A)
+ REMOTE_KEY(0x42, KEY_B)
+ REMOTE_KEY(0x5d, KEY_C)
+ REMOTE_KEY(0x4c, KEY_D)
+ REMOTE_KEY(0x58, KEY_CUT)
+ REMOTE_KEY(0x55, KEY_CALC)>;
+ };
+ map_1: map_1{
+ mapname = "amlogic-remote-2";
+ customcode = <0xfe01>;
+ release_delay = <80>;
+ size = <53>;
+ keymap = <REMOTE_KEY(0x01, KEY_1)
+ REMOTE_KEY(0x02, KEY_2)
+ REMOTE_KEY(0x03, KEY_3)
+ REMOTE_KEY(0x04, KEY_4)
+ REMOTE_KEY(0x05, KEY_5)
+ REMOTE_KEY(0x06, KEY_6)
+ REMOTE_KEY(0x07, KEY_7)
+ REMOTE_KEY(0x08, KEY_8)
+ REMOTE_KEY(0x09, KEY_9)
+ REMOTE_KEY(0x0a, KEY_0)
+ REMOTE_KEY(0x1F, KEY_FN_F1)
+ REMOTE_KEY(0x15, KEY_MENU)
+ REMOTE_KEY(0x16, KEY_TAB)
+ REMOTE_KEY(0x0c, KEY_CHANNELUP)
+ REMOTE_KEY(0x0d, KEY_CHANNELDOWN)
+ REMOTE_KEY(0x0e, KEY_VOLUMEUP)
+ REMOTE_KEY(0x0f, KEY_VOLUMEDOWN)
+ REMOTE_KEY(0x11, KEY_HOME)
+ REMOTE_KEY(0x1c, KEY_RIGHT)
+ REMOTE_KEY(0x1b, KEY_LEFT)
+ REMOTE_KEY(0x19, KEY_UP)
+ REMOTE_KEY(0x1a, KEY_DOWN)
+ REMOTE_KEY(0x1d, KEY_ENTER)
+ REMOTE_KEY(0x17, KEY_MUTE)
+ REMOTE_KEY(0x49, KEY_FINANCE)
+ REMOTE_KEY(0x43, KEY_BACK)
+ REMOTE_KEY(0x12, KEY_FN_F4)
+ REMOTE_KEY(0x14, KEY_FN_F5)
+ REMOTE_KEY(0x18, KEY_FN_F6)
+ REMOTE_KEY(0x59, KEY_INFO)
+ REMOTE_KEY(0x5a, KEY_STOPCD)
+ REMOTE_KEY(0x10, KEY_POWER)
+ REMOTE_KEY(0x42, KEY_PREVIOUSSONG)
+ REMOTE_KEY(0x44, KEY_NEXTSONG)
+ REMOTE_KEY(0x1e, KEY_REWIND)
+ REMOTE_KEY(0x4b, KEY_FASTFORWARD)
+ REMOTE_KEY(0x58, KEY_PLAYPAUSE)
+ REMOTE_KEY(0x46, KEY_PROPS)
+ REMOTE_KEY(0x40, KEY_UNDO)
+ REMOTE_KEY(0x38, KEY_SCROLLLOCK)
+ REMOTE_KEY(0x57, KEY_FN)
+ REMOTE_KEY(0x5b, KEY_FN_ESC)
+ REMOTE_KEY(0x54, KEY_RED)
+ REMOTE_KEY(0x4c, KEY_GREEN)
+ REMOTE_KEY(0x4e, KEY_YELLOW)
+ REMOTE_KEY(0x55, KEY_BLUE)
+ REMOTE_KEY(0x53, KEY_BLUETOOTH)
+ REMOTE_KEY(0x52, KEY_WLAN)
+ REMOTE_KEY(0x39, KEY_CAMERA)
+ REMOTE_KEY(0x41, KEY_SOUND)
+ REMOTE_KEY(0x0b, KEY_QUESTION)
+ REMOTE_KEY(0x00, KEY_CHAT)
+ REMOTE_KEY(0x13, KEY_SEARCH)>;
+ };
+ map_2: map_2{
+ mapname = "amlogic-remote-3";
+ customcode = <0xbd02>;
+ release_delay = <80>;
+ size = <17>;
+ keymap = <REMOTE_KEY(0xca,103)
+ REMOTE_KEY(0xd2,108)
+ REMOTE_KEY(0x99,105)
+ REMOTE_KEY(0xc1,106)
+ REMOTE_KEY(0xce,97)
+ REMOTE_KEY(0x45,116)
+ REMOTE_KEY(0xc5,133)
+ REMOTE_KEY(0x80,113)
+ REMOTE_KEY(0xd0,15)
+ REMOTE_KEY(0xd6,125)
+ REMOTE_KEY(0x95,102)
+ REMOTE_KEY(0xdd,104)
+ REMOTE_KEY(0x8c,109)
+ REMOTE_KEY(0x89,131)
+ REMOTE_KEY(0x9c,130)
+ REMOTE_KEY(0x9a,120)
+ REMOTE_KEY(0xcd,121)>;
+ };
+ };
++#else
+ custom_maps:custom_maps {
+ mapnum = <2>;
+ map0 = <&map_0>;
+ map1 = <&map_1>;
+ map_0: map_0{
+ mapname = "khadas-ir";
+ customcode = <0xff00>;
+ release_delay = <80>;
+ fn_key_scancode = <0x5c>;
+ fn_key_scancode_other = <0x5b>;
+ cursor_left_scancode = <0x0e>;
+ cursor_right_scancode = <0x1a>;
+ cursor_up_scancode = <0x03>;
+ cursor_down_scancode = <0x02>;
+ cursor_ok_scancode = <0x07>;
+ size = <13>;
+ keymap = <REMOTE_KEY(0x14,116)
+ REMOTE_KEY(0x13,139)
+ REMOTE_KEY(0x03,103)
+ REMOTE_KEY(0x02,108)
+ REMOTE_KEY(0x0e,105)
+ REMOTE_KEY(0x1a,106)
+ REMOTE_KEY(0x07,28)
+ REMOTE_KEY(0x58,114)
+ REMOTE_KEY(0x5c,63)
+ REMOTE_KEY(0x5b,63)
+ REMOTE_KEY(0x0b,115)
+ REMOTE_KEY(0x01,158)
+ REMOTE_KEY(0x48,102)>;
+ };
+
+ map_1: map_1{
+ mapname = "dvb-ir";
+ customcode = <0xfe01>;
+ release_delay = <80>;
+ fn_key_scancode = <0x0d>;
+ cursor_left_scancode = <0x54>;
+ cursor_right_scancode = <0x15>;
+ cursor_up_scancode = <0x59>;
+ cursor_down_scancode = <0x51>;
+ cursor_ok_scancode = <0x55>;
+ size = <45>;
+ keymap = <REMOTE_KEY(0x0d,272)
+ REMOTE_KEY(0x00,116)
+ REMOTE_KEY(0x50,102)
+ REMOTE_KEY(0x41,113)
+ REMOTE_KEY(0x48,115)
+ REMOTE_KEY(0x0b,114)
+ REMOTE_KEY(0x58,139)
+ REMOTE_KEY(0x59,103)
+ REMOTE_KEY(0x51,108)
+ REMOTE_KEY(0x54,105)
+ REMOTE_KEY(0x15,106)
+ REMOTE_KEY(0x55,232)
+ REMOTE_KEY(0x1e,11)
+ REMOTE_KEY(0x13,2)
+ REMOTE_KEY(0x12,3)
+ REMOTE_KEY(0x10,4)
+ REMOTE_KEY(0x17,5)
+ REMOTE_KEY(0x16,6)
+ REMOTE_KEY(0x14,7)
+ REMOTE_KEY(0x1b,8)
+ REMOTE_KEY(0x1a,9)
+ REMOTE_KEY(0x18,10)
+ REMOTE_KEY(0x11,14)
+ REMOTE_KEY(0x07,128)
+ REMOTE_KEY(0x40,121)
+ REMOTE_KEY(0x03,120)
+ REMOTE_KEY(0x01,123)
+ REMOTE_KEY(0x05,122)
+ REMOTE_KEY(0x44,119)
+ REMOTE_KEY(0x19,158)
+ REMOTE_KEY(0x04,104)
+ REMOTE_KEY(0x06,109)
+ REMOTE_KEY(0x5c,365)
+ REMOTE_KEY(0x1d,358)
+ REMOTE_KEY(0x0a,398)
+ REMOTE_KEY(0x4d,399)
+ REMOTE_KEY(0x0e,400)
+ REMOTE_KEY(0x0c,401)
+ REMOTE_KEY(0x1c,750)
+ REMOTE_KEY(0x08,751)
+ REMOTE_KEY(0x45,752)
+ REMOTE_KEY(0x1f,753)
+ REMOTE_KEY(0x4c,754)
+ REMOTE_KEY(0x49,755)
+ REMOTE_KEY(0x09,756)>;
+ };
+ };
++#endif
++
aml_reboot{
compatible = "aml, reboot";
sys_reset = <0x84000009>;
max_frame_time = <200>; /*set software decoder max frame time*/
};
++#ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
+ custom_maps:custom_maps {
+ mapnum = <3>;
+ map0 = <&map_0>;
+ map1 = <&map_1>;
+ map2 = <&map_2>;
+ map_0: map_0{
+ mapname = "amlogic-remote-1";
+ customcode = <0xfb04>;
+ release_delay = <80>;
+ size = <44>; /*keymap size*/
+ keymap = <REMOTE_KEY(0x47, KEY_0)
+ REMOTE_KEY(0x13, KEY_1)
+ REMOTE_KEY(0x10, KEY_2)
+ REMOTE_KEY(0x11, KEY_3)
+ REMOTE_KEY(0x0F, KEY_4)
+ REMOTE_KEY(0x0C, KEY_5)
+ REMOTE_KEY(0x0D, KEY_6)
+ REMOTE_KEY(0x0B, KEY_7)
+ REMOTE_KEY(0x08, KEY_8)
+ REMOTE_KEY(0x09, KEY_9)
+ REMOTE_KEY(0x5C, KEY_RIGHTCTRL)
+ REMOTE_KEY(0x51, KEY_F7)
+ REMOTE_KEY(0x49, KEY_BACKSPACE)
+ REMOTE_KEY(0x06, KEY_PROPS)
+ REMOTE_KEY(0x14, KEY_UNDO)
+ REMOTE_KEY(0x44, KEY_UP)
+ REMOTE_KEY(0x1D, KEY_DOWN)
+ REMOTE_KEY(0x1C, KEY_LEFT)
+ REMOTE_KEY(0x48, KEY_RIGHT)
+ REMOTE_KEY(0x53, KEY_LEFTMETA)
+ REMOTE_KEY(0x45, KEY_PAGEUP)
+ REMOTE_KEY(0x19, KEY_PAGEDOWN)
+ REMOTE_KEY(0x16, KEY_HOME)//
+ REMOTE_KEY(0x52, KEY_PAUSE)
+ REMOTE_KEY(0x05, KEY_HANGEUL)
+ REMOTE_KEY(0x59, KEY_HANJA)
+ REMOTE_KEY(0x1b, KEY_SCALE)
+ REMOTE_KEY(0x04, KEY_KPCOMMA)
+ REMOTE_KEY(0x1A, KEY_POWER)
+ REMOTE_KEY(0x0A, KEY_TAB)
+ REMOTE_KEY(0x0e, KEY_MUTE)
+ REMOTE_KEY(0x15, KEY_F5)
+ REMOTE_KEY(0x1F, KEY_HOME)
+ REMOTE_KEY(0x1e, KEY_FRONT)
+ REMOTE_KEY(0x07, KEY_COPY)
+ REMOTE_KEY(0x12, KEY_OPEN)
+ REMOTE_KEY(0x54, KEY_PASTE)
+ REMOTE_KEY(0x02, KEY_FIND)
+ REMOTE_KEY(0x4f, KEY_A)
+ REMOTE_KEY(0x42, KEY_B)
+ REMOTE_KEY(0x5d, KEY_C)
+ REMOTE_KEY(0x4c, KEY_D)
+ REMOTE_KEY(0x58, KEY_CUT)
+ REMOTE_KEY(0x55, KEY_CALC)>;
+ };
+ map_1: map_1{
+ mapname = "amlogic-remote-2";
+ customcode = <0xfe01>;
+ release_delay = <80>;
+ size = <53>;
+ keymap = <REMOTE_KEY(0x01, KEY_1)
+ REMOTE_KEY(0x02, KEY_2)
+ REMOTE_KEY(0x03, KEY_3)
+ REMOTE_KEY(0x04, KEY_4)
+ REMOTE_KEY(0x05, KEY_5)
+ REMOTE_KEY(0x06, KEY_6)
+ REMOTE_KEY(0x07, KEY_7)
+ REMOTE_KEY(0x08, KEY_8)
+ REMOTE_KEY(0x09, KEY_9)
+ REMOTE_KEY(0x0a, KEY_0)
+ REMOTE_KEY(0x1F, KEY_FN_F1)
+ REMOTE_KEY(0x15, KEY_MENU)
+ REMOTE_KEY(0x16, KEY_TAB)
+ REMOTE_KEY(0x0c, KEY_CHANNELUP)
+ REMOTE_KEY(0x0d, KEY_CHANNELDOWN)
+ REMOTE_KEY(0x0e, KEY_VOLUMEUP)
+ REMOTE_KEY(0x0f, KEY_VOLUMEDOWN)
+ REMOTE_KEY(0x11, KEY_HOME)
+ REMOTE_KEY(0x1c, KEY_RIGHT)
+ REMOTE_KEY(0x1b, KEY_LEFT)
+ REMOTE_KEY(0x19, KEY_UP)
+ REMOTE_KEY(0x1a, KEY_DOWN)
+ REMOTE_KEY(0x1d, KEY_ENTER)
+ REMOTE_KEY(0x17, KEY_MUTE)
+ REMOTE_KEY(0x49, KEY_FINANCE)
+ REMOTE_KEY(0x43, KEY_BACK)
+ REMOTE_KEY(0x12, KEY_FN_F4)
+ REMOTE_KEY(0x14, KEY_FN_F5)
+ REMOTE_KEY(0x18, KEY_FN_F6)
+ REMOTE_KEY(0x59, KEY_INFO)
+ REMOTE_KEY(0x5a, KEY_STOPCD)
+ REMOTE_KEY(0x10, KEY_POWER)
+ REMOTE_KEY(0x42, KEY_PREVIOUSSONG)
+ REMOTE_KEY(0x44, KEY_NEXTSONG)
+ REMOTE_KEY(0x1e, KEY_REWIND)
+ REMOTE_KEY(0x4b, KEY_FASTFORWARD)
+ REMOTE_KEY(0x58, KEY_PLAYPAUSE)
+ REMOTE_KEY(0x46, KEY_PROPS)
+ REMOTE_KEY(0x40, KEY_UNDO)
+ REMOTE_KEY(0x38, KEY_SCROLLLOCK)
+ REMOTE_KEY(0x57, KEY_FN)
+ REMOTE_KEY(0x5b, KEY_FN_ESC)
+ REMOTE_KEY(0x54, KEY_RED)
+ REMOTE_KEY(0x4c, KEY_GREEN)
+ REMOTE_KEY(0x4e, KEY_YELLOW)
+ REMOTE_KEY(0x55, KEY_BLUE)
+ REMOTE_KEY(0x53, KEY_BLUETOOTH)
+ REMOTE_KEY(0x52, KEY_WLAN)
+ REMOTE_KEY(0x39, KEY_CAMERA)
+ REMOTE_KEY(0x41, KEY_SOUND)
+ REMOTE_KEY(0x0b, KEY_QUESTION)
+ REMOTE_KEY(0x00, KEY_CHAT)
+ REMOTE_KEY(0x13, KEY_SEARCH)>;
+ };
+ map_2: map_2{
+ mapname = "amlogic-remote-3";
+ customcode = <0xbd02>;
+ release_delay = <80>;
+ size = <17>;
+ keymap = <REMOTE_KEY(0xca,103)
+ REMOTE_KEY(0xd2,108)
+ REMOTE_KEY(0x99,105)
+ REMOTE_KEY(0xc1,106)
+ REMOTE_KEY(0xce,97)
+ REMOTE_KEY(0x45,116)
+ REMOTE_KEY(0xc5,133)
+ REMOTE_KEY(0x80,113)
+ REMOTE_KEY(0xd0,15)
+ REMOTE_KEY(0xd6,125)
+ REMOTE_KEY(0x95,102)
+ REMOTE_KEY(0xdd,104)
+ REMOTE_KEY(0x8c,109)
+ REMOTE_KEY(0x89,131)
+ REMOTE_KEY(0x9c,130)
+ REMOTE_KEY(0x9a,120)
+ REMOTE_KEY(0xcd,121)>;
+ };
+ };
++#else
+ custom_maps:custom_maps {
+ mapnum = <2>;
+ map0 = <&map_0>;
+ map1 = <&map_1>;
+ map_0: map_0{
+ mapname = "khadas-ir";
+ customcode = <0xff00>;
+ release_delay = <80>;
+ fn_key_scancode = <0x5c>;
+ fn_key_scancode_other = <0x5b>;
+ cursor_left_scancode = <0x0e>;
+ cursor_right_scancode = <0x1a>;
+ cursor_up_scancode = <0x03>;
+ cursor_down_scancode = <0x02>;
+ cursor_ok_scancode = <0x07>;
+ size = <13>;
+ keymap = <REMOTE_KEY(0x14,116)
+ REMOTE_KEY(0x13,139)
+ REMOTE_KEY(0x03,103)
+ REMOTE_KEY(0x02,108)
+ REMOTE_KEY(0x0e,105)
+ REMOTE_KEY(0x1a,106)
+ REMOTE_KEY(0x07,28)
+ REMOTE_KEY(0x58,114)
+ REMOTE_KEY(0x5c,63)
+ REMOTE_KEY(0x5b,63)
+ REMOTE_KEY(0x0b,115)
+ REMOTE_KEY(0x01,158)
+ REMOTE_KEY(0x48,102)>;
+ };
+
+ map_1: map_1{
+ mapname = "dvb-ir";
+ customcode = <0xfe01>;
+ release_delay = <80>;
+ fn_key_scancode = <0x0d>;
+ cursor_left_scancode = <0x54>;
+ cursor_right_scancode = <0x15>;
+ cursor_up_scancode = <0x59>;
+ cursor_down_scancode = <0x51>;
+ cursor_ok_scancode = <0x55>;
+ size = <45>;
+ keymap = <REMOTE_KEY(0x0d,272)
+ REMOTE_KEY(0x00,116)
+ REMOTE_KEY(0x50,102)
+ REMOTE_KEY(0x41,113)
+ REMOTE_KEY(0x48,115)
+ REMOTE_KEY(0x0b,114)
+ REMOTE_KEY(0x58,139)
+ REMOTE_KEY(0x59,103)
+ REMOTE_KEY(0x51,108)
+ REMOTE_KEY(0x54,105)
+ REMOTE_KEY(0x15,106)
+ REMOTE_KEY(0x55,232)
+ REMOTE_KEY(0x1e,11)
+ REMOTE_KEY(0x13,2)
+ REMOTE_KEY(0x12,3)
+ REMOTE_KEY(0x10,4)
+ REMOTE_KEY(0x17,5)
+ REMOTE_KEY(0x16,6)
+ REMOTE_KEY(0x14,7)
+ REMOTE_KEY(0x1b,8)
+ REMOTE_KEY(0x1a,9)
+ REMOTE_KEY(0x18,10)
+ REMOTE_KEY(0x11,14)
+ REMOTE_KEY(0x07,128)
+ REMOTE_KEY(0x40,121)
+ REMOTE_KEY(0x03,120)
+ REMOTE_KEY(0x01,123)
+ REMOTE_KEY(0x05,122)
+ REMOTE_KEY(0x44,119)
+ REMOTE_KEY(0x19,158)
+ REMOTE_KEY(0x04,104)
+ REMOTE_KEY(0x06,109)
+ REMOTE_KEY(0x5c,365)
+ REMOTE_KEY(0x1d,358)
+ REMOTE_KEY(0x0a,398)
+ REMOTE_KEY(0x4d,399)
+ REMOTE_KEY(0x0e,400)
+ REMOTE_KEY(0x0c,401)
+ REMOTE_KEY(0x1c,750)
+ REMOTE_KEY(0x08,751)
+ REMOTE_KEY(0x45,752)
+ REMOTE_KEY(0x1f,753)
+ REMOTE_KEY(0x4c,754)
+ REMOTE_KEY(0x49,755)
+ REMOTE_KEY(0x09,756)>;
+ };
+ };
++#endif
++
aml_reboot{
compatible = "aml, reboot";
sys_reset = <0x84000009>;
max_frame_time = <200>; /*set software decoder max frame time*/
};
++#ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
+ custom_maps:custom_maps {
+ mapnum = <3>;
+ map0 = <&map_0>;
+ map1 = <&map_1>;
+ map2 = <&map_2>;
+ map_0: map_0{
+ mapname = "amlogic-remote-1";
+ customcode = <0xfb04>;
+ release_delay = <80>;
+ size = <50>; /*keymap size*/
+ keymap = <REMOTE_KEY(0x47, KEY_0)
+ REMOTE_KEY(0x13, KEY_1)
+ REMOTE_KEY(0x10, KEY_2)
+ REMOTE_KEY(0x11, KEY_3)
+ REMOTE_KEY(0x0F, KEY_4)
+ REMOTE_KEY(0x0C, KEY_5)
+ REMOTE_KEY(0x0D, KEY_6)
+ REMOTE_KEY(0x0B, KEY_7)
+ REMOTE_KEY(0x08, KEY_8)
+ REMOTE_KEY(0x09, KEY_9)
+ REMOTE_KEY(0x5C, KEY_RIGHTCTRL)
+ REMOTE_KEY(0x51, KEY_F3)
+ REMOTE_KEY(0x50, KEY_F4)
+ REMOTE_KEY(0x40, KEY_F5)
+ REMOTE_KEY(0x4d, KEY_F6)
+ REMOTE_KEY(0x43, KEY_F7)
+ REMOTE_KEY(0x17, KEY_F8)
+ REMOTE_KEY(0x00, KEY_F9)
+ REMOTE_KEY(0x01, KEY_F10)
+ REMOTE_KEY(0x16, KEY_F11)
+ REMOTE_KEY(0x49, KEY_BACKSPACE)
+ REMOTE_KEY(0x06, KEY_PROPS)
+ REMOTE_KEY(0x14, KEY_UNDO)
+ REMOTE_KEY(0x44, KEY_UP)
+ REMOTE_KEY(0x1D, KEY_DOWN)
+ REMOTE_KEY(0x1C, KEY_LEFT)
+ REMOTE_KEY(0x48, KEY_RIGHT)
+ REMOTE_KEY(0x53, KEY_LEFTMETA)
+ REMOTE_KEY(0x45, KEY_PAGEUP)
+ REMOTE_KEY(0x19, KEY_PAGEDOWN)
+ REMOTE_KEY(0x52, KEY_PAUSE)
+ REMOTE_KEY(0x05, KEY_HANGEUL)
+ REMOTE_KEY(0x59, KEY_HANJA)
+ REMOTE_KEY(0x1b, KEY_SCALE)
+ REMOTE_KEY(0x04, KEY_KPCOMMA)
+ REMOTE_KEY(0x1A, KEY_POWER)
+ REMOTE_KEY(0x0A, KEY_TAB)
+ REMOTE_KEY(0x0e, KEY_MUTE)
+ REMOTE_KEY(0x1F, KEY_HOME)
+ REMOTE_KEY(0x1e, KEY_FRONT)
+ REMOTE_KEY(0x07, KEY_COPY)
+ REMOTE_KEY(0x12, KEY_OPEN)
+ REMOTE_KEY(0x54, KEY_PASTE)
+ REMOTE_KEY(0x02, KEY_FIND)
+ REMOTE_KEY(0x4f, KEY_A)
+ REMOTE_KEY(0x42, KEY_B)
+ REMOTE_KEY(0x5d, KEY_C)
+ REMOTE_KEY(0x4c, KEY_D)
+ REMOTE_KEY(0x58, KEY_CUT)
+ REMOTE_KEY(0x55, KEY_CALC)>;
+ };
+ map_1: map_1{
+ mapname = "amlogic-remote-2";
+ customcode = <0xfe01>;
+ release_delay = <80>;
+ size = <53>;
+ keymap = <REMOTE_KEY(0x01, KEY_1)
+ REMOTE_KEY(0x02, KEY_2)
+ REMOTE_KEY(0x03, KEY_3)
+ REMOTE_KEY(0x04, KEY_4)
+ REMOTE_KEY(0x05, KEY_5)
+ REMOTE_KEY(0x06, KEY_6)
+ REMOTE_KEY(0x07, KEY_7)
+ REMOTE_KEY(0x08, KEY_8)
+ REMOTE_KEY(0x09, KEY_9)
+ REMOTE_KEY(0x0a, KEY_0)
+ REMOTE_KEY(0x1F, KEY_FN_F1)
+ REMOTE_KEY(0x15, KEY_MENU)
+ REMOTE_KEY(0x16, KEY_TAB)
+ REMOTE_KEY(0x0c, KEY_CHANNELUP)
+ REMOTE_KEY(0x0d, KEY_CHANNELDOWN)
+ REMOTE_KEY(0x0e, KEY_VOLUMEUP)
+ REMOTE_KEY(0x0f, KEY_VOLUMEDOWN)
+ REMOTE_KEY(0x11, KEY_HOME)
+ REMOTE_KEY(0x1c, KEY_RIGHT)
+ REMOTE_KEY(0x1b, KEY_LEFT)
+ REMOTE_KEY(0x19, KEY_UP)
+ REMOTE_KEY(0x1a, KEY_DOWN)
+ REMOTE_KEY(0x1d, KEY_ENTER)
+ REMOTE_KEY(0x17, KEY_MUTE)
+ REMOTE_KEY(0x49, KEY_FINANCE)
+ REMOTE_KEY(0x43, KEY_BACK)
+ REMOTE_KEY(0x12, KEY_FN_F4)
+ REMOTE_KEY(0x14, KEY_FN_F5)
+ REMOTE_KEY(0x18, KEY_FN_F6)
+ REMOTE_KEY(0x59, KEY_INFO)
+ REMOTE_KEY(0x5a, KEY_STOPCD)
+ REMOTE_KEY(0x10, KEY_POWER)
+ REMOTE_KEY(0x42, KEY_PREVIOUSSONG)
+ REMOTE_KEY(0x44, KEY_NEXTSONG)
+ REMOTE_KEY(0x1e, KEY_REWIND)
+ REMOTE_KEY(0x4b, KEY_FASTFORWARD)
+ REMOTE_KEY(0x58, KEY_PLAYPAUSE)
+ REMOTE_KEY(0x46, KEY_PROPS)
+ REMOTE_KEY(0x40, KEY_UNDO)
+ REMOTE_KEY(0x38, KEY_SCROLLLOCK)
+ REMOTE_KEY(0x57, KEY_FN)
+ REMOTE_KEY(0x5b, KEY_FN_ESC)
+ REMOTE_KEY(0x54, KEY_RED)
+ REMOTE_KEY(0x4c, KEY_GREEN)
+ REMOTE_KEY(0x4e, KEY_YELLOW)
+ REMOTE_KEY(0x55, KEY_BLUE)
+ REMOTE_KEY(0x53, KEY_BLUETOOTH)
+ REMOTE_KEY(0x52, KEY_WLAN)
+ REMOTE_KEY(0x39, KEY_CAMERA)
+ REMOTE_KEY(0x41, KEY_SOUND)
+ REMOTE_KEY(0x0b, KEY_QUESTION)
+ REMOTE_KEY(0x00, KEY_CHAT)
+ REMOTE_KEY(0x13, KEY_SEARCH)>;
+ };
+ map_2: map_2{
+ mapname = "amlogic-remote-3";
+ customcode = <0xbd02>;
+ release_delay = <80>;
+ size = <17>;
+ keymap = <REMOTE_KEY(0xca,103)
+ REMOTE_KEY(0xd2,108)
+ REMOTE_KEY(0x99,105)
+ REMOTE_KEY(0xc1,106)
+ REMOTE_KEY(0xce,97)
+ REMOTE_KEY(0x45,116)
+ REMOTE_KEY(0xc5,133)
+ REMOTE_KEY(0x80,113)
+ REMOTE_KEY(0xd0,15)
+ REMOTE_KEY(0xd6,125)
+ REMOTE_KEY(0x95,102)
+ REMOTE_KEY(0xdd,104)
+ REMOTE_KEY(0x8c,109)
+ REMOTE_KEY(0x89,131)
+ REMOTE_KEY(0x9c,130)
+ REMOTE_KEY(0x9a,120)
+ REMOTE_KEY(0xcd,121)>;
+ };
+ };
++#else
+ custom_maps:custom_maps {
+ mapnum = <1>;
+ map0 = <&map_0>;
+ map_0: map_0{
+ mapname = "khadas-ir";
+ customcode = <0xff00>;
+ release_delay = <80>;
+ fn_key_scancode = <0x5b>;
+ cursor_left_scancode = <0x0e>;
+ cursor_right_scancode = <0x1a>;
+ cursor_up_scancode = <0x03>;
+ cursor_down_scancode = <0x02>;
+ cursor_ok_scancode = <0x07>;
+ size = <13>; /*keymap size*/
+ keymap = <REMOTE_KEY(0x14, 116)
+ REMOTE_KEY(0x13,139)
+ REMOTE_KEY(0x03,103)
+ REMOTE_KEY(0x02,108)
+ REMOTE_KEY(0x0e,105)
+ REMOTE_KEY(0x1a,106)
+ REMOTE_KEY(0x07,28)
+ REMOTE_KEY(0x58,114)
+ REMOTE_KEY(0x5c,63)
+ REMOTE_KEY(0x5b,63)
+ REMOTE_KEY(0x0b,115)
+ REMOTE_KEY(0x01,158)
+ REMOTE_KEY(0x48,102)>;
+ };
+ };
++#endif
uart_A: serial@ffd24000 {
compatible = "amlogic, meson-uart";
seq_printf(m, "%02x", chipid[i]);
seq_puts(m, "\n");
#endif
+ {
+ int ret;
+ char uuid[32];
+ loff_t pos = 0;
+ seq_puts(m, "Serial\t\t: ");
+
+ ret = efuse_read_usr(uuid, sizeof(uuid), &pos);
+ if ((ret < 0) || (ret != sizeof(uuid))) {
+ seq_puts(m, "Unknown\n");
+ } else {
+ for (i = 0; i < sizeof(uuid); i++) {
+ if ((i == 8) || (i == 12) || (i == 16) || (i == 20))
+ seq_putc(m, '-');
+ seq_printf(m, "%c", uuid[i]);
+ }
+ seq_putc(m, '\n');
+ }
+ }
+ #else
+ #ifdef CONFIG_AMLOGIC_CPU_INFO
+ cpuinfo_get_chipid(chipid, CHIPID_LEN);
+ seq_puts(m, "Serial\t\t: ");
+ for (i = 0; i < 16; i++)
+ seq_printf(m, "%02x", chipid[i]);
+ seq_puts(m, "\n");
+ #endif
+ #endif
+ #ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
+ seq_printf(m, "Hardware\t: %s\n", machine_name);
+ seq_printf(m, "Revision\t: %04x\n\n", system_rev);
++#else
+ seq_printf(m, "Hardware\t: %s\n", machine_model);
+ #endif
return 0;
}
#include <asm/xen/hypervisor.h>
#include <asm/mmu_context.h>
+ #include <linux/platform_data/board_odroid.h>
+
phys_addr_t __fdt_pointer __initdata;
+const char *machine_model;
+EXPORT_SYMBOL(machine_model);
+
+ #ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
+ const char *machine_name = "Hardkernel ODROID Ref.";
+ EXPORT_SYMBOL(machine_name);
+
+ unsigned int system_rev = 0;
+ EXPORT_SYMBOL(system_rev);
+
+ static u32 __odroid_model = 0;
+ u32 odroid_model(void)
+ {
+ return __odroid_model;
+ }
+
+ static bool __odroid_amlogic_usb3 = true;
+
+ bool odroid_amlogic_usb3(void)
+ {
+ return __odroid_amlogic_usb3;
+ }
+ #endif
+
/*
* Standard memory resources
*/
name = of_flat_dt_get_machine_name();
if (!name)
return;
+
+ machine_model = name;
+ #ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
+ machine_name = name;
+ #endif
pr_info("Machine model: %s\n", name);
dump_stack_set_arch_desc("%s (DT)", name);
/* Grab the vDSO code pages. */
-- pfn = sym_to_pfn(&vdso_start);
++ pfn = sym_to_pfn(vdso_start);
for (i = 0; i < vdso_pages; i++)
- vdso_pagelist[i + 1] = pfn_to_page(PHYS_PFN(__pa(vdso_start)) + i);
+ vdso_pagelist[i + 1] = pfn_to_page(pfn + i);
vdso_spec[0].pages = &vdso_pagelist[0];
vdso_spec[1].pages = &vdso_pagelist[1];
#endif /* CONFIG_NUMA */
#ifdef CONFIG_HAVE_ARCH_PFN_VALID
--#define PFN_MASK ((1UL << (64 - PAGE_SHIFT)) - 1)
--
int pfn_valid(unsigned long pfn)
{
- return (pfn & PFN_MASK) == pfn && memblock_is_map_memory(pfn << PAGE_SHIFT);
+ phys_addr_t addr = pfn << PAGE_SHIFT;
+
+ if ((addr >> PAGE_SHIFT) != pfn)
+ return 0;
+ return memblock_is_map_memory(addr);
}
EXPORT_SYMBOL(pfn_valid);
#endif
msr cpacr_el1, x6
/* Don't change t0sz here, mask those bits when restoring */
-- mrs x7, tcr_el1
-- bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
++ mrs x5, tcr_el1
++ bfi x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
msr tcr_el1, x8
msr vbar_el1, x9
/*
* Restore oslsr_el1 by writing oslar_el1
*/
-- msr osdlr_el1, x5
ubfx x11, x11, #1, #1
msr oslar_el1, x11
reset_pmuserenr_el0 x0 // Disable PMU access from EL0
KBUILD_CFLAGS += $(call cc-option,-mno-80387)
KBUILD_CFLAGS += $(call cc-option,-mno-fp-ret-in-387)
- # By default gcc and clang use a stack alignment of 16 bytes for x86.
+ KBUILD_CFLAGS += -fno-pic
+
+ # By default gcc and clang use a stack alignment of 16 bytes for x86.
# However the standard kernel entry on x86-64 leaves the stack on an
# 8-byte boundary. If the compiler isn't informed about the actual
# alignment it will generate extra alignment instructions for the
source "drivers/amlogic/dolby_fw/Kconfig"
+ source "drivers/amlogic/ircut/Kconfig"
+
+ source "drivers/amlogic/hifi4dsp/Kconfig"
+
+ source "drivers/amlogic/pixel_probe/Kconfig"
+
+ source "drivers/amlogic/firmware/Kconfig"
+
source "drivers/amlogic/media_modules/Kconfig"
+source "drivers/amlogic/npu/Kconfig"
+
+source "drivers/amlogic/isp_module/Kconfig"
+
endmenu
endif
obj-$(CONFIG_DOLBY_FW) += dolby_fw/
- obj-y += media_modules/
+ obj-$(CONFIG_AMLOGIC_IRCUT) += ircut/
+
+ obj-$(CONFIG_AMLOGIC_PIXEL_PROBE) += pixel_probe/
+
+ obj-$(CONFIG_AMLOGIC_FIRMWARE) += firmware/
+
+ obj-y += media_modules/
+obj-$(CONFIG_AMLOGIC_NPU) += npu/
+obj-y += isp_module/
#include <linux/amlogic/scpi_protocol.h>
#include "../../base/power/opp/opp.h"
#include "meson-cpufreq.h"
+#include <linux/amlogic/cpu_version.h>
+
+#define VIM3_A53_DEFAULT 1800000 /* VIM3 Little Core A53 */
+#define VIM3_A73_DEFAULT 2208000 /* VIM3 Big Core A73 */
+#define VIM3L_A55_DEFAULT 1908000 /* VIM3L Core A55 */
+
+
+static unsigned long max_freq[2] = {0, 0};
-#include <linux/amlogic/cpu_version.h>
+ #ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
+ #include <linux/platform_data/board_odroid.h>
-
-static unsigned long max_freq[2] = {
- 0,
- 0,
-};
+
+ #ifdef CONFIG_ARCH_MESON64_ODROIDN2
+ #define N2_A53_DEFAULT 1896000 /* N2 Core A53 */
+ #define N2_A73_DEFAULT 1800000 /* N2 Core A73 */
+
+ #define N2PLUS_A53_DEFAULT 1908000 /* N2 Plus Core A53 */
+ #define N2PLUS_A73_DEFAULT 2208000 /* N2 Plus Core A73 */
+ #endif
+
+ #ifdef CONFIG_ARCH_MESON64_ODROIDC4
+ #define C4_A55_DEFAULT 1800000 /* C4 Core A55 */
+ #endif
+ #endif
+
static unsigned int meson_cpufreq_get_rate(unsigned int cpu)
{
ret = meson_cpufreq_set_rate(policy, cur_cluster,
freq_old / 1000);
-- cpufreq_freq_transition_end(policy,
- &freqs, ret);
- &freqs, ret);
++ cpufreq_freq_transition_end(policy, &freqs, ret);
}
}
goto free_reg;
}
+ #ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
+ if (board_is_odroidn2() || board_is_odroidc4()
+ || board_is_odroidhc4()) {
+ int i = 0;
+
+ max_freq[cur_cluster] = min(max_freq[cur_cluster],
+ (unsigned long)get_table_max(freq_table[cur_cluster]));
+ for (i = 0; (freq_table[cur_cluster][i].frequency != CPUFREQ_TABLE_END)
+ && max_freq[cur_cluster]; i++) {
+ if (freq_table[cur_cluster][i].frequency > max_freq[cur_cluster]) {
+ pr_info("dvfs [%s] - cluster %d freq %d\n",
+ __func__, cur_cluster,
+ freq_table[cur_cluster][i].frequency);
+
+ freq_table[cur_cluster][i].frequency = CPUFREQ_TABLE_END;
+ }
+ }
+ }
++#else
+ if (is_meson_g12b_cpu() || is_meson_sm1_cpu()) {
+ int i = 0;
+
+ max_freq[cur_cluster] = min(max_freq[cur_cluster], (unsigned long)get_table_max(freq_table[cur_cluster]));
+ for (i = 0; (freq_table[cur_cluster][i].frequency != CPUFREQ_TABLE_END) && max_freq[cur_cluster]; i++) {
+ if (freq_table[cur_cluster][i].frequency > max_freq[cur_cluster]) {
+ freq_table[cur_cluster][i].frequency = CPUFREQ_TABLE_END;
+ }
+ }
+ }
+ #endif
ret = cpufreq_table_validate_and_show(policy, freq_table[cur_cluster]);
if (ret) {
return ret;
}
- static int __init get_max_freq(unsigned int cluster, char *str)
-#ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
+ static int __init get_max_freq_cortex(unsigned int cluster, char *str)
{
int ret;
unsigned long value;
static int __init get_max_freq_a53(char *str)
{
- return get_max_freq(0, str);
+ if (0 == strcmp(machine_model, "Khadas VIM3"))
++ return get_max_freq_cortex(0, str);
++
++#ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
+ if (board_is_odroidn2())
+ return get_max_freq_cortex(0, str);
++#endif
++
return -EINVAL;
}
__setup("max_freq_a53=", get_max_freq_a53);
static int __init get_max_freq_a55(char *str)
{
- return get_max_freq(0, str);
+ if (0 == strcmp(machine_model, "Khadas VIM3L"))
++ return get_max_freq_cortex(0, str);
++
++#ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
+ if (board_is_odroidc4() || board_is_odroidhc4())
+ return get_max_freq_cortex(0, str);
++#endif
++
return -EINVAL;
}
__setup("max_freq_a55=", get_max_freq_a55);
static int __init get_max_freq_a73(char *str)
{
- return get_max_freq(1, str);
+ if (0 == strcmp(machine_model, "Khadas VIM3"))
++ return get_max_freq_cortex(1, str);
++#ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
+ if (board_is_odroidn2())
+ return get_max_freq_cortex(1, str);
++#endif
return -EINVAL;
}
__setup("max_freq_a73=", get_max_freq_a73);
unsigned int cpu = 0;
int ret, i;
+ #ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
+ /* Set the maximum cpufreq when kernel parameter is not given with
+ 'max_freq_<a53|a55|a73>' */
+ if (board_is_odroidn2()) {
+ if (!max_freq[0]) {
+ max_freq[0] = (is_meson_g12b_cpu() && is_meson_rev_a())
+ ? N2_A53_DEFAULT : N2PLUS_A53_DEFAULT;
+ }
+ if (!max_freq[1]) {
+ max_freq[1] = (is_meson_g12b_cpu() && is_meson_rev_a())
+ ? N2_A73_DEFAULT : N2PLUS_A73_DEFAULT;
+ }
+ } else if (board_is_odroidc4() || board_is_odroidhc4()) {
+ if (!max_freq[0])
+ max_freq[0] = C4_A55_DEFAULT;
+ }
++#else
+ if (is_meson_g12b_cpu()) {
+ if (!max_freq[0]) {
+ max_freq[0] = VIM3_A53_DEFAULT;
+ }
+ if (!max_freq[1]) {
+ max_freq[1] = VIM3_A73_DEFAULT;
+ }
+ } else if (is_meson_sm1_cpu()) {
+ if (!max_freq[0])
+ max_freq[0] = VIM3L_A55_DEFAULT;
+ }
+ #endif
for (i = 0; i < MAX_CLUSTERS; i++)
mutex_init(&cluster_lock[i]);
{ .port_id = 46, .port_name = "SANA" }
};
+ static struct ddr_port_desc ddr_port_desc_tm2[] __initdata = {
+ { .port_id = 0, .port_name = "ARM" },
+ { .port_id = 1, .port_name = "MALI" },
+ { .port_id = 2, .port_name = "PCIE" },
+ { .port_id = 3, .port_name = "HDCP" },
+ { .port_id = 4, .port_name = "HEVC FRONT" },
+ { .port_id = 5, .port_name = "TEST" },
+ { .port_id = 6, .port_name = "USB3.0" },
+ { .port_id = 7, .port_name = "DEVICE" },
+ { .port_id = 8, .port_name = "HEVC BACK" },
+ { .port_id = 9, .port_name = "DSPA" },
+ { .port_id = 10, .port_name = "DSPB" },
+ { .port_id = 11, .port_name = "NNA" },
+ { .port_id = 12, .port_name = "PCIE1" },
+ { .port_id = 16, .port_name = "VPU READ1" },
+ { .port_id = 17, .port_name = "VPU READ2" },
+ { .port_id = 18, .port_name = "VPU READ3" },
+ { .port_id = 19, .port_name = "VPU WRITE1" },
+ { .port_id = 20, .port_name = "VPU WRITE2" },
+ { .port_id = 21, .port_name = "VDEC" },
+ { .port_id = 22, .port_name = "HCODEC" },
+ { .port_id = 23, .port_name = "GE2D" },
+ /* start of each device */
+ { .port_id = 32, .port_name = "SPICC1" },
+ { .port_id = 33, .port_name = "USB0" },
+ { .port_id = 34, .port_name = "DMA" },
+ { .port_id = 35, .port_name = "ARB0" },
+ { .port_id = 36, .port_name = "SD_EMMC_B" },
+ { .port_id = 37, .port_name = "USB1" },
+ { .port_id = 38, .port_name = "AUDIO" },
+ { .port_id = 39, .port_name = "AIFIFO" },
+ { .port_id = 40, .port_name = "PARSER1" },
+ { .port_id = 41, .port_name = "PARSER" },
+ { .port_id = 42, .port_name = "AO CPU" },
+ { .port_id = 43, .port_name = "SD_EMMC_C" },
+ { .port_id = 44, .port_name = "SPICC2" },
+ { .port_id = 45, .port_name = "ETHERNET" },
+ { .port_id = 46, .port_name = "SANA" },
+ { .port_id = 47, .port_name = "DEMODE" }
+ };
-
static struct ddr_port_desc *chip_ddr_port;
static unsigned char chip_ddr_port_num;
struct input_dev *input_dev;
};
+static struct input_dev *g_input_dev;
+void send_power_key(int state)
+{
+ if (!g_input_dev)
+ return;
+ if (state) {
+ input_report_key(g_input_dev, KEY_POWER, 1);
+ input_sync(g_input_dev);
+ } else {
+ input_report_key(g_input_dev, KEY_POWER, 0);
+ input_sync(g_input_dev);
+ }
+}
+
+EXPORT_SYMBOL(send_power_key);
+
+ static int __init gpiopower_setup(char *str)
+ {
+ int ret;
+
+ if (str == NULL) {
+ gpiopower = 0;
+ return -EINVAL;
+ }
+
+ ret = kstrtoul(str, 0, &gpiopower);
+
+ pr_info("%s gpiopower : %ld\n", __func__, gpiopower);
+
+ return 0;
+ }
+ __setup("gpiopower=", gpiopower_setup);
+
static irqreturn_t gpio_irq_handler(int irq, void *data)
{
struct gpio_keypad *keypad;
platform_set_drvdata(pdev, keypad);
keypad->count = 0;
keypad->index = -1;
+ g_input_dev = input_dev;
setup_timer(&(keypad->polling_timer),
polling_timer_handler, (unsigned long) keypad);
+
+ device_init_wakeup(&pdev->dev, true);
+
if (keypad->use_irq) {
for (i = 0; i < keypad->key_size; i++) {
keypad->key[i].irq_num =
void ir_cdev_free(struct remote_chip *chip);
++int remote_pulses_malloc(struct remote_chip *chip);
++void remote_pulses_free(struct remote_chip *chip);
int remote_reg_read(struct remote_chip *chip, unsigned char id,
unsigned int reg, unsigned int *val);
int remote_reg_write(struct remote_chip *chip, unsigned char id,
unsigned int reg, unsigned int val);
+ int remote_reg_update_bits(struct remote_chip *chip, unsigned char id,
+ unsigned int reg, unsigned int mask, unsigned int val);
int ir_scancode_sort(struct ir_map_tab *ir_map);
struct ir_map_tab_list *seek_map_tab(struct remote_chip *chip, int custom_code);
+ const struct aml_remote_reg_proto **ir_get_proto_reg(void);
void ir_tab_free(struct ir_map_tab_list *ir_map_list);
++void demod_reset(struct remote_chip *chip);
+ #if defined(CONFIG_IR_HK_LIRC_HELPER)
+ extern void remote_wakeup_decode_type(int dec_type);
+ #endif
#endif
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
val |= REG_EDGE_POL_LOW(idx);
- spin_lock(&ctl->lock);
+ spin_lock_irqsave(&ctl->lock, flags);
+
+ /* Double-edge has priority over all others. If a double-edge gpio
+ * changes to another method's, we need to reset the corresponding bit
+ * of double-edge register.
+ */
+ if (ctl->support_double_edge)
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
+ REG_EDGE_BOTH_EDGE(idx), 0);
+ /* Double-edge has priority over all others. If a double-edge gpio
+ * changes to another method's, we need to reset the corresponding bit
+ * of double-edge register.
+ */
+ if (ctl->support_double_edge)
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
+ REG_EDGE_BOTH_EDGE(idx), 0);
+
meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
REG_EDGE_POL_MASK(idx), val);
.reserved = 0,
.offset = IC_OFFS_V4,
.ic = IC_VER_TL1,
- }
+ },
+ };
- }
+ const struct meson_ddemod_data data_tm2 = {
+ .name = "ddmode_tm2",
+ .icver = {
+ .atsc = IC_ATSC_V2,
+ .dvbt = IC_MD_NONE,
+ .dtmb = IC_DTMB_V3,
+ .dvbc = IC_DVBC_V3,
+ .reserved = 0,
+ .offset = IC_OFFS_V4,
+ .ic = IC_VER_TM2,
++ },
};
static const struct of_device_id meson_ddemod_match[] = {
fb_def_var[index].xres = vinfo->width;
fb_def_var[index].yres = vinfo->height;
++#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ fb_def_var[index].xres_virtual = vinfo->width;
++#else
+ fb_def_var[index].xres_virtual = vinfo->width == 1088 ? 1080 : vinfo->width;
++#endif
fb_def_var[index].yres_virtual = vinfo->height * 2;
fb_def_var[index].bits_per_pixel = 32;
ret = copy_from_user(&sync_request, argp,
sizeof(struct fb_sync_request_s));
break;
+ // Only wait for vsync when not HW decoding.
case FBIO_WAITFORVSYNC:
- if (get_vpu_mem_pd_vmod(VPU_VIU_VD1))
- if (info->node < osd_meson_dev.viu1_osd_count)
-- vsync_timestamp = (s32)osd_wait_vsync_event();
-- else
- vsync_timestamp = 0;
- vsync_timestamp = (s32)osd_wait_vsync_event_viu2();
++ if (info->node < osd_meson_dev.viu1_osd_count) {
++ if (get_vpu_mem_pd_vmod(VPU_VIU_VD1))
++ vsync_timestamp = (s32)osd_wait_vsync_event();
++ else
++ vsync_timestamp = 0;
++ } else {
++ if (get_vpu_mem_pd_vmod(VPU_VIU_VD2))
++ vsync_timestamp = (s32)osd_wait_vsync_event_viu2();
++ else
++ vsync_timestamp = 0;
++ }
ret = copy_to_user(argp, &vsync_timestamp, sizeof(s32));
break;
case FBIO_WAITFORVSYNC_64:
- if (get_vpu_mem_pd_vmod(VPU_VIU_VD1))
- if (info->node < osd_meson_dev.viu1_osd_count)
-- vsync_timestamp_64 = osd_wait_vsync_event();
-- else
- vsync_timestamp_64 = 0;
- vsync_timestamp_64 = osd_wait_vsync_event_viu2();
++ if (info->node < osd_meson_dev.viu1_osd_count) {
++ if (get_vpu_mem_pd_vmod(VPU_VIU_VD1))
++ vsync_timestamp_64 = osd_wait_vsync_event();
++ else
++ vsync_timestamp_64 = 0;
++ } else {
++ if (get_vpu_mem_pd_vmod(VPU_VIU_VD2))
++ vsync_timestamp_64 = osd_wait_vsync_event_viu2();
++ else
++ vsync_timestamp_64 = 0;
++ }
ret = copy_to_user(argp, &vsync_timestamp_64, sizeof(s64));
break;
case FBIOGET_OSD_SCALE_AXIS:
}
#endif
-
/* get meson-fb resource from dt */
prop = of_get_property(pdev->dev.of_node, "scale_mode", NULL);
- if (prop)
+ if (prop) {
prop_idx = of_read_ulong(prop, 1);
- /* Todo: only osd0 */
- osd_set_free_scale_mode_hw(DEV_OSD0, prop_idx);
- prop_idx = 0;
+ /* Todo: only osd0 */
+ osd_set_free_scale_mode_hw(DEV_OSD0, prop_idx);
++ prop_idx = 0;
+ }
+
prop = of_get_property(pdev->dev.of_node, "4k2k_fb", NULL);
- if (prop)
+ if (prop) {
prop_idx = of_read_ulong(prop, 1);
- osd_set_4k2k_fb_mode_hw(prop_idx);
+ osd_set_4k2k_fb_mode_hw(prop_idx);
+ }
+
/* get default display mode from dt */
- ret = of_property_read_string(pdev->dev.of_node, "display_mode_default", &str);
-
+ ret = of_property_read_string(pdev->dev.of_node,
+ "display_mode_default", &str);
+ prop_idx = 0;
prop = of_get_property(pdev->dev.of_node, "pxp_mode", NULL);
- if (prop)
+ if (prop) {
prop_idx = of_read_ulong(prop, 1);
- osd_set_pxp_mode(prop_idx);
+ osd_set_pxp_mode(prop_idx);
+ }
prop = of_get_property(pdev->dev.of_node, "ddr_urgent", NULL);
if (prop) {
},
};
-/* new display modes for odroid-n2 */
-static struct hdmi_format_para fmt_para_vesa_2560x1440p60_16x9 = {
- .vic = HDMIV_2560x1440p60hz,
- .name = "2560x1440p60hz",
- .sname = "2560x1440p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 241500,
- .timing = {
- .pixel_freq = 241500,
- .frac_freq = 241500,
- .h_freq = 98700,
- .v_freq = 60000,
- .vsync_polarity = 0,
- .hsync_polarity = 1,
- .h_active = 2560,
- .h_total = 2720,
- .h_blank = 160,
- .h_front = 48,
- .h_sync = 32,
- .h_back = 80,
- .v_active = 1440,
- .v_total = 1481,
- .v_blank = 41,
- .v_front = 2,
- .v_sync = 5,
- .v_back = 34,
- .v_sync_ln = 1,
- },
- .hdmitx_vinfo = {
- .name = "2560x1440p60hz",
- .mode = VMODE_HDMI,
- .width = 2560,
- .height = 1440,
- .field_height = 1440,
- .aspect_ratio_num = 16,
- .aspect_ratio_den = 9,
- .sync_duration_num = 60,
- .sync_duration_den = 1,
- .video_clk = 241500000,
- .htotal = 2720,
- .vtotal = 1481,
- .viu_color_fmt = COLOR_FMT_YUV444,
- .viu_mux = VIU_MUX_ENCP,
- },
-};
-
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ static struct hdmi_format_para fmt_para_480x320p60_4x3 = {
+ .vic = HDMI_480x320p60_4x3,
+ .name = "480x320p60hz",
+ .sname = "480x320p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 25200,
+ .timing = {
+ .pixel_freq = 25200,
+ .frac_freq = 25200,
+ .h_freq = 31500,
+ .v_freq = 60000,
+ .vsync_polarity = 0, /* -VSync */
+ .hsync_polarity = 0, /* -HSync */
+ .h_active = 480,
+ .h_total = 800,
+ .h_blank = 320,
+ .h_front = 120,
+ .h_sync = 100,
+ .h_back = 100,
+ .v_active = 320,
+ .v_total = 525,
+ .v_blank = 205,
+ .v_front = 8,
+ .v_sync = 8,
+ .v_back = 189,
+ .v_sync_ln = 1,
+ },
+ .hdmitx_vinfo = {
+ .name = "480x320p60hz",
+ .mode = VMODE_HDMI,
+ .width = 480,
+ .height = 320,
+ .field_height = 320,
+ .aspect_ratio_num = 4,
+ .aspect_ratio_den = 3,
+ .sync_duration_num = 60,
+ .sync_duration_den = 1,
+ .video_clk = 25200000,
+ .htotal = 800,
+ .vtotal = 525,
+ .viu_color_fmt = COLOR_FMT_YUV444,
+ .viu_mux = VIU_MUX_ENCP,
+ },
+ };
+
+ static struct hdmi_format_para fmt_para_480x272p60_4x3 = {
+ .vic = HDMI_480x272p60_4x3,
+ .name = "480x272p60hz",
+ .sname = "480x272p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 25200,
+ .timing = {
+ .pixel_freq = 25200,
+ .frac_freq = 25200,
+ .h_freq = 31500,
+ .v_freq = 60000,
+ .vsync_polarity = 0, /* -VSync */
+ .hsync_polarity = 0, /* -HSync */
+ .h_active = 480,
+ .h_total = 800,
+ .h_blank = 320,
+ .h_front = 120,
+ .h_sync = 100,
+ .h_back = 100,
+ .v_active = 272,
+ .v_total = 525,
+ .v_blank = 253,
+ .v_front = 8,
+ .v_sync = 7,
+ .v_back = 238,
+ .v_sync_ln = 1,
+ },
+ .hdmitx_vinfo = {
+ .name = "480x272p60hz",
+ .mode = VMODE_HDMI,
+ .width = 480,
+ .height = 272,
+ .field_height = 272,
+ .aspect_ratio_num = 4,
+ .aspect_ratio_den = 3,
+ .sync_duration_num = 60,
+ .sync_duration_den = 1,
+ .video_clk = 25200000,
+ .htotal = 800,
+ .vtotal = 525,
+ .viu_color_fmt = COLOR_FMT_YUV444,
+ .viu_mux = VIU_MUX_ENCP,
+ },
+ };
+
+ static struct hdmi_format_para fmt_para_480x800p60_4x3 = {
+ .vic = HDMI_480x800p60_4x3,
+ .name = "480x800p60hz",
+ .sname = "480x800p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 32000,
+ .timing = {
+ .pixel_freq = 32000,
+ .frac_freq = 32000,
+ .h_freq = 52600,
+ .v_freq = 62300,
+ .vsync_polarity = 0,
+ .hsync_polarity = 0,
+ .h_active = 480,
+ .h_total = 608,
+ .h_blank = 128,
+ .h_front = 40,
+ .h_sync = 48,
+ .h_back = 40,
+ .v_active = 800,
+ .v_total = 845,
+ .v_blank = 45,
+ .v_front = 13,
+ .v_sync = 3,
+ .v_back = 29,
+ .v_sync_ln = 1,
+ },
+ .hdmitx_vinfo = {
+ .name = "480x800p60hz",
+ .mode = VMODE_HDMI,
+ .width = 480,
+ .height = 800,
+ .field_height = 800,
+ .aspect_ratio_num = 4,
+ .aspect_ratio_den = 3,
+ .sync_duration_num = 60,
+ .sync_duration_den = 1,
+ .video_clk = 32000000,
+ .htotal = 608,
+ .vtotal = 845,
+ .viu_color_fmt = COLOR_FMT_YUV444,
+ .viu_mux = VIU_MUX_ENCP,
+ },
+ };
+
+ static struct hdmi_format_para fmt_para_vesa_3440x1440p60_43x18 = {
+ .vic = HDMIV_3440x1440p60hz,
+ .name = "3440x1440p60hz",
+ .sname = "3440x1440p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 319750,
+ .timing = {
+ .pixel_freq = 319750,
+ .frac_freq = 319750,
+ .h_freq = 88819,
+ .v_freq = 60000,
+ .vsync_polarity = 0, /* -VSync */
+ .hsync_polarity = 1, /* +HSync */
+ .h_active = 3440,
+ .h_total = 3600,
+ .h_blank = 160,
+ .h_front = 48,
+ .h_sync = 32,
+ .h_back = 80,
+ .v_active = 1440,
+ .v_total = 1481,
+ .v_blank = 41,
+ .v_front = 3,
+ .v_sync = 10,
+ .v_back = 28,
+ .v_sync_ln = 1,
+ },
+ .hdmitx_vinfo = {
+ .name = "3440x1440p60hz",
+ .mode = VMODE_HDMI,
+ .width = 3440,
+ .height = 1440,
+ .field_height = 1440,
+ .aspect_ratio_num = 43,
+ .aspect_ratio_den = 19,
+ .sync_duration_num = 60,
+ .sync_duration_den = 1,
+ .video_clk = 319750000,
+ .htotal = 3600,
+ .vtotal = 1481,
+ .viu_color_fmt = COLOR_FMT_YUV444,
+ .viu_mux = VIU_MUX_ENCP,
+ },
+ };
+
+ static struct hdmi_format_para fmt_para_custombuilt = {
+ .vic = HDMI_CUSTOMBUILT,
+ .name = "custombuilt",
+ .sname = "custombuilt",
+ .pixel_repetition_factor = 0,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .timing = {
+ .v_sync_ln = 1,
+ },
+ .hdmitx_vinfo = {
+ .name = "custombuilt",
+ .mode = VMODE_HDMI,
+ .aspect_ratio_num = 16,
+ .aspect_ratio_den = 9,
+ .sync_duration_den = 1,
+ .viu_color_fmt = COLOR_FMT_YUV444,
+ .viu_mux = VIU_MUX_ENCP,
+ },
+ };
+ #endif
+
static struct hdmi_format_para fmt_para_non_hdmi_fmt = {
.vic = HDMI_Unknown,
.name = "invalid",
static struct hdmi_format_para fmt_para_vesa_640x480p60_4x3 = {
.vic = HDMIV_640x480p60hz,
.name = "640x480p60hz",
- .sname = "640x480p60hz",
++ .sname = "640x480p60hz",
.pixel_repetition_factor = 0,
.progress_mode = 1,
.scrambler_en = 0,
.tmds_clk = 25175,
.timing = {
.pixel_freq = 25175,
++#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ .h_freq = 26218,
++#else
+ .h_freq = 31469,
++#endif
.v_freq = 59940,
.vsync = 60,
.vsync_polarity = 0,
static struct hdmi_format_para fmt_para_vesa_800x480p60_4x3 = {
.vic = HDMIV_800x480p60hz,
.name = "800x480p60hz",
- .sname = "800x480p60hz",
++ .sname = "800x480p60hz",
.pixel_repetition_factor = 0,
.progress_mode = 1,
.scrambler_en = 0,
},
};
- .vic = HDMIV_1280x480p60hz,
- .name = "1280x480p60hz",
- .sname = "1280x480p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 43200,
- .timing = {
- .pixel_freq = 43200,
- .h_freq = 30000,
- .v_freq = 60000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1280,
- .h_total = 1440,
- .h_blank = 160,
- .h_front = 48,
- .h_sync = 32,
- .h_back = 80,
- .v_active = 480,
- .v_total = 500,
- .v_blank = 20,
- .v_front = 3,
- .v_sync = 7,
- .v_back = 10,
- .v_sync_ln = 1,
- },
- .hdmitx_vinfo = {
- .name = "1280x480p60hz",
- .mode = VMODE_HDMI,
- .width = 1280,
- .height = 480,
- .field_height = 480,
- .aspect_ratio_num = 8,
- .aspect_ratio_den = 3,
- .sync_duration_num = 60,
- .sync_duration_den = 1,
- .video_clk = 43200000,
- .htotal = 1440,
- .vtotal = 500,
- .fr_adj_type = VOUT_FR_ADJ_HDMI,
- .viu_color_fmt = COLOR_FMT_YUV444,
- .viu_mux = VIU_MUX_ENCP,
- },
+static struct hdmi_format_para fmt_para_vesa_1280x480p60_8x3 = {
-
++ .vic = HDMIV_1280x480p60hz,
++ .name = "1280x480p60hz",
++ .sname = "1280x480p60hz",
++ .pixel_repetition_factor = 0,
++ .progress_mode = 1,
++ .scrambler_en = 0,
++ .tmds_clk_div40 = 0,
++ .tmds_clk = 43200,
++ .timing = {
++ .pixel_freq = 43200,
++ .h_freq = 30000,
++ .v_freq = 60000,
++ .vsync_polarity = 1,
++ .hsync_polarity = 1,
++ .h_active = 1280,
++ .h_total = 1440,
++ .h_blank = 160,
++ .h_front = 48,
++ .h_sync = 32,
++ .h_back = 80,
++ .v_active = 480,
++ .v_total = 500,
++ .v_blank = 20,
++ .v_front = 3,
++ .v_sync = 7,
++ .v_back = 10,
++ .v_sync_ln = 1,
++ },
++ .hdmitx_vinfo = {
++ .name = "1280x480p60hz",
++ .mode = VMODE_HDMI,
++ .width = 1280,
++ .height = 480,
++ .field_height = 480,
++ .aspect_ratio_num = 8,
++ .aspect_ratio_den = 3,
++ .sync_duration_num = 60,
++ .sync_duration_den = 1,
++ .video_clk = 43200000,
++ .htotal = 1440,
++ .vtotal = 500,
++ .fr_adj_type = VOUT_FR_ADJ_HDMI,
++ .viu_color_fmt = COLOR_FMT_YUV444,
++ .viu_mux = VIU_MUX_ENCP,
++ },
+};
+
static struct hdmi_format_para fmt_para_vesa_800x600p60_4x3 = {
.vic = HDMIV_800x600p60hz,
.name = "800x600p60hz",
- .sname = "800x600p60hz",
++ .sname = "800x600p60hz",
.pixel_repetition_factor = 0,
.progress_mode = 1,
.scrambler_en = 0,
static struct hdmi_format_para fmt_para_vesa_854x480p60_427x240 = {
.vic = HDMIV_854x480p60hz,
.name = "854x480p60hz",
- .sname = "1024x600p60hz",
++ .sname = "1024x600p60hz",
.pixel_repetition_factor = 0,
.progress_mode = 1,
.scrambler_en = 0,
static struct hdmi_format_para fmt_para_vesa_1024x600p60_17x10 = {
.vic = HDMIV_1024x600p60hz,
.name = "1024x600p60hz",
- .sname = "1024x768p60hz",
++ .sname = "1024x768p60hz",
.pixel_repetition_factor = 0,
.progress_mode = 1,
.scrambler_en = 0,
static struct hdmi_format_para fmt_para_vesa_1024x768p60_4x3 = {
.vic = HDMIV_1024x768p60hz,
.name = "1024x768p60hz",
- .sname = "1024x768p60hz",
++ .sname = "1024x768p60hz",
.pixel_repetition_factor = 0,
.progress_mode = 1,
.scrambler_en = 0,
.tmds_clk_div40 = 0,
- .tmds_clk = 65000,
++#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ .tmds_clk = 79500,
++#else
++ .tmds_clk = 65000,
++#endif
.timing = {
- .pixel_freq = 65000,
++#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ .pixel_freq = 79500,
++#else
++ .pixel_freq = 65000,
++#endif
.h_freq = 48360,
.v_freq = 60004,
.vsync = 60,
.aspect_ratio_den = 3,
.sync_duration_num = 60,
.sync_duration_den = 1,
- .video_clk = 65000000,
++#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ .video_clk = 79500000,
++#else
++ .video_clk = 65000000,
++#endif
.htotal = 1344,
.vtotal = 806,
.fr_adj_type = VOUT_FR_ADJ_HDMI,
static struct hdmi_format_para fmt_para_vesa_1280x768p60_5x3 = {
.vic = HDMIV_1280x768p60hz,
.name = "1280x768p60hz",
- .sname = "1280x800p60hz",
++ .sname = "1280x800p60hz",
.pixel_repetition_factor = 0,
.progress_mode = 1,
.scrambler_en = 0,
static struct hdmi_format_para fmt_para_vesa_1280x1024p60_5x4 = {
.vic = HDMIV_1280x1024p60hz,
.name = "1280x1024p60hz",
- .sname = "1360x768p60hz",
++ .sname = "1360x768p60hz",
.pixel_repetition_factor = 0,
.progress_mode = 1,
.scrambler_en = 0,
.tmds_clk = 108000,
.timing = {
.pixel_freq = 108000,
- .h_freq = 63981,
++#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ .h_freq = 64080,
++#else
++ .h_freq = 63981,
++#endif
.v_freq = 60020,
.vsync = 60,
.vsync_polarity = 1,
static struct hdmi_format_para fmt_para_vesa_1440x900p60_8x5 = {
.vic = HDMIV_1440x900p60hz,
.name = "1440x900p60hz",
- .sname = "1440x900p60hz",
++ .sname = "1440x900p60hz",
.pixel_repetition_factor = 0,
.progress_mode = 1,
.scrambler_en = 0,
},
};
++#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
++/* new display modes for odroid-n2 */
++static struct hdmi_format_para fmt_para_vesa_2560x1440p60_16x9 = {
++ .vic = HDMIV_2560x1440p60hz,
++ .name = "2560x1440p60hz",
++ .sname = "2560x1440p60hz",
++ .pixel_repetition_factor = 0,
++ .progress_mode = 1,
++ .scrambler_en = 0,
++ .tmds_clk_div40 = 0,
++ .tmds_clk = 241500,
++ .timing = {
++ .pixel_freq = 241500,
++ .frac_freq = 241500,
++ .h_freq = 98700,
++ .v_freq = 60000,
++ .vsync_polarity = 0,
++ .hsync_polarity = 1,
++ .h_active = 2560,
++ .h_total = 2720,
++ .h_blank = 160,
++ .h_front = 48,
++ .h_sync = 32,
++ .h_back = 80,
++ .v_active = 1440,
++ .v_total = 1481,
++ .v_blank = 41,
++ .v_front = 2,
++ .v_sync = 5,
++ .v_back = 34,
++ .v_sync_ln = 1,
++ },
++ .hdmitx_vinfo = {
++ .name = "2560x1440p60hz",
++ .mode = VMODE_HDMI,
++ .width = 2560,
++ .height = 1440,
++ .field_height = 1440,
++ .aspect_ratio_num = 16,
++ .aspect_ratio_den = 9,
++ .sync_duration_num = 60,
++ .sync_duration_den = 1,
++ .video_clk = 241500000,
++ .htotal = 2720,
++ .vtotal = 1481,
++ .viu_color_fmt = COLOR_FMT_YUV444,
++ .viu_mux = VIU_MUX_ENCP,
++ },
++};
++#else
+static struct hdmi_format_para fmt_para_vesa_2560x1440p60_16x9 = {
+ .vic = HDMIV_2560x1440p60hz,
+ .name = "2560x1440p60hz",
+ .sname = "2560x1440p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 241500,
+ .timing = {
+ .pixel_freq = 241500,
+ .h_freq = 88790,
+ .v_freq = 60000,
+ .vsync = 60,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 2560,
+ .h_total = 2720,
+ .h_blank = 160,
+ .h_front = 48,
+ .h_sync = 32,
+ .h_back = 80,
+ .v_active = 1440,
+ .v_total = 1481,
+ .v_blank = 41,
+ .v_front = 2,
+ .v_sync = 5,
+ .v_back = 34,
+ .v_sync_ln = 1,
+ },
+ .hdmitx_vinfo = {
+ .name = "2560x1440p60hz",
+ .mode = VMODE_HDMI,
+ .width = 2560,
+ .height = 1440,
+ .field_height = 1440,
+ .aspect_ratio_num = 16,
+ .aspect_ratio_den = 9,
+ .sync_duration_num = 60,
+ .sync_duration_den = 1,
+ .video_clk = 241500000,
+ .htotal = 2720,
+ .vtotal = 1481,
+ .viu_color_fmt = COLOR_FMT_YUV444,
+ .viu_mux = VIU_MUX_ENCP,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_480x320p60_4x3 = {
+ .vic = HDMIV_480x320p60hz,
+ .name = "480x320p60hz",
+ .sname = "480x320p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 25200,
+ .timing = {
+ .pixel_freq = 25200,
+ .frac_freq = 25200,
+ .h_freq = 31500,
+ .v_freq = 60000,
+ .vsync_polarity = 0, /* -VSync */
+ .hsync_polarity = 0, /* -HSync */
+ .h_active = 480,
+ .h_total = 800,
+ .h_blank = 320,
+ .h_front = 120,
+ .h_sync = 100,
+ .h_back = 100,
+ .v_active = 320,
+ .v_total = 525,
+ .v_blank = 205,
+ .v_front = 8,
+ .v_sync = 8,
+ .v_back = 189,
+ .v_sync_ln = 1,
+ },
+ .hdmitx_vinfo = {
+ .name = "480x320p60hz",
+ .mode = VMODE_HDMI,
+ .width = 480,
+ .height = 320,
+ .field_height = 320,
+ .aspect_ratio_num = 4,
+ .aspect_ratio_den = 3,
+ .sync_duration_num = 60,
+ .sync_duration_den = 1,
+ .video_clk = 25200000,
+ .htotal = 800,
+ .vtotal = 525,
+ .viu_color_fmt = COLOR_FMT_YUV444,
+ .viu_mux = VIU_MUX_ENCP,
+ },
+};
++#endif
+
static struct hdmi_format_para fmt_para_vesa_1600x900p60_16x9 = {
.vic = HDMIV_1600x900p60hz,
.name = "1600x900p60hz",
- .sname = "1600x900p60hz",
++ .sname = "1600x900p60hz",
.pixel_repetition_factor = 0,
.progress_mode = 1,
.scrambler_en = 0,
static struct hdmi_format_para fmt_para_vesa_1600x1200p60_4x3 = {
.vic = HDMIV_1600x1200p60hz,
.name = "1600x1200p60hz",
- .sname = "1600x1200p60hz",
++ .sname = "1600x1200p60hz",
.pixel_repetition_factor = 0,
.progress_mode = 1,
.scrambler_en = 0,
},
};
++#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
static struct hdmi_format_para fmt_para_vesa_1680x1050p60_8x5 = {
.vic = HDMIV_1680x1050p60hz,
.name = "1680x1050p60hz",
- .sname = "1680x1050p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 146250,
+ .timing = {
+ .pixel_freq = 146250,
+ .h_freq = 65340,
+ .v_freq = 59954,
+ .vsync = 60,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1680,
+ .h_total = 2240,
+ .h_blank = 560,
+ .h_front = 104,
+ .h_sync = 176,
+ .h_back = 280,
+ .v_active = 1050,
+ .v_total = 1089,
+ .v_blank = 39,
+ .v_front = 3,
+ .v_sync = 6,
+ .v_back = 30,
+ .v_sync_ln = 1,
+ },
+ .hdmitx_vinfo = {
+ .name = "1680x1050p60hz",
+ .mode = VMODE_HDMI,
+ .width = 1680,
+ .height = 1050,
+ .field_height = 1050,
+ .aspect_ratio_num = 8,
+ .aspect_ratio_den = 5,
+ .sync_duration_num = 60,
+ .sync_duration_den = 1,
+ .video_clk = 146250000,
+ .htotal = 2240,
+ .vtotal = 1089,
+ .fr_adj_type = VOUT_FR_ADJ_HDMI,
+ .viu_color_fmt = COLOR_FMT_YUV444,
+ .viu_mux = VIU_MUX_ENCP,
+ },
+ };
++#else
++static struct hdmi_format_para fmt_para_vesa_1680x1050p60_8x5 = {
++ .vic = HDMIV_1680x1050p60hz,
++ .name = "1680x1050p60hz",
++ .sname = "1680x1050p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 119000,
+ .timing = {
- .pixel_freq = 119000,
- .h_freq = 64673,
- .v_freq = 59883,
++ .pixel_freq = 119000,
++ .h_freq = 64673,
++ .v_freq = 59883,
+ .vsync = 60,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1680,
- .h_total = 1840,
- .h_blank = 160,
- .h_front = 48,
- .h_sync = 32,
- .h_back = 80,
++ .h_total = 1840,
++ .h_blank = 160,
++ .h_front = 48,
++ .h_sync = 32,
++ .h_back = 80,
+ .v_active = 1050,
+ .v_total = 1080,
+ .v_blank = 30,
+ .v_front = 3,
+ .v_sync = 6,
+ .v_back = 21,
+ .v_sync_ln = 1,
+ },
+ .hdmitx_vinfo = {
+ .name = "1680x1050p60hz",
+ .mode = VMODE_HDMI,
+ .width = 1680,
+ .height = 1050,
+ .field_height = 1050,
+ .aspect_ratio_num = 8,
+ .aspect_ratio_den = 5,
+ .sync_duration_num = 60,
+ .sync_duration_den = 1,
- .video_clk = 119000000,
- .htotal = 1840,
- .vtotal = 1080,
++ .video_clk = 119000000,
++ .htotal = 1840,
++ .vtotal = 1080,
+ .fr_adj_type = VOUT_FR_ADJ_HDMI,
+ .viu_color_fmt = COLOR_FMT_YUV444,
+ .viu_mux = VIU_MUX_ENCP,
+ },
+};
++#endif
static struct hdmi_format_para fmt_para_vesa_1920x1200p60_8x5 = {
.vic = HDMIV_1920x1200p60hz,
.name = "1920x1200p60hz",
- .sname = "1920x1200p60hz",
++ .sname = "1920x1200p60hz",
.pixel_repetition_factor = 0,
.progress_mode = 1,
.scrambler_en = 0,
static struct hdmi_format_para fmt_para_vesa_2560x1600p60_8x5 = {
.vic = HDMIV_2560x1600p60hz,
.name = "2560x1600p60hz",
- .sname = "2560x1600p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 268000,
+ .timing = {
+ .pixel_freq = 268000,
+ .h_freq = 98529,
+ .v_freq = 59859,
+ .vsync = 60,
+ .vsync_polarity = 1,
+ .hsync_polarity = 0,
+ .h_active = 2560,
+ .h_total = 2720,
+ .h_blank = 160,
+ .h_front = 48,
+ .h_sync = 32,
+ .h_back = 80,
+ .v_active = 1600,
+ .v_total = 1646,
+ .v_blank = 46,
+ .v_front = 2,
+ .v_sync = 6,
+ .v_back = 38,
+ .v_sync_ln = 1,
+ },
+ .hdmitx_vinfo = {
+ .name = "2560x1600p60hz",
+ .mode = VMODE_HDMI,
+ .width = 2560,
+ .height = 1600,
+ .field_height = 1600,
+ .aspect_ratio_num = 8,
+ .aspect_ratio_den = 5,
+ .sync_duration_num = 60,
+ .sync_duration_den = 1,
+ .video_clk = 268000000,
+ .htotal = 2720,
+ .vtotal = 1646,
+ .fr_adj_type = VOUT_FR_ADJ_HDMI,
+ .viu_color_fmt = COLOR_FMT_YUV444,
+ .viu_mux = VIU_MUX_ENCP,
+ },
+ };
+ #else
+ static struct hdmi_format_para fmt_para_vesa_2560x1600p60_8x5 = {
+ .vic = HDMIV_2560x1600p60hz,
+ .name = "2560x1600p60hz",
++ .sname = "2560x1600p60hz",
.pixel_repetition_factor = 0,
.progress_mode = 1,
.scrambler_en = 0,
&fmt_para_3840x2160p50_16x9_y420,
&fmt_para_4096x2160p50_256x135_y420,
&fmt_para_2560x1080p50_64x27,
- &fmt_para_vesa_2560x1080p60_64x27,
- &fmt_para_vesa_2560x1440p60_16x9,
- &fmt_para_vesa_480x320p60_4x3,
- &fmt_para_2560x1080p60_64x27,
++ &fmt_para_vesa_2560x1080p60_64x27,
++ &fmt_para_vesa_2560x1440p60_16x9,
++#if !defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
++ &fmt_para_vesa_480x320p60_4x3,
++#endif
&fmt_para_vesa_640x480p60_4x3,
&fmt_para_vesa_800x480p60_4x3,
- &fmt_para_vesa_1280x480p60_8x3,
++ &fmt_para_vesa_1280x480p60_8x3,
&fmt_para_vesa_800x600p60_4x3,
&fmt_para_vesa_852x480p60_213x120,
&fmt_para_vesa_854x480p60_427x240,
&fmt_para_vesa_1920x1200p60_8x5,
&fmt_para_vesa_2160x1200p90_9x5,
&fmt_para_vesa_2560x1600p60_8x5,
- &fmt_para_vesa_2560x1440p60_16x9,
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ &fmt_para_vesa_3440x1440p60_43x18,
+ &fmt_para_480x320p60_4x3,
+ &fmt_para_480x272p60_4x3,
+ &fmt_para_480x800p60_4x3,
+ &fmt_para_custombuilt,
+ #endif
&fmt_para_null_hdmi_fmt,
&fmt_para_non_hdmi_fmt,
NULL,
struct hdmi_format_para *para = NULL;
unsigned char mode[32];
enum hdmi_vic vic = HDMI_Unknown;
+// char* pix_fmt[] = {"RGB","YUV422","YUV444","YUV420"};
+// char* eotf[] = {"SDR","HDR","HDR10","HLG"};
+// char* range[] = {"default","limited","full"};
+
/* vic_ready got from IP */
- enum hdmi_vic vic_ready = hdev->HWOp.GetState(
+ enum hdmi_vic vic_ready = hdev->hwop.getstate(
hdev, STAT_VIDEO_VIC, 0);
memset(mode, 0, sizeof(mode));
else {
/* nothing */
}
- if ((vic_ready != HDMI_Unknown) && (vic_ready == vic)) {
+ if ((vic_ready != HDMI_Unknown) && (vic_ready == vic) && (strstr(hdmitx_device.fmt_attr,"now") == NULL)) {
pr_info(SYS "[%s] ALREADY init VIC = %d\n",
__func__, vic);
- if (hdev->RXCap.ieeeoui == 0) {
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ if (odroid_voutmode() == VOUTMODE_HDMI) {
+ hdev->hwop.cntlconfig(hdev, CONF_HDMI_DVI_MODE,
+ HDMI_MODE);
+ pr_info(SYS "change to HDMI mode\n");
+ } else if (odroid_voutmode() == VOUTMODE_DVI) {
+ hdev->hwop.cntlconfig(hdev, CONF_HDMI_DVI_MODE,
+ DVI_MODE);
+ pr_info(SYS "change to DVI mode\n");
+ } else if (hdev->rxcap.ieeeoui == 0) {
+ #else
+ if (hdev->rxcap.ieeeoui == 0) {
+ #endif
/* DVI case judgement. In uboot, directly output HDMI
* mode
*/
hdmitx_pre_display_init();
- if (strstr(hdmitx_device.fmt_attr,"now") != NULL){
+
++ if (strstr(hdmitx_device.fmt_attr,"now") != NULL) {
+ memcpy(strstr(hdmitx_device.fmt_attr,"now"), " ", 3);
+ }
hdev->cur_VIC = HDMI_Unknown;
/* if vic is HDMI_Unknown, hdmitx_set_display will disable HDMI */
ret = hdmitx_set_display(hdev, vic);
"cur_video_param->VIC=%d\n",
hdev->cur_video_param->VIC);
if (hdev->para) {
- pos += snprintf(buf+pos, PAGE_SIZE, "cd = %d\n",
- hdev->para->cd);
- pos += snprintf(buf+pos, PAGE_SIZE, "cs = %d\n",
- hdev->para->cs);
+ struct hdmi_format_para *para;
+ para = hdev->para;
+
+ pos += snprintf(buf+pos, PAGE_SIZE, "VIC: %d %s\n",
+ hdmitx_device.cur_VIC, para->name);
+ pos += snprintf(buf + pos, PAGE_SIZE, "Colour depth: %d-bit\nColourspace: %s\nColour range: %s\nEOTF: %s\nYCC colour range: %s\n",
+ (((hdmitx_rd_reg(HDMITX_DWC_TX_INVID0) & 0x6) >> 1) + 4 ) * 2,
+ pix_fmt[(hdmitx_rd_reg(HDMITX_DWC_FC_AVICONF0) & 0x3)],
+ range[(hdmitx_rd_reg(HDMITX_DWC_FC_AVICONF2) & 0xc) >> 2],
+ eotf[(hdmitx_rd_reg(HDMITX_DWC_FC_DRM_PB00) & 7)],
+ range[((hdmitx_rd_reg(HDMITX_DWC_FC_AVICONF3) & 0xc) >> 2) + 1]);
- if (((hdmitx_rd_reg(HDMITX_DWC_FC_AVICONF1) & 0xc0) >> 6) < 0x3)
++ if (((hdmitx_rd_reg(HDMITX_DWC_FC_AVICONF1) & 0xc0) >> 6) < 0x3)
+ pos += snprintf(buf + pos, PAGE_SIZE, "Colourimetry: %s\n",
+ colourimetry[(hdmitx_rd_reg(HDMITX_DWC_FC_AVICONF1) & 0xc0) >> 6]);
- else
++ else
+ pos += snprintf(buf + pos, PAGE_SIZE, "Colourimetry: %s\n",
+ colourimetry[((hdmitx_rd_reg(HDMITX_DWC_FC_AVICONF2) & 0x70) >> 4) + 3]);
+ pos += snprintf(buf + pos, PAGE_SIZE, "PLL clock: 0x%08x, Vid clock div 0x%08x\n",
+ hd_read_reg(P_HHI_HDMI_PLL_CNTL),
+ hd_read_reg(P_HHI_VID_PLL_CLK_DIV));
}
switch (hdev->tx_aud_cfg) {
vic = hdmitx_edid_get_VIC(&hdmitx_device, mode_tmp, 0);
/* Handling only 4k420 mode */
if (vic == HDMI_Unknown) {
-- if (is_4k50_fmt(mode_tmp)) {
-- strcat(mode_tmp, "420");
-- vic = hdmitx_edid_get_VIC(&hdmitx_device,
-- mode_tmp, 0);
++ if (is_4k50_fmt(mode_tmp)) {
++ strcat(mode_tmp, "420");
++ vic = hdmitx_edid_get_VIC(&hdmitx_device,
++ mode_tmp, 0);
++ }
}
-- }
-- if (vic != HDMI_Unknown) {
-- pos += snprintf(buf+pos, PAGE_SIZE, "%s",
++ if (vic != HDMI_Unknown) {
++ pos += snprintf(buf+pos, PAGE_SIZE, "%s",
disp_mode_t[i]);
-- if (native_disp_mode && (strcmp(
-- native_disp_mode,
-- disp_mode_t[i]) == 0)) {
-- pos += snprintf(buf+pos, PAGE_SIZE,
-- "*\n");
-- } else
-- pos += snprintf(buf+pos, PAGE_SIZE, "\n");
-- }
++ if (native_disp_mode && (strcmp(
++ native_disp_mode,
++ disp_mode_t[i]) == 0)) {
++ pos += snprintf(buf+pos, PAGE_SIZE,
++ "*\n");
++ } else
++ pos += snprintf(buf+pos, PAGE_SIZE, "\n");
++ }
}
- pos += snprintf(buf + pos, PAGE_SIZE, "1024x768p60hz\n");
++ pos += snprintf(buf + pos, PAGE_SIZE, "1024x768p60hz\n");
}
return pos;
}
if ((vinfo != NULL) && (vinfo->name != NULL))
recalc_vinfo_sync_duration(vinfo,
hdmitx_device.frac_rate_policy);
-
-#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
if (!(mode & VMODE_INIT_BIT_MASK) && get_hpd_state())
-#else
- if (!(mode & VMODE_INIT_BIT_MASK))
-#endif
set_disp_mode_auto();
else
pr_info("alread display in uboot\n");
info = hdmitx_get_current_vinfo();
if (info && (info->mode == VMODE_HDMI))
hdmitx_set_audio(hdev, &(hdev->cur_audio_param));
-#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ set_disp_mode_auto();
-#endif
hdev->hpd_state = 1;
hdmitx_notify_hpd(hdev->hpd_state);
{MREG_END_MARKER, 0},
};
- {P_ENCP_VIDEO_EN, 0,},
- {P_ENCI_VIDEO_EN, 0,},
+static const struct reg_s tvregs_vesa_1280x480p_60hz[] = {
- {P_ENCP_VIDEO_MODE, 0x4040,},
- {P_ENCP_VIDEO_MODE_ADV, 0x18,},
++ {P_ENCP_VIDEO_EN, 0,},
++ {P_ENCI_VIDEO_EN, 0,},
+
- {P_ENCP_VIDEO_MAX_PXCNT, 0x59F,},
- {P_ENCP_VIDEO_MAX_LNCNT, 0x1F3,},
- {P_ENCP_VIDEO_HAVON_BEGIN, 0x70,},
- {P_ENCP_VIDEO_HAVON_END, 0x56F,},
- {P_ENCP_VIDEO_VAVON_BLINE, 0x11,},
- {P_ENCP_VIDEO_VAVON_ELINE, 0x1F0,},
- {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
- {P_ENCP_VIDEO_HSO_END, 0x20,},
- {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
- {P_ENCP_VIDEO_VSO_END, 0x32,},
- {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
- {P_ENCP_VIDEO_VSO_ELINE, 0x7,},
++ {P_ENCP_VIDEO_MODE, 0x4040,},
++ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+
- {P_ENCP_VIDEO_EN, 1,},
- {P_ENCI_VIDEO_EN, 0,},
- {MREG_END_MARKER, 0}
++ {P_ENCP_VIDEO_MAX_PXCNT, 0x59F,},
++ {P_ENCP_VIDEO_MAX_LNCNT, 0x1F3,},
++ {P_ENCP_VIDEO_HAVON_BEGIN, 0x70,},
++ {P_ENCP_VIDEO_HAVON_END, 0x56F,},
++ {P_ENCP_VIDEO_VAVON_BLINE, 0x11,},
++ {P_ENCP_VIDEO_VAVON_ELINE, 0x1F0,},
++ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
++ {P_ENCP_VIDEO_HSO_END, 0x20,},
++ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
++ {P_ENCP_VIDEO_VSO_END, 0x32,},
++ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
++ {P_ENCP_VIDEO_VSO_ELINE, 0x7,},
+
-
++ {P_ENCP_VIDEO_EN, 1,},
++ {P_ENCI_VIDEO_EN, 0,},
++ {MREG_END_MARKER, 0}
+};
+
static const struct reg_s tvregs_vesa_852x480p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{MREG_END_MARKER, 0}
};
- {P_ENCP_VIDEO_MAX_PXCNT, 0x72F,},
- {P_ENCP_VIDEO_MAX_LNCNT, 0x437,},
- {P_ENCP_VIDEO_HAVON_BEGIN, 0x70,},
- {P_ENCP_VIDEO_HAVON_END, 0x6FF,},
- {P_ENCP_VIDEO_VAVON_BLINE, 0x1B,},
- {P_ENCP_VIDEO_VAVON_ELINE, 0x434,},
++#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ static const struct reg_s tvregs_vesa_1680x1050p60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x8BF,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x440,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x1C8,},
+ {P_ENCP_VIDEO_HAVON_END, 0x857,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x24,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x43D,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0xB0,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x6,},
+
+ {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+ };
++#else
+static const struct reg_s tvregs_vesa_1680x1050p60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x8BF,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x440,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x1C8,},
+ {P_ENCP_VIDEO_HAVON_END, 0x857,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x24,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x43D,},
- {P_ENCP_VIDEO_HSO_END, 0x20,},
++ {P_ENCP_VIDEO_MAX_PXCNT, 0x72F,},
++ {P_ENCP_VIDEO_MAX_LNCNT, 0x437,},
++ {P_ENCP_VIDEO_HAVON_BEGIN, 0x70,},
++ {P_ENCP_VIDEO_HAVON_END, 0x6FF,},
++ {P_ENCP_VIDEO_VAVON_BLINE, 0x1B,},
++ {P_ENCP_VIDEO_VAVON_ELINE, 0x434,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
++ {P_ENCP_VIDEO_HSO_END, 0x20,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x6,},
+
+ {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+};
++#endif
static const struct reg_s tvregs_vesa_1920x1200p60hz[] = {
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0},
{MREG_END_MARKER, 0}
};
+ #endif
-#if 0 /* TODO */
+#if 1 /* TODO */
static const struct reg_s tvregs_vesa_2560x1080p60hz[] = {
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
- {P_ENCP_VIDEO_MAX_PXCNT, 0xBB7,},
- {P_ENCP_VIDEO_MAX_LNCNT, 0x44B,},
- {P_ENCP_VIDEO_HAVON_BEGIN, 0xC0,},
- {P_ENCP_VIDEO_HAVON_END, 0xABF,},
- {P_ENCP_VIDEO_VAVON_BLINE, 0x10,},
- {P_ENCP_VIDEO_VAVON_ELINE, 0x447,},
- {P_ENCP_VIDEO_MAX_PXCNT, 0xA1F,},
- {P_ENCP_VIDEO_MAX_LNCNT, 0x4DC,},
- {P_ENCP_VIDEO_HAVON_BEGIN, 0x218,},
- {P_ENCP_VIDEO_HAVON_END, 0x997,},
- {P_ENCP_VIDEO_VAVON_BLINE, 0x2A,},
- {P_ENCP_VIDEO_VAVON_ELINE, 0x4D9,},
++ {P_ENCP_VIDEO_MAX_PXCNT, 0xBB7,},
++ {P_ENCP_VIDEO_MAX_LNCNT, 0x44B,},
++ {P_ENCP_VIDEO_HAVON_BEGIN, 0xC0,},
++ {P_ENCP_VIDEO_HAVON_END, 0xABF,},
++ {P_ENCP_VIDEO_VAVON_BLINE, 0x10,},
++ {P_ENCP_VIDEO_VAVON_ELINE, 0x447,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
- {P_ENCP_VIDEO_HSO_END, 0x2C,},
- {P_ENCP_VIDEO_HSO_END, 0xC8,},
++ {P_ENCP_VIDEO_HSO_END, 0x2C,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
- {P_ENCP_VIDEO_VSO_ELINE, 0x5,},
- {P_ENCP_VIDEO_VSO_ELINE, 0x6,},
++ {P_ENCP_VIDEO_VSO_ELINE, 0x5,},
+
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{MREG_END_MARKER, 0}
};
++#if !defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
++static const struct reg_s tvregs_vesa_480x320p_60hz[] = {
++ {P_VENC_VDAC_SETTING, 0xff,},
++ {P_ENCP_VIDEO_EN, 0,},
++ {P_ENCI_VIDEO_EN, 0,},
++
++ {P_ENCP_VIDEO_MODE, 0x4040,},
++ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
++
++ {P_ENCP_VIDEO_MAX_PXCNT, 0x31F,},
++ {P_ENCP_VIDEO_MAX_LNCNT, 0x20C,},
++ {P_ENCP_VIDEO_HAVON_BEGIN, 0x64,},
++ {P_ENCP_VIDEO_HAVON_END, 0x243,},
++ {P_ENCP_VIDEO_VAVON_BLINE, 0xBD,},
++ {P_ENCP_VIDEO_VAVON_ELINE, 0x1FC,},
++ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
++ {P_ENCP_VIDEO_HSO_END, 0x64,},
++ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
++ {P_ENCP_VIDEO_VSO_END, 0x32,},
++ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
++ {P_ENCP_VIDEO_VSO_ELINE, 0x8,},
++
++ {P_ENCP_VIDEO_EN, 1,},
++ {P_ENCI_VIDEO_EN, 0,},
++ {MREG_END_MARKER, 0}
++};
++
static const struct reg_s tvregs_vesa_2560x1440p60hz[] = {
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
- {P_ENCP_VIDEO_MAX_PXCNT, 0xA9F,},
- {P_ENCP_VIDEO_MAX_LNCNT, 0x5C8,},
- {P_ENCP_VIDEO_HAVON_BEGIN, 0x70,},
- {P_ENCP_VIDEO_HAVON_END, 0xA6F,},
- {P_ENCP_VIDEO_VAVON_BLINE, 0x27,},
- {P_ENCP_VIDEO_VAVON_ELINE, 0x5C6,},
- {P_ENCP_VIDEO_MAX_PXCNT, 0xA1F,},
- {P_ENCP_VIDEO_MAX_LNCNT, 0x4DC,},
- {P_ENCP_VIDEO_HAVON_BEGIN, 0x218,},
- {P_ENCP_VIDEO_HAVON_END, 0x997,},
- {P_ENCP_VIDEO_VAVON_BLINE, 0x2A,},
- {P_ENCP_VIDEO_VAVON_ELINE, 0x4D9,},
++ {P_ENCP_VIDEO_MAX_PXCNT, 0xA9F,},
++ {P_ENCP_VIDEO_MAX_LNCNT, 0x5C8,},
++ {P_ENCP_VIDEO_HAVON_BEGIN, 0x70,},
++ {P_ENCP_VIDEO_HAVON_END, 0xA6F,},
++ {P_ENCP_VIDEO_VAVON_BLINE, 0x27,},
++ {P_ENCP_VIDEO_VAVON_ELINE, 0x5C6,},
{P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
- {P_ENCP_VIDEO_HSO_END, 0x20,},
- {P_ENCP_VIDEO_HSO_END, 0xC8,},
++ {P_ENCP_VIDEO_HSO_END, 0x20,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
- {P_ENCP_VIDEO_VSO_ELINE, 0x5,},
- {P_ENCP_VIDEO_VSO_ELINE, 0x6,},
++ {P_ENCP_VIDEO_VSO_ELINE, 0x5,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCI_VIDEO_EN, 0},
{MREG_END_MARKER, 0}
};
++#endif /* !defined(CONFIG_ARCH_MESON64_ODROID_COMMON) */
+ #endif
+
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ static const struct reg_s tvregs_vesa_2560x1440p60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+
+ {P_ENCP_VIDEO_MAX_PXCNT, 0xA9F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x5C8,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x50,},
+ {P_ENCP_VIDEO_HAVON_END, 0xA4F,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x22,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x5C1,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0,},
+ {P_ENCP_VIDEO_HSO_END, 0x20,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x5,},
+
+ {P_ENCP_VIDEO_EN, 1,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0},
+ };
+
+ static const struct reg_s tvregs_480x320p_60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x31F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x20C,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x64,},
+ {P_ENCP_VIDEO_HAVON_END, 0x243,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0xBD,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x1FC,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x64,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x8,},
+
+ {P_ENCP_VIDEO_EN, 1,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+ };
+
+ static const struct reg_s tvregs_480x272p_60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x31F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x20C,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x64,},
+ {P_ENCP_VIDEO_HAVON_END, 0x243,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0xEE,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x1FD,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x64,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x7,},
+
+ {P_ENCP_VIDEO_EN, 1,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+ };
+
+ static const struct reg_s tvregs_480x800p_60hz[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+
+ {P_ENCP_VIDEO_MODE, 0x4040},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18},
+
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x25F},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x34C},
+
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x28},
+ {P_ENCP_VIDEO_HAVON_END, 0x207},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x1D},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x33C},
+
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0},
+ {P_ENCP_VIDEO_HSO_END, 0x30},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E},
+ {P_ENCP_VIDEO_VSO_END, 0x32},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x3},
+
+ {P_ENCP_VIDEO_EN, 1},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+ };
+
+ static const struct reg_s tvregs_vesa_3440x1440p60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+
+ {P_ENCP_VIDEO_MAX_PXCNT, 3599,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 1480,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 80,},
+ {P_ENCP_VIDEO_HAVON_END, 3519,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 28,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 1467,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0,},
+ {P_ENCP_VIDEO_HSO_END, 32,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 10,},
+
+ {P_ENCP_VIDEO_EN, 1,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0},
+ };
#endif
struct vic_tvregs_set {
{HDMI_2560x1080p60_64x27, tvregs_2560x1080p60hz},
{HDMIV_640x480p60hz, tvregs_vesa_640x480p60hz},
{HDMIV_800x480p60hz, tvregs_vesa_800x480p60hz},
- {HDMIV_1280x480p60hz, tvregs_vesa_1280x480p_60hz},
++ {HDMIV_1280x480p60hz, tvregs_vesa_1280x480p_60hz},
{HDMIV_800x600p60hz, tvregs_vesa_800x600p60hz},
{HDMIV_852x480p60hz, tvregs_vesa_852x480p60hz},
{HDMIV_854x480p60hz, tvregs_vesa_854x480p60hz},
{HDMIV_1920x1200p60hz, tvregs_vesa_1920x1200p60hz},
{HDMIV_2160x1200p90hz, tvregs_vesa_2160x1200p90hz},
{HDMIV_2560x1600p60hz, tvregs_vesa_2560x1600p60hz},
- {HDMIV_2560x1440p60hz, tvregs_vesa_2560x1440p60hz},
- {HDMIV_2560x1080p60hz, tvregs_vesa_2560x1080p60hz},
- {HDMIV_480x320p60hz, tvregs_vesa_480x320p_60hz},
++ {HDMIV_2560x1080p60hz, tvregs_vesa_2560x1080p60hz},
++ {HDMIV_2560x1440p60hz, tvregs_vesa_2560x1440p60hz},
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ {HDMIV_3440x1440p60hz, tvregs_vesa_3440x1440p60hz},
- {HDMIV_2560x1440p60hz, tvregs_vesa_2560x1440p60hz},
+ {HDMI_480x320p60_4x3, tvregs_480x320p_60hz},
+ {HDMI_480x272p60_4x3, tvregs_480x272p_60hz},
+ {HDMI_480x800p60_4x3, tvregs_480x800p_60hz},
++#else
++ {HDMIV_480x320p60hz, tvregs_vesa_480x320p_60hz},
+ #endif
};
/*
SOF_LINES = hdmi_encp_timing->v_back;
TOTAL_FRAMES = 4;
break;
- case HDMIV_1024x768p60hz:
- printk("jason hdmi_tvenc_set \n");
- INTERLACE_MODE = 0;
- PIXEL_REPEAT_VENC = 0;
- PIXEL_REPEAT_HDMI = 0;
- ACTIVE_PIXELS = (1024*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (768/(1+INTERLACE_MODE));
- LINES_F0 = 806;
- LINES_F1 = 806;
- FRONT_PORCH = 24;
- HSYNC_PIXELS = 136;
- BACK_PORCH = 160;
- EOF_LINES = 3;
- VSYNC_LINES = 6;
- SOF_LINES = 29;
- TOTAL_FRAMES = 4;
- break;
++ case HDMIV_1024x768p60hz:
++ INTERLACE_MODE = 0;
++ PIXEL_REPEAT_VENC = 0;
++ PIXEL_REPEAT_HDMI = 0;
++ ACTIVE_PIXELS = (1024*(1+PIXEL_REPEAT_HDMI));
++ ACTIVE_LINES = (768/(1+INTERLACE_MODE));
++ LINES_F0 = 806;
++ LINES_F1 = 806;
++ FRONT_PORCH = 24;
++ HSYNC_PIXELS = 136;
++ BACK_PORCH = 160;
++ EOF_LINES = 3;
++ VSYNC_LINES = 6;
++ SOF_LINES = 29;
++ TOTAL_FRAMES = 4;
++ break;
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ case HDMIV_3440x1440p60hz:
+ INTERLACE_MODE = 0U;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (3440*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (1440/(1+INTERLACE_MODE));
+ LINES_F0 = 1481;
+ LINES_F1= 1481;
+ FRONT_PORCH = 48;
+ HSYNC_PIXELS = 32;
+ BACK_PORCH = 80;
+ EOF_LINES = 3;
+ VSYNC_LINES = 10;
+ SOF_LINES = 28;
+ TOTAL_FRAMES = 4;
+ break;
+ case HDMIV_2560x1600p60hz:
+ INTERLACE_MODE = 0U;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (2560*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (1600/(1+INTERLACE_MODE));
+ LINES_F0 = 1646;
+ LINES_F1 = 1646;
+ FRONT_PORCH = 48;
+ HSYNC_PIXELS = 32;
+ BACK_PORCH = 80;
+ EOF_LINES = 2;
+ VSYNC_LINES = 3;
+ SOF_LINES = 19;
+ TOTAL_FRAMES = 4;
+ break;
+ case HDMIV_2560x1440p60hz:
+ INTERLACE_MODE = 0U;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (2560*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (1440/(1+INTERLACE_MODE));
+ LINES_F0 = 1481;
+ LINES_F1 = 1481;
+ FRONT_PORCH = 48;
+ HSYNC_PIXELS = 32;
+ BACK_PORCH = 80;
+ EOF_LINES = 2;
+ VSYNC_LINES = 5;
+ SOF_LINES = 34;
+ TOTAL_FRAMES = 4;
+ break;
+ case HDMI_2560x1080p60_64x27:
+ INTERLACE_MODE = 0U;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (2560*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (1080/(1+INTERLACE_MODE));
+ LINES_F0 = 1100;
+ LINES_F1 = 1100;
+ FRONT_PORCH = 248;
+ HSYNC_PIXELS = 44;
+ BACK_PORCH = 148;
+ EOF_LINES = 4;
+ VSYNC_LINES = 5;
+ SOF_LINES = 11;
+ TOTAL_FRAMES = 4;
+ break;
+ case HDMIV_1920x1200p60hz:
+ INTERLACE_MODE = 0U;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (1200/(1+INTERLACE_MODE));
+ LINES_F0 = 1245;
+ LINES_F1 = 1245;
+ FRONT_PORCH = 136;
+ HSYNC_PIXELS = 200;
+ BACK_PORCH = 336;
+ EOF_LINES = 3;
+ VSYNC_LINES = 6;
+ SOF_LINES = 36;
+ TOTAL_FRAMES = 4;
+ break;
+ case HDMIV_1600x1200p60hz:
+ INTERLACE_MODE = 0U;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (1600*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (1200/(1+INTERLACE_MODE));
+ LINES_F0 = 1250;
+ LINES_F1 = 1250;
+ FRONT_PORCH = 64;
+ HSYNC_PIXELS = 192;
+ BACK_PORCH = 304;
+ EOF_LINES = 1;
+ VSYNC_LINES = 3;
+ SOF_LINES = 46;
+ TOTAL_FRAMES = 4;
+ break;
+ case HDMIV_1600x900p60hz:
+ INTERLACE_MODE = 0U;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (1600*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (900/(1+INTERLACE_MODE));
+ LINES_F0 = 1800;
+ LINES_F1 = 1800;
+ FRONT_PORCH = 24;
+ HSYNC_PIXELS = 80;
+ BACK_PORCH = 96;
+ EOF_LINES = 1;
+ VSYNC_LINES = 3;
+ SOF_LINES = 96;
+ TOTAL_FRAMES = 4;
+ break;
+ case HDMIV_1440x900p60hz:
+ INTERLACE_MODE = 0U;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (1440*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (900/(1+INTERLACE_MODE));
+ LINES_F0 = 934;
+ LINES_F1 = 934;
+ FRONT_PORCH = 80;
+ HSYNC_PIXELS = 152;
+ BACK_PORCH = 232;
+ EOF_LINES = 3;
+ VSYNC_LINES = 6;
+ SOF_LINES = 25;
+ TOTAL_FRAMES = 4;
+ break;
+ case HDMIV_1280x1024p60hz:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (1024/(1+INTERLACE_MODE));
+ LINES_F0 = 1066;
+ LINES_F1 = 1066;
+ FRONT_PORCH = 48;
+ HSYNC_PIXELS = 112;
+ BACK_PORCH = 248;
+ EOF_LINES = 1;
+ VSYNC_LINES = 3;
+ SOF_LINES = 38;
+ break;
+ case HDMIV_1280x800p60hz:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (800/(1+INTERLACE_MODE));
+ LINES_F0 = 823;
+ LINES_F1 = 823;
+ FRONT_PORCH = 48;
+ HSYNC_PIXELS = 32;
+ BACK_PORCH = 80;
+ EOF_LINES = 3;
+ VSYNC_LINES = 6;
+ SOF_LINES = 14;
+ break;
- case HDMIV_1024x768p60hz:
- INTERLACE_MODE = 0;
- PIXEL_REPEAT_VENC = 0;
- PIXEL_REPEAT_HDMI = 0;
- ACTIVE_PIXELS = (1024*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (768/(1+INTERLACE_MODE));
- LINES_F0 = 806;
- LINES_F1 = 806;
- FRONT_PORCH = 24;
- HSYNC_PIXELS = 136;
- BACK_PORCH = 160;
- EOF_LINES = 3;
- VSYNC_LINES = 6;
- SOF_LINES = 29;
- TOTAL_FRAMES = 4;
- break;
+ case HDMIV_1024x600p60hz:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (1024*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (600/(1+INTERLACE_MODE));
+ LINES_F0 = 638;
+ LINES_F1 = 638;
+ FRONT_PORCH = 24;
+ HSYNC_PIXELS = 136;
+ BACK_PORCH = 160;
+ EOF_LINES = 3;
+ VSYNC_LINES = 6;
+ SOF_LINES = 29;
+ TOTAL_FRAMES = 4;
+ break;
+ case HDMIV_800x600p60hz:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (800*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (600/(1+INTERLACE_MODE));
+ LINES_F0 = 628;
+ LINES_F1 = 628;
+ FRONT_PORCH = 40;
+ HSYNC_PIXELS = 128;
+ BACK_PORCH = 88;
+ EOF_LINES = 1;
+ VSYNC_LINES = 4;
+ SOF_LINES = 23;
+ TOTAL_FRAMES = 4;
+ break;
+ case HDMIV_800x480p60hz:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (800*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (480/(1+INTERLACE_MODE));
+ LINES_F0 = 500;
+ LINES_F1 = 500;
+ FRONT_PORCH = 24;
+ HSYNC_PIXELS = 72;
+ BACK_PORCH = 96;
+ EOF_LINES = 3;
+ VSYNC_LINES = 7;
+ SOF_LINES = 10;
+ TOTAL_FRAMES = 4;
+ break;
+ case HDMIV_640x480p60hz:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (640*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (480/(1+INTERLACE_MODE));
+ LINES_F0 = 525;
+ LINES_F1 = 525;
+ FRONT_PORCH = 16;
+ HSYNC_PIXELS = 96;
+ BACK_PORCH = 48;
+ EOF_LINES = 10;
+ VSYNC_LINES = 2;
+ SOF_LINES = 33;
+ TOTAL_FRAMES = 4;
+ break;
+ case HDMI_480x320p60_4x3:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (480*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (320/(1+INTERLACE_MODE));
+ LINES_F0 = 263;
+ LINES_F1 = 263;
+ FRONT_PORCH = 120;
+ HSYNC_PIXELS = 100;
+ BACK_PORCH = 100;
+ EOF_LINES = 8;
+ VSYNC_LINES = 4;
+ SOF_LINES = 95;
+ TOTAL_FRAMES = 4;
+ break;
+ case HDMI_480x272p60_4x3:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (480*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (272/(1+INTERLACE_MODE));
+ LINES_F0 = 263;
+ LINES_F1 = 263;
+ FRONT_PORCH = 120;
+ HSYNC_PIXELS = 100;
+ BACK_PORCH = 100;
+ EOF_LINES = 8;
+ VSYNC_LINES = 4;
+ SOF_LINES = 119;
+ TOTAL_FRAMES = 4;
+ break;
+ case HDMI_480x800p60_4x3:
+ INTERLACE_MODE = 0U;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (480*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (800*(1+PIXEL_REPEAT_HDMI));
+ LINES_F0 = 845;
+ LINES_F1 = 845;
+ FRONT_PORCH = 40;
+ HSYNC_PIXELS = 48;
+ BACK_PORCH = 40;
+ EOF_LINES = 13;
+ VSYNC_LINES = 3;
+ SOF_LINES = 29;
+ break;
+ case HDMI_CUSTOMBUILT:
+ custom_timing = get_custom_timing();
+ INTERLACE_MODE = 0U;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = custom_timing->h_active;
+ ACTIVE_LINES = custom_timing->v_active;
+ LINES_F0 = custom_timing->v_total;
+ LINES_F1 = custom_timing->v_total;
+ FRONT_PORCH = custom_timing->h_front;
+ HSYNC_PIXELS = custom_timing->h_sync;
+ BACK_PORCH = custom_timing->h_back;
+ EOF_LINES = custom_timing->v_front;
+ VSYNC_LINES = custom_timing->v_sync;
+ SOF_LINES = custom_timing->v_back;
+ TOTAL_FRAMES = 4;
+ break;
+ #endif
default:
break;
}
HDMI_3840x2160p50_16x9_Y420,
HDMI_VIC_END},
5940000, 2, 1, 1, VID_PLL_DIV_5, 1, 2, 1, -1},
- {{HDMIV_2560x1440p60hz,
- HDMI_VIC_END},
- 4830000, 2, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ {{HDMIV_3440x1440p60hz,
+ HDMI_VIC_END},
+ 3197500, 1, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ {{HDMI_480x320p60_4x3,
+ HDMI_480x272p60_4x3,
+ HDMI_VIC_END},
+ /* actual hpll : 2016000 */
+ 2000000, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ {{HDMI_480x800p60_4x3,
+ HDMI_VIC_END},
+ 2560000, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ {{HDMI_CUSTOMBUILT,
+ HDMI_VIC_END},
+ /* default 1080p60hz */
+ 5940000, 4, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ #endif
{{HDMI_VIC_FAKE,
HDMI_VIC_END},
3450000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
/* pll setting for VESA modes */
{{HDMIV_640x480p60hz, /* 4.028G / 16 = 251.75M */
HDMI_VIC_END},
- 4028000, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ 2000000, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ #else
+ 251750, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #endif
{{HDMIV_800x480p60hz,
HDMI_VIC_END},
- 4761600, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ 2415000, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ #else
- {{HDMIV_1280x480p60hz,
- HDMI_VIC_END},
- 432000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ 297600, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #endif
++ {{HDMIV_1280x480p60hz,
++ HDMI_VIC_END},
++ 432000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_800x600p60hz,
HDMI_VIC_END},
- 3200000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ 3243240, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ #else
+ 400000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #endif
{{HDMIV_852x480p60hz,
HDMIV_854x480p60hz,
HDMI_VIC_END},
4838400, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_1024x600p60hz,
HDMI_VIC_END},
- 504000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ 2058000, 4, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ #else
- 4115866, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
++ 504000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #endif
{{HDMIV_1024x768p60hz,
HDMI_VIC_END},
- 5200000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ 2600000, 2, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #else
+ 650000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #endif
{{HDMIV_1280x768p60hz,
HDMI_VIC_END},
3180000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_1280x800p60hz,
HDMI_VIC_END},
- 5680000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ 1422000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #else
+ 835000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #endif
{{HDMIV_1152x864p75hz,
HDMIV_1280x960p60hz,
HDMIV_1280x1024p60hz,
HDMIV_1600x900p60hz,
HDMI_VIC_END},
- 4320000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ 4324320, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #else
+ 1080000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #endif
{{HDMIV_1600x1200p60hz,
HDMI_VIC_END},
- 3240000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ 3243240, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #else
+ 1620000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #endif
{{HDMIV_1360x768p60hz,
HDMIV_1366x768p60hz,
HDMI_VIC_END},
++#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ 3420000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
++#else
+ 855000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
++#endif
{{HDMIV_1400x1050p60hz,
HDMI_VIC_END},
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ 2134000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #else
4870000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #endif
{{HDMIV_1440x900p60hz,
HDMI_VIC_END},
- 4260000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ 2134000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #else
+ 1065000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #endif
{{HDMIV_1440x2560p60hz,
HDMI_VIC_END},
4897000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_1680x1050p60hz,
HDMI_VIC_END},
++#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ 5850000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
++#else
+ 1190000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
++#endif
{{HDMIV_1920x1200p60hz,
HDMI_VIC_END},
++#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ 3865000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
++#else
+ 1932500, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
++#endif
{{HDMIV_2160x1200p90hz,
HDMI_VIC_END},
5371100, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
{{HDMIV_2560x1600p60hz,
HDMI_VIC_END},
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ 5370000, 2, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ #else
3485000, 1, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
- {{HDMIV_2560x1080p60hz,
- HDMI_VIC_END},
- 1980000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
- {{HDMIV_2560x1440p60hz,
- HDMI_VIC_END},
- 2415000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
- {{HDMIV_480x320p60hz,
- HDMI_VIC_END},
- 252000, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ #endif
++ {{HDMIV_2560x1080p60hz,
++ HDMI_VIC_END},
++ 1980000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
++ {{HDMIV_2560x1440p60hz,
++ HDMI_VIC_END},
++#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
++ 4830000, 2, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
++#else
++ 2415000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
++ {{HDMIV_480x320p60hz,
++ HDMI_VIC_END},
++ 252000, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
++#endif
};
/* For colordepth 10bits */
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
break;
- case 650000:
- hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004d8);
- if (frac_rate)
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
- else
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
- WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
- pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
- break;
- case 1065000:
- hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b1);
- if (frac_rate)
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
- else
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
- WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
- pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
- break;
- case 251750:
- hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004a7);
- if (frac_rate)
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
- else
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
- WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
- pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
- break;
- case 1080000://1600x900 1280x1024
- hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b3);
- if (frac_rate)
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
- else
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
- WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
- pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
- break;
- case 400000:
- hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000485);//133
- if (frac_rate)
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
- else
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
- WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
- pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
- break;
- case 1190000:
- hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004C6);//198
- if (frac_rate)
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
- else
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
- WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
- pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
- break;
- case 504000://1024x600
- hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004A7);
- if (frac_rate)
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
- else
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
- WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
- pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
- break;
- case 3485000://2560x1600
- hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000491);
- if (frac_rate)
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
- else
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
- WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
- pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
- break;
- case 2415000:
- hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004C8);//2560x1440
- if (frac_rate)
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
- else
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
- WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
- pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
- break;
- case 1980000://2560x1080
- hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004A5);
- if (frac_rate)
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
- else
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
- WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
- pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
- break;
- case 1932500://1920x1200
- hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004A1);
- if (frac_rate)
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
- else
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
- WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
- pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
- break;
- case 1620000://1600x1200
- hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000486);
- if (frac_rate)
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
- else
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
- WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
- pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
- break;
- case 855000://1360x768
- hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00048E);
- if (frac_rate)
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
- else
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
- WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
- pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
- break;
- case 835000:
- hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00048B);//1280x800
- if (frac_rate)
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
- else
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
- WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
- pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
- break;
- case 252000:
- hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004A8);//480X320
- if (frac_rate)
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
- else
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
- WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
- pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
- break;
- case 297600:
- hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004C6);//800x480
- if (frac_rate)
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001cccc);
- else
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
- WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
- pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
- break;
- case 432000:
- hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000490);//1280x480
- if (frac_rate)
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
- else
- hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
- hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
- hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
- WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
- pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
- break;
++ case 650000:
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004d8);
++ if (frac_rate)
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
++ else
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
++ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
++ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
++ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
++ break;
++ case 1065000:
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b1);
++ if (frac_rate)
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
++ else
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
++ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
++ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
++ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
++ break;
++ case 251750:
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004a7);
++ if (frac_rate)
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
++ else
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
++ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
++ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
++ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
++ break;
++ case 1080000://1600x900 1280x1024
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b3);
++ if (frac_rate)
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
++ else
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
++ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
++ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
++ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
++ break;
++ case 400000:
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000485);//133
++ if (frac_rate)
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
++ else
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
++ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
++ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
++ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
++ break;
++ case 1190000:
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004C6);//198
++ if (frac_rate)
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
++ else
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
++ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
++ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
++ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
++ break;
++ case 504000://1024x600
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004A7);
++ if (frac_rate)
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
++ else
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
++ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
++ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
++ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
++ break;
++ case 3485000://2560x1600
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000491);
++ if (frac_rate)
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
++ else
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
++ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
++ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
++ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
++ break;
++ case 1980000://2560x1080
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004A5);
++ if (frac_rate)
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
++ else
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
++ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
++ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
++ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
++ break;
++ case 1932500://1920x1200
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004A1);
++ if (frac_rate)
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
++ else
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
++ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
++ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
++ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
++ break;
++ case 1620000://1600x1200
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000486);
++ if (frac_rate)
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
++ else
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
++ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
++ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
++ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
++ break;
++ case 855000://1360x768
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00048E);
++ if (frac_rate)
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
++ else
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
++ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
++ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
++ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
++ break;
++ case 835000:
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00048B);//1280x800
++ if (frac_rate)
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
++ else
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
++ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
++ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
++ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
++ break;
++ case 252000:
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004A8);//480X320
++ if (frac_rate)
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
++ else
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
++ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
++ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
++ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
++ break;
++ case 297600:
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004C6);//800x480
++ if (frac_rate)
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001cccc);
++ else
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
++ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
++ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
++ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
++ break;
++ case 432000:
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000490);//1280x480
++ if (frac_rate)
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
++ else
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
++ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
++ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
++ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
++ break;
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ case 5370000:
+ /* stability issue : 5370000 (0xdf) -> 5360000 (0xde) */
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004de);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 3197500:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000485);
+ if (frac_rate)
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000110e1);
+ else
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00016000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 3960000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004a4);
+ if (frac_rate)
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000110e1);
+ else
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00016000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 3865000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004a0);
+ if (frac_rate)
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000110e1);
+ else
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00016000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 3420000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00048e);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 2685000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00046F);
+ if (frac_rate)
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+ else
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 2600000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00046C);
+ if (frac_rate)
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+ else
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 2560000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00046A);
+ if (frac_rate)
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+ else
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 2415000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000464);
+ if (frac_rate)
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+ else
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 2134000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00045A);
+ if (frac_rate)
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+ else
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 2058000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000455);
+ if (frac_rate)
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+ else
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 2000000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000453);
+ if (frac_rate)
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000140b4);
+ else
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 1855800:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00044C);
+ if (frac_rate)
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+ else
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001A000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 1560000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000440);
+ if (frac_rate)
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+ else
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001A000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 1540000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00043F);
+ if (frac_rate)
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+ else
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001A000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 1462500:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00043C);
+ if (frac_rate)
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+ else
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001A000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 1422000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00043A);
+ if (frac_rate)
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+ else
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001A000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 320000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00040D);
+ if (frac_rate)
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+ else
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
++ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
++ break;
++#else
++ case 2415000:
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004C8);//2560x1440
++ if (frac_rate)
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001ffff);
++ else
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
++ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
++ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
++ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ #endif
default:
- pr_info("error hpll clk: %d\n", clk);
+ pr_info("NO HPLL candidate - clk: %d, calculate HPLL\n", clk);
+
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ {
+ unsigned int m, m1, m2;
+ unsigned int ret;
+ unsigned int frac;
+
+ /* calculate m */
+ m = clk / XTAL_FREQ;
+ m &= 0xff;
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, (m | 0x3b000400));
+ pr_info("m1 0x%x, m2 0x%x, m 0x%x\n", m1, m2, m);
+
+ /* calculate frac */
+ frac = get_g12a_pll_get_frac(m, clk);
+ pr_info("m 0x%x, frac 0x%x\n", m, frac);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, frac);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+
+ if (m >= 0xf7) {
+ if (frac < 0x10000) {
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x11551293);
+ } else {
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0xea68dc00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290);
+ }
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x55540000);
+ } else {
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ }
+
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+
+ ret = (((hd_read_reg(P_HHI_HDMI_PLL_CNTL0) >> 30) & 0x3) == 0x3);
+ if (ret)
+ pr_info("[%s] HPLL set OK!\n", __func__);
+ else
+ pr_info("[%s] Error! Check HPLL track!\n", __func__);
+ }
+ #endif
break;
}
}
index = lcd_power->power_on_step[i].index;
switch (lcd_power->power_on_step[i].type) {
case LCD_POWER_TYPE_CPU:
+ case LCD_POWER_TYPE_EXPANDER_IO:
+ case LCD_POWER_TYPE_WAIT_GPIO:
if (index < LCD_CPU_GPIO_NUM_MAX)
lcd_cpu_gpio_probe(index);
break;
index = lcd_power->power_off_step[i].index;
switch (lcd_power->power_off_step[i].type) {
case LCD_POWER_TYPE_CPU:
+ case LCD_POWER_TYPE_EXPANDER_IO:
+ case LCD_POWER_TYPE_WAIT_GPIO:
if (index < LCD_CPU_GPIO_NUM_MAX)
lcd_cpu_gpio_probe(index);
break;
mux_sel, mux_bit, 2);
}
if (clk_bit < 0xff)
- vout_func_vcbus_setb(VPU_VENCX_CLK_CTRL, clk_sel, clk_bit, 1);
+ vout_vcbus_setb(VPU_VENCX_CLK_CTRL, clk_sel, clk_bit, 1);
-#if 0
+#if 1
VOUTPR("%s: %d, mux_sel=%d, clk_sel=%d\n",
__func__, index, mux_sel, clk_sel);
#endif
extern int vout2_shutdown(void);
#endif
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ extern int cvbs_cable_connected(void);
++#else
+extern int is_panel_exist(void);
+ #endif
#endif
char init_mode_str[VMODE_NAME_LEN_MAX];
int ret = 0;
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ strncpy(vout_mode_uboot,
+ (vout_get_hpd_state() || !cvbs_cable_connected()) ?
+ hdmimode : cvbsmode,
+ sizeof(vout_mode_uboot));
++#else
+ strncpy(vout_mode_uboot,
+ (vout_get_hpd_state() || !is_panel_exist()) ?
+ hdmimode : "panel",
+ sizeof(vout_mode_uboot));
+ #endif
snprintf(init_mode_str, VMODE_NAME_LEN_MAX, "%s", vout_mode_uboot);
vout_init_vmode = validate_vmode(vout_mode_uboot);
if (vout_init_vmode >= VMODE_MAX) {
-#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
++#if 1
VOUTERR("no matched vout mode %s, force to set 1080p60hz\n",
vout_mode_uboot);
snprintf(init_mode_str, VMODE_NAME_LEN_MAX, "%s", "1080p60hz");
hpd_state = vout_get_hpd_state();
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ /* Unless CVBS cable is not attached, we assumed that HDMI cable is attached */
+ if (!cvbs_cable_connected())
+ hpd_state = 1;
++#else
+ if (!is_panel_exist())
+ hpd_state = 1;
+ #endif
if (hpd_state) {
- cur_vmode = validate_vmode(hdmimode);
- snprintf(cur_mode_str, VMODE_NAME_LEN_MAX, "%s", hdmimode);
+ /* Vout will check the checksum of EDID of uboot and kernel.
+ * If checksum is different. Vout will set null to display/mode.
+ * When systemcontrol bootup, it will set the correct mode and
+ * colorspace according to current EDID from kernel.
+ */
+ if ((memcmp(hdmichecksum, info->hdmichecksum, 10)) &&
+ (memcmp(emptychecksum, info->hdmichecksum, 10)) &&
+ (memcmp(invalidchecksum, hdmichecksum, 10))) {
+ VOUTPR("hdmi crc is diff between uboot and kernel\n");
+ cur_vmode = validate_vmode("null");
+ snprintf(cur_mode_str, VMODE_NAME_LEN_MAX, "null");
+
+ } else {
+ cur_vmode = validate_vmode(hdmimode);
+ snprintf(cur_mode_str, VMODE_NAME_LEN_MAX,
+ "%s", hdmimode);
+ }
} else {
cur_vmode = validate_vmode(cvbsmode);
snprintf(cur_mode_str, VMODE_NAME_LEN_MAX, "%s", cvbsmode);
strncpy(vout_mode, cur_mode_str, VMODE_NAME_LEN_MAX);
if (cur_vmode >= VMODE_MAX) {
-#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
++#if 1
VOUTERR("%s: no matched vmode: %s, force to set 1080p60hz\n",
__func__, cur_mode_str);
cur_vmode = validate_vmode("1080p60hz");
set_vframe(dec, vf, pic, 0);
decoder_do_frame_check(hw_to_vdec(dec), vf);
kfifo_put(&dec->display_q, (const struct vframe_s *)vf);
+ ATRACE_COUNTER(MODULE_NAME, vf->pts);
- #ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
+ #ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
++ dec->gvs->frame_dur = dec->frame_dur;
/*count info*/
-- gvs->frame_dur = dec->frame_dur;
-- vdec_count_info(gvs, 0, stream_offset);
++ vdec_count_info(dec->gvs, 0, pic->stream_offset);
#endif
hw_to_vdec(dec)->vdec_fps_detec(hw_to_vdec(dec)->id);
- vf_notify_receiver(dec->provider_name,
- VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
+ if (without_display_mode == 0) {
+ vf_notify_receiver(dec->provider_name,
+ VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
+ } else
+ vavs2_vf_put(vavs2_vf_get(dec), dec);
}
}
/*!NO_DISPLAY*/
vstatus->error_count = 0;
vstatus->status = dec->stat | dec->fatal_error;
vstatus->frame_dur = dec->frame_dur;
- #if 0 //#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
- vstatus->bit_rate = gvs->bit_rate;
- vstatus->frame_data = gvs->frame_data;
- vstatus->total_data = gvs->total_data;
- vstatus->frame_count = gvs->frame_count;
- vstatus->error_frame_count = gvs->error_frame_count;
- vstatus->drop_frame_count = gvs->drop_frame_count;
- vstatus->total_data = gvs->total_data;
- vstatus->samp_cnt = gvs->samp_cnt;
- vstatus->offset = gvs->offset;
+ #ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
- vstatus->bit_rate = gvs->bit_rate;
- vstatus->frame_data = gvs->frame_data;
- vstatus->total_data = gvs->total_data;
- vstatus->frame_count = gvs->frame_count;
- vstatus->error_frame_count = gvs->error_frame_count;
- vstatus->drop_frame_count = gvs->drop_frame_count;
- vstatus->total_data = gvs->total_data;
- vstatus->samp_cnt = gvs->samp_cnt;
- vstatus->offset = gvs->offset;
++ vstatus->bit_rate = dec->gvs->bit_rate;
++ vstatus->frame_data = dec->gvs->frame_data;
++ vstatus->total_data = dec->gvs->total_data;
++ vstatus->frame_count = dec->gvs->frame_count;
++ vstatus->error_frame_count = dec->gvs->error_frame_count;
++ vstatus->drop_frame_count = dec->gvs->drop_frame_count;
++ vstatus->total_data = dec->gvs->total_data;
++ vstatus->samp_cnt = dec->gvs->samp_cnt;
++ vstatus->offset = dec->gvs->offset;
snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
"%s", DRIVER_NAME);
#endif
}
update_vf_memhandle(pbi, vf, pic_config);
if (!(pic_config->y_crop_width == 196
- && pic_config->y_crop_height == 196
- && (debug & VP9_DEBUG_NO_TRIGGER_FRAME) == 0
- )) {
- inc_vf_ref(pbi, pic_config->index);
- decoder_do_frame_check(hw_to_vdec(pbi), vf);
- kfifo_put(&pbi->display_q, (const struct vframe_s *)vf);
- pbi->vf_pre_count++;
- #ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
- /*count info*/
- gvs->frame_dur = pbi->frame_dur;
- vdec_count_info(gvs, 0, stream_offset);
- #endif
- hw_to_vdec(pbi)->vdec_fps_detec(hw_to_vdec(pbi)->id);
- vf_notify_receiver(pbi->provider_name,
- VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
+ && pic_config->y_crop_height == 196
+ && (debug & VP9_DEBUG_NO_TRIGGER_FRAME) == 0
+ && (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX))) {
+ inc_vf_ref(pbi, pic_config->index);
+ decoder_do_frame_check(hw_to_vdec(pbi), vf);
+ kfifo_put(&pbi->display_q, (const struct vframe_s *)vf);
+ ATRACE_COUNTER(MODULE_NAME, vf->pts);
+ pbi->vf_pre_count++;
+ #ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
+ /*count info*/
- gvs->frame_dur = pbi->frame_dur;
- vdec_count_info(gvs, 0, stream_offset);
++ pbi->gvs->frame_dur = pbi->frame_dur;
++ vdec_count_info(pbi->gvs, 0, stream_offset);
+ #endif
+ hw_to_vdec(pbi)->vdec_fps_detec(hw_to_vdec(pbi)->id);
+ if (without_display_mode == 0) {
+ vf_notify_receiver(pbi->provider_name,
+ VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
+ } else
+ vvp9_vf_put(vvp9_vf_get(pbi), pbi);
} else {
pbi->stat |= VP9_TRIGGER_FRAME_DONE;
hevc_source_changed(VFORMAT_VP9, 196, 196, 30);
vstatus->error_count = 0;
vstatus->status = vp9->stat | vp9->fatal_error;
vstatus->frame_dur = vp9->frame_dur;
- #if 0 //#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
- vstatus->bit_rate = gvs->bit_rate;
- vstatus->frame_data = gvs->frame_data;
- vstatus->total_data = gvs->total_data;
- vstatus->frame_count = gvs->frame_count;
- vstatus->error_frame_count = gvs->error_frame_count;
- vstatus->drop_frame_count = gvs->drop_frame_count;
- vstatus->total_data = gvs->total_data;
- vstatus->samp_cnt = gvs->samp_cnt;
- vstatus->offset = gvs->offset;
+ #ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
- vstatus->bit_rate = gvs->bit_rate;
- vstatus->frame_data = gvs->frame_data;
- vstatus->total_data = gvs->total_data;
- vstatus->frame_count = gvs->frame_count;
- vstatus->error_frame_count = gvs->error_frame_count;
- vstatus->drop_frame_count = gvs->drop_frame_count;
- vstatus->total_data = gvs->total_data;
- vstatus->samp_cnt = gvs->samp_cnt;
- vstatus->offset = gvs->offset;
++ vstatus->bit_rate = vp9->gvs->bit_rate;
++ vstatus->frame_data = vp9->gvs->frame_data;
++ vstatus->total_data = vp9->gvs->total_data;
++ vstatus->frame_count = vp9->gvs->frame_count;
++ vstatus->error_frame_count = vp9->gvs->error_frame_count;
++ vstatus->drop_frame_count = vp9->gvs->drop_frame_count;
++ vstatus->total_data = vp9->gvs->total_data;
++ vstatus->samp_cnt = vp9->gvs->samp_cnt;
++ vstatus->offset = vp9->gvs->offset;
snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
"%s", DRIVER_NAME);
#endif
fec_bch_add = dtmb_read_reg(DTMB_TOP_FEC_BCH_ACC);
fec_ldpc_unc_acc = dtmb_read_reg(DTMB_TOP_FEC_LDPC_UNC_ACC);
fec_ldpc_it_avg = dtmb_read_reg(DTMB_TOP_FEC_LDPC_IT_AVG);
- pr_dbg("??FSM ??: %x %x %x %x\n",
- pr_dbg("¡¾FSM ¡¿: %x %x %x %x\n",
++ pr_dbg("FSM: %x %x %x %x\n",
dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE0),
dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE1),
dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE2),
dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE3));
pr_dbg
- ("??AGC ??: agc_power %d,agc_if_gain %d,agc_rf_gain %d,",
- ("¡¾AGC ¡¿: agc_power %d,agc_if_gain %d,agc_rf_gain %d,",
++ ("AGC: agc_power %d,agc_if_gain %d,agc_rf_gain %d,",
(-(((dtmb_read_reg(DTMB_TOP_FRONT_AGC) >> 22) & 0x3ff) / 16)),
((dtmb_read_reg(DTMB_TOP_FRONT_AGC)) & 0x3ff),
((dtmb_read_reg(DTMB_TOP_FRONT_AGC) >> 11) & 0x7ff));
((dtmb_read_reg(DTMB_TOP_FRONT_DAGC) >> 8) & 0xfff),
(dtmb_read_reg(DTMB_TOP_CTRL_SYS_OFDM_CNT) >> 8) & 0x7ffff);
pr_dbg
- ("??TPS ?? SC or MC %2d,f_r %2d qam_nr %2d ",
- ("¡¾TPS ¡¿ SC or MC %2d,f_r %2d qam_nr %2d ",
++ ("TPS SC or MC %2d,f_r %2d qam_nr %2d ",
(dtmb_read_reg(DTMB_TOP_CHE_OBS_STATE1) >> 1) & 0x1,
(tps >> 22) & 0x1, (tps >> 21) & 0x1);
pr_dbg
readl(host->base + SD_EMMC_DELAY2_V3));
win_size = emmc_ds_manual_sht(mmc);
emmc_data_alignment(mmc, win_size);
-
+ set_emmc_cmd_delay(mmc, 0);
}
/* test clock, return delay cells for one cycle
*/
u32 u2_hhi_mem_pd_shift = 0;
u32 u2_hhi_mem_pd_mask = 0;
u32 u2_ctrl_iso_shift = 0;
- gpiod_direction_output(usb_gd, 1);
+
+ gpio_name = of_get_property(dev->of_node, "gpio-vbus-power", NULL);
+ if (gpio_name) {
+ usb_gd = gpiod_get_index(&pdev->dev,
+ NULL, 0, GPIOD_OUT_LOW);
+ if (IS_ERR(usb_gd))
+ return -1;
++ gpiod_direction_output(usb_gd, 1);
+ }
+
prop = of_get_property(dev->of_node, "portnum", NULL);
if (prop)
portnum = of_read_ulong(prop, 1);
#define DHD_PREALLOC_OSL_BUF_SIZE (STATIC_BUF_MAX_NUM * STATIC_BUF_SIZE)
#define DHD_PREALLOC_WIPHY_ESCAN0_SIZE (64 * 1024)
#define DHD_PREALLOC_DHD_INFO_SIZE (32 * 1024)
- #define DHD_PREALLOC_MEMDUMP_RAM_SIZE (1280 * 1024)
- #define DHD_PREALLOC_DHD_WLFC_HANGER_SIZE (73 * 1024)
+#define DHD_PREALLOC_WL_ESCAN_INFO_SIZE (67 * 1024)
+ #define DHD_PREALLOC_MEMDUMP_RAM_SIZE (1290 * 1024)
+ #define DHD_PREALLOC_DHD_WLFC_HANGER_SIZE (73 * 1024)
+ #define DHD_PREALLOC_DHD_LOG_DUMP_BUF_SIZE (1024 * 1024 * CUSTOM_LOG_DUMP_BUFSIZE_MB)
+ #define DHD_PREALLOC_DHD_LOG_DUMP_BUF_EX_SIZE (8 * 1024)
+ #define DHD_PREALLOC_WL_WEXT_INFO_SIZE (70 * 1024)
#ifdef CONFIG_64BIT
#define DHD_PREALLOC_IF_FLOW_LKUP_SIZE (20 * 1024 * 2)
#else
# taken to initialize them in the correct order. Link order is the only way
# to ensure this currently.
obj-$(CONFIG_TEGRA_HOST1X) += host1x/
- obj-y += drm/ vga/
+ obj-y += drm/ vga/
obj-$(CONFIG_IMX_IPUV3_CORE) += ipu-v3/
-
-ifneq ($(CONFIG_DRM_BIFROST),y)
obj-y += arm/
-endif
break;
case SPEED_1000:
val |= (1 << 3);
-- break;
++ break;
}
writel(val, dwmac->reg);
struct pinctrl *pin_ctrl;
struct pinctrl_state *turnon_tes = NULL;
pr_info("resuem inter = %d\n", is_internal_phy);
+ if (ee_reset_base)
+ writel((1 << 11), (void __iomem *)
+ (unsigned long)ee_reset_base);
+
if ((is_internal_phy) && (support_mac_wol == 0)) {
+ if (ee_reset_base)
+ writel((1 << 11), (void __iomem *)
+ (unsigned long)ee_reset_base);
+
pin_ctrl = devm_pinctrl_get(dev);
if (IS_ERR_OR_NULL(pin_ctrl)) {
pr_info("pinctrl is null\n");
}
#endif
phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd04); /*set page 0xd04*/
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ phy_write(phydev, RTL821x_LCR,
+ (1 << 6) | (1 << 9) // LED1 - GREEN (100Mbps)
+ | (1 << 13) | (1 << 14)); // LED2 - AMBER (1000Mbps)
+ #else
phy_write(phydev, RTL821x_LCR, 0XC171); /*led configuration*/
+ #endif
+ g_phydev = phydev;
+
+ if (3 == mcu_get_wol_status())
+ enable_wol(3, false);
+
/* restore to default page 0 */
phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
}
#ifdef CONFIG_AMLOGIC_ETH_PRIVE
-
-static u32 enable_wol = 0;
-
-static int __init enable_wol_setup(char *str)
-{
- enable_wol = (str[0] != '0');
- support_external_phy_wol = enable_wol;
-
- return 0;
-}
-__setup("enable_wol=", enable_wol_setup);
+
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
+ #include <linux/amlogic/scpi_protocol.h>
+ #endif
+
int rtl8211f_suspend(struct phy_device *phydev)
{
- int value = 0;
-
+ #if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
- scpi_send_usr_data(SCPI_CL_WOL, &enable_wol, sizeof(enable_wol));
++ scpi_send_usr_data(SCPI_CL_WOL, &wol_enable, sizeof(wol_enable));
+ #endif
+
if (support_external_phy_wol) {
- mutex_lock(&phydev->lock);
- phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd8a);
- /*set magic packet for wol*/
- phy_write(phydev, 0x10, 0x1000);
- phy_write(phydev, 0x11, 0x9fff);
- /*pad isolation*/
- value = phy_read(phydev, 0x13);
- phy_write(phydev, 0x13, value | (0x1 << 15));
+ printk("rtl8211f_suspend...\n");
+ enable_wol((wol_enable << 0), false);
+ } else {
+ int value;
+
/*pin 31 pull high*/
- phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd40);
- value = phy_read(phydev, 0x16);
- phy_write(phydev, 0x16, value | (1 << 5));
- phy_write(phydev, RTL8211F_PAGE_SELECT, 0);
+ phy_write(g_phydev, RTL8211F_PAGE_SELECT, 0xd40);
+ value = phy_read(g_phydev, 0x16);
+ phy_write(g_phydev, 0x16, value | (1 << 5));
+ phy_write(g_phydev, RTL8211F_PAGE_SELECT, 0);
- mutex_unlock(&phydev->lock);
- } else {
genphy_suspend(phydev);
}
return 0;
obj-$(CONFIG_USB_NET_QMI_WWAN) += qmi_wwan.o
obj-$(CONFIG_USB_NET_CDC_MBIM) += cdc_mbim.o
obj-$(CONFIG_USB_NET_CH9200) += ch9200.o
- obj-y += GobiNet.o
+
++obj-$(CONFIG_USB_USBNET) += GobiNet.o
+GobiNet-objs := GobiUSBNet.o QMIDevice.o QMI.o
source "drivers/net/wireless/st/Kconfig"
source "drivers/net/wireless/ti/Kconfig"
source "drivers/net/wireless/zydas/Kconfig"
-source "drivers/net/wireless/esp8089/Kconfig"
+source "drivers/net/wireless/bcmdhd/Kconfig"
+ source "drivers/net/wireless/rtl8812au/Kconfig"
+ source "drivers/net/wireless/rtl8188eu/Kconfig"
+ source "drivers/net/wireless/rtl8192cu/Kconfig"
config PCMCIA_RAYCS
tristate "Aviator/Raytheon 2.4GHz wireless support"
obj-$(CONFIG_USB_NET_RNDIS_WLAN) += rndis_wlan.o
obj-$(CONFIG_MAC80211_HWSIM) += mac80211_hwsim.o
-obj-$(CONFIG_ESP8089) += esp8089/
+
+ obj-$(CONFIG_88XXAU) += rtl8812au/
+ obj-$(CONFIG_RTL8188EU) += rtl8188eu/
+ obj-$(CONFIG_RTL8192CU) += rtl8192cu/
buffer->sg_table->nents, DMA_BIDIRECTIONAL);
#endif
dma_buf_put(dmabuf);
++
return 0;
}
u32 freq_mhz, voltage_mv;
u64 power;
++#if defined(CONFIG_IR_HK_LIRC_HELPER)
+ if (board_is_odroidn2()) {
+ if (i >= num_opps)
+ break;
+ } else {
+ if (i >= num_opps) {
+ rcu_read_unlock();
+ ret = -EAGAIN;
+ goto free_power_table;
+ }
+ }
++#else
+ if (i >= num_opps) {
+ rcu_read_unlock();
+ ret = -EAGAIN;
+ goto free_power_table;
+ }
++#endif
freq_mhz = freq / 1000000;
voltage_mv = dev_pm_opp_get_voltage(opp) / 1000;
} else {
tz->polling_delay = 0;
}
-
#endif
-
+
mutex_unlock(&tz->lock);
data->mode = mode;
xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
port_change_bit, wIndex, port_status);
#ifdef CONFIG_AMLOGIC_USB
- if (odroid_amlogic_usb3()) {
- if (DEV_HIGHSPEED(port_status) &&
- (wValue == USB_PORT_FEAT_C_RESET))
- set_usb_phy_host_tuning(wIndex, 0);
- if (DEV_LOWSPEED(port_status) &&
- (wValue == USB_PORT_FEAT_C_RESET))
- set_usb_phy_host_low_reset(wIndex);
- }
+ if (DEV_HIGHSPEED(port_status) &&
- (wValue == USB_PORT_FEAT_C_RESET))
++ (wValue == USB_PORT_FEAT_C_RESET))
+ set_usb_phy_host_tuning(wIndex, 0);
+ if (DEV_LOWSPEED(port_status) &&
- (wValue == USB_PORT_FEAT_C_RESET))
++ (wValue == USB_PORT_FEAT_C_RESET))
+ set_usb_phy_host_low_reset(wIndex);
#endif
}
if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
xhci_dbg_trace(xhci, trace_xhci_dbg_init,
"xHCI 1.0: support USB2 software lpm");
- xhci->sw_lpm_support = 1;
+
#ifdef CONFIG_AMLOGIC_USB
- if (odroid_amlogic_usb3())
- xhci->sw_lpm_support = 0;
+ xhci->sw_lpm_support = 0;
+#else
+ xhci->sw_lpm_support = 1;
#endif
if (temp & XHCI_HLC) {
xhci_dbg_trace(xhci, trace_xhci_dbg_init,
continue;
}
xhci->port_array[i] = major_revision;
- if (major_revision == 0x03)
+ if (major_revision == 0x03) {
+ xhci->num_usb3_ports++;
#ifdef CONFIG_AMLOGIC_USB
- if (xhci->quirks & XHCI_AML_SUPER_SPEED_SUPPORT)
- xhci->num_usb3_ports++;
- else
- if (odroid_amlogic_usb3()) {
- if (!(xhci->quirks & XHCI_AML_SUPER_SPEED_SUPPORT))
- xhci->num_usb3_ports = 0;
- }
++ if (!(xhci->quirks & XHCI_AML_SUPER_SPEED_SUPPORT))
+ xhci->num_usb3_ports = 0;
- #else
- xhci->num_usb3_ports++;
#endif
- else
+ } else {
xhci->num_usb2_ports++;
+ }
}
/* FIXME: Should we disable ports not in the Extended Capabilities? */
}
de_name.name = d->filename[bit_pos];
de_name.len = le16_to_cpu(de->name_len);
-- /* check memory boundary before moving forward */
-- bit_pos += GET_DENTRY_SLOTS(le16_to_cpu(de->name_len));
-- if (unlikely(bit_pos > d->max ||
-- le16_to_cpu(de->name_len) > F2FS_NAME_LEN)) {
-- f2fs_msg(F2FS_I_SB(d->inode)->sb, KERN_WARNING,
-- "%s: corrupted namelen=%d, run fsck to fix.",
-- __func__, le16_to_cpu(de->name_len));
-- set_sbi_flag(F2FS_I_SB(d->inode)->sb->s_fs_info, SBI_NEED_FSCK);
-- return -EINVAL;
-- }
--
if (f2fs_encrypted_inode(d->inode)) {
int save_len = fstr->len;
int err;
if (sbi->readdir_ra == 1)
ra_node_page(sbi, le32_to_cpu(de->ino));
++ bit_pos += GET_DENTRY_SLOTS(le16_to_cpu(de->name_len));
ctx->pos = start_pos + bit_pos;
}
return 0;
* we get the space back only from inline_data.
*/
fi->i_inline_xattr_size = 0;
+ }
+
+ if (!sanity_check_inode(inode, node_page)) {
+ f2fs_put_page(node_page, 1);
+ return -EINVAL;
+ }
+
/* check data exist */
if (f2fs_has_inline_data(inode) && !f2fs_exist_data(inode))
__recover_inline_status(inode, node_page);
continue;
}
new_flags = vma->vm_flags & ~(VM_UFFD_MISSING | VM_UFFD_WP);
- prev = vma_merge(mm, prev, vma->vm_start, vma->vm_end,
- new_flags, vma->anon_vma,
- vma->vm_file, vma->vm_pgoff,
- vma_policy(vma),
- NULL_VM_UFFD_CTX,
- vma_get_anon_name(vma));
- if (prev)
- vma = prev;
- else
- prev = vma;
+ if (still_valid) {
+ prev = vma_merge(mm, prev, vma->vm_start, vma->vm_end,
+ new_flags, vma->anon_vma,
+ vma->vm_file, vma->vm_pgoff,
+ vma_policy(vma),
- NULL_VM_UFFD_CTX);
++ NULL_VM_UFFD_CTX,
++ vma_get_anon_name(vma));
+ if (prev)
+ vma = prev;
+ else
+ prev = vma;
+ }
vma->vm_flags = new_flags;
vma->vm_userfaultfd_ctx = NULL_VM_UFFD_CTX;
}
#define MESON_CPU_VERSION_LVL_MISC 3
#define MESON_CPU_VERSION_LVL_MAX MESON_CPU_VERSION_LVL_MISC
+extern const char *machine_model;
+ extern const char *machine_name;
+ extern unsigned int system_rev;
#define CHIPID_LEN 16
void cpuinfo_get_chipid(unsigned char *cid, unsigned int size);
*/
#define HDMITX_VIC420_OFFSET 0x100
#define HDMITX_VIC420_FAKE_OFFSET 0x200
- #define HDMITX_VESA_OFFSET 0x301
-#define HDMITX_VESA_OFFSET 0x300
-
++#define HDMITX_VESA_OFFSET 0x301
#define HDMITX_VIC_MASK 0xff
HDMI_VIC_FAKE = HDMITX_VIC420_FAKE_OFFSET,
HDMIV_640x480p60hz = HDMITX_VESA_OFFSET,
HDMIV_800x480p60hz,
- HDMIV_1280x480p60hz,
++ HDMIV_1280x480p60hz,
HDMIV_800x600p60hz,
HDMIV_852x480p60hz,
HDMIV_854x480p60hz,
HDMIV_2560x1440p60hz,
HDMIV_2560x1600p60hz,
HDMIV_3440x1440p60hz,
- HDMIV_480x320p60hz,
++#if !defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
++ HDMIV_480x320p60hz,
++#endif
HDMI_VIC_END,
};
LCD_POWER_TYPE_PMU,
LCD_POWER_TYPE_SIGNAL,
LCD_POWER_TYPE_EXTERN,
+ LCD_POWER_TYPE_EXPANDER_IO,
+ LCD_POWER_TYPE_WAIT_GPIO,
+ LCD_POWER_TYPE_CLK_SS,
LCD_POWER_TYPE_MAX,
};
#define CEC_WAKEUP 8
#define REMOTE_CUS_WAKEUP 9
#define ETH_PHY_WAKEUP 10
+#define WOL_WAKEUP 13
extern unsigned int get_resume_method(void);
extern unsigned int is_pm_freeze_mode(void);
+ #ifdef CONFIG_AMLOGIC_ADC_KEYPADS
+ bool meson_adc_is_alive_freeze(void);
+ #endif
#ifdef CONFIG_AMLOGIC_LEGACY_EARLY_SUSPEND
enum {
#define _POWER_CTRL_H_
#include <linux/types.h>
+ #ifdef CONFIG_AMLOGIC_POWER
+ bool is_support_power_ctrl(void);
int power_ctrl_sleep(bool power_on, unsigned int shift);
+ int power_ctrl_sleep_mask(bool power_on,
+ unsigned int mask_val, unsigned int shift);
int power_ctrl_iso(bool power_on, unsigned int shift);
+ int power_ctrl_iso_mask(bool power_on,
+ unsigned int mask_val, unsigned int shift);
int power_ctrl_mempd0(bool power_on, unsigned int mask_val, unsigned int shift);
+ #else
+ static inline int power_ctrl_sleep(bool power_on, unsigned int shift)
+ {
+ return -EINVAL;
+ }
+
+ static inline int power_ctrl_iso(bool power_on, unsigned int shift)
+ {
+ return -EINVAL;
+ }
+
+ static inline int power_ctrl_mempd0(bool power_on, unsigned int mask_val,
+ unsigned int shift)
+ {
+ return -EINVAL;
+ }
+ #endif
++
#endif /*_POWER_CTRL_H_*/
if (hardirq_count())
irqtime_account_delta(irqtime, delta, CPUTIME_IRQ);
else if (in_serving_softirq() && curr != this_cpu_ksoftirqd())
- irqtime->softirq_time += delta;
+ irqtime_account_delta(irqtime, delta, CPUTIME_SOFTIRQ);
+#ifdef CONFIG_SCHED_WALT
+ else
+ account = false;
- #endif
+
- u64_stats_update_end(&irqtime->sync);
- #ifdef CONFIG_SCHED_WALT
+ if (account)
+ walt_account_irqtime(cpu, curr, delta, wallclock);
+#endif
- irqtime_account_delta(irqtime, delta, CPUTIME_SOFTIRQ);
}
EXPORT_SYMBOL_GPL(irqtime_account_irq);
kasan_poison_shadow((void *)redzone_start, redzone_end - redzone_start,
KASAN_PAGE_REDZONE);
}
--
#endif
void kasan_krealloc(const void *object, size_t size, gfp_t flags)
void ip6_sk_update_pmtu(struct sk_buff *skb, struct sock *sk, __be32 mtu)
{
+ int oif = sk->sk_bound_dev_if;
struct dst_entry *dst;
- ip6_update_pmtu(skb, sock_net(sk), mtu,
- sk->sk_bound_dev_if, sk->sk_mark, sk->sk_uid);
+ if (!oif && skb->dev)
+ oif = l3mdev_master_ifindex(skb->dev);
+
- ip6_update_pmtu(skb, sock_net(sk), mtu,
- sk->sk_bound_dev_if, sk->sk_mark, sk->sk_uid);
-
++ ip6_update_pmtu(skb, sock_net(sk), mtu, oif, sk->sk_mark, sk->sk_uid);
+
dst = __sk_dst_get(sk);
if (!dst || !dst->obsolete ||
dst->ops->check(dst, inet6_sk(sk)->dst_cookie))
reg = calc_toddr_address(EE_AUDIO_TODDR_A_CTRL1, reg_base);
if (index == RESAMPLE_A)
aml_audiobus_update_bits(actrl, reg, 1 << 27, !!enable << 27);
- else if (index == RESAMPLE_B)
- aml_audiobus_update_bits(actrl, reg, 1 << 26, !!enable << 26);
-
}
static void aml_resample_enable(
},
};
- static const struct snd_kcontrol_new earc_controls[] = {
-
+ static const char *const attended_type[] = {
+ "DISCONNECT",
+ "ARC",
+ "eARC"
+ };
+
+ const struct soc_enum attended_type_enum =
+ SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(attended_type),
+ attended_type);
+
+ int earcrx_get_attend_type(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+ struct earc *p_earc = dev_get_drvdata(component->dev);
+ enum attend_type type =
+ earcrx_cmdc_get_attended_type(p_earc->rx_cmdc_map);
+
+ ucontrol->value.integer.value[0] = type;
+
+ return 0;
+ }
+
+ int earcrx_set_attend_type(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+ struct earc *p_earc = dev_get_drvdata(component->dev);
+ enum cmdc_st state = earcrx_cmdc_get_state(p_earc->rx_cmdc_map);
+
+ if (state != CMDC_ST_IDLE2)
+ return 0;
+
+ /* only support set cmdc from idle to ARC */
+
+ return 0;
+ }
+
+ static int earcrx_arc_get_enable(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+ struct earc *p_earc = dev_get_drvdata(component->dev);
+ enum attend_type type =
+ earcrx_cmdc_get_attended_type(p_earc->rx_cmdc_map);
+
+ ucontrol->value.integer.value[0] = (bool)(type == ATNDTYP_ARC);
+
+ return 0;
+ }
+
+ static int earcrx_arc_set_enable(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+ struct earc *p_earc = dev_get_drvdata(component->dev);
+
+ if (!p_earc)
+ return 0;
+
+ earcrx_cmdc_arc_connect(
+ p_earc->rx_cmdc_map,
+ (bool)ucontrol->value.integer.value[0]);
+
+ return 0;
+ }
+
+ int earctx_get_attend_type(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+ struct earc *p_earc = dev_get_drvdata(component->dev);
+ enum attend_type type;
+
+ if (!p_earc || IS_ERR(p_earc->tx_top_map))
+ return 0;
+
+ type = earctx_cmdc_get_attended_type(p_earc->tx_cmdc_map);
+
+ ucontrol->value.integer.value[0] = type;
+
+ return 0;
+ }
+
+ int earctx_set_attend_type(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+ struct earc *p_earc = dev_get_drvdata(component->dev);
+ enum cmdc_st state;
+
+ if (!p_earc || IS_ERR(p_earc->tx_top_map))
+ return 0;
+
+ state = earctx_cmdc_get_state(p_earc->tx_cmdc_map);
+
+ if (state != CMDC_ST_IDLE2)
+ return 0;
+
+ /* only support set cmdc from idle to ARC */
+
+ return 0;
+ }
+
+ int earcrx_get_latency(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+ struct earc *p_earc = dev_get_drvdata(component->dev);
+ enum cmdc_st state;
+ u8 val = 0;
+
+ if (!p_earc || IS_ERR(p_earc->rx_top_map))
+ return 0;
+
+ state = earcrx_cmdc_get_state(p_earc->rx_cmdc_map);
+ if (state != CMDC_ST_EARC)
+ return 0;
+
+ earcrx_cmdc_get_latency(p_earc->rx_cmdc_map, &val);
+ ucontrol->value.integer.value[0] = val;
+ return 0;
+ }
+
+ int earcrx_set_latency(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+ struct earc *p_earc = dev_get_drvdata(component->dev);
+ u8 latency = ucontrol->value.integer.value[0];
+ enum cmdc_st state;
+
+ if (!p_earc || IS_ERR(p_earc->rx_top_map))
+ return 0;
+
+ state = earcrx_cmdc_get_state(p_earc->rx_cmdc_map);
+ if (state != CMDC_ST_EARC)
+ return 0;
+
+ earcrx_cmdc_set_latency(p_earc->rx_cmdc_map, &latency);
+
+ return 0;
+ }
+
+ int earcrx_get_cds(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+ struct earc *p_earc = dev_get_drvdata(component->dev);
+ struct soc_bytes_ext *bytes_ext =
+ (struct soc_bytes_ext *)kcontrol->private_value;
+ u8 *value = (u8 *)ucontrol->value.bytes.data;
+ enum cmdc_st state;
+ int i;
+ u8 data[256];
+
+ if (!p_earc || IS_ERR(p_earc->rx_top_map))
+ return 0;
+
+ state = earcrx_cmdc_get_state(p_earc->rx_cmdc_map);
+ if (state != CMDC_ST_EARC)
+ return 0;
+
+ earcrx_cmdc_get_cds(p_earc->rx_cmdc_map, data);
+
+ for (i = 0; i < bytes_ext->max; i++)
+ *value++ = data[i];
+
+ return 0;
+ }
+
+ int earcrx_set_cds(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+ struct earc *p_earc = dev_get_drvdata(component->dev);
+ struct soc_bytes_ext *params = (void *)kcontrol->private_value;
+ u8 *data;
+ enum cmdc_st state;
+
+ if (!p_earc || IS_ERR(p_earc->rx_top_map))
+ return 0;
+
+ state = earcrx_cmdc_get_state(p_earc->rx_cmdc_map);
+ if (state != CMDC_ST_EARC)
+ return 0;
+
+ data = kmemdup(ucontrol->value.bytes.data,
+ params->max, GFP_KERNEL | GFP_DMA);
+ if (!data)
+ return -ENOMEM;
+
+ earcrx_cmdc_set_cds(p_earc->rx_cmdc_map, data);
+
+ kfree(data);
+
+ return 0;
+ }
+
+ int earctx_get_latency(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+ struct earc *p_earc = dev_get_drvdata(component->dev);
+ enum cmdc_st state;
+ u8 val = 0;
+
+ if (!p_earc || IS_ERR(p_earc->tx_top_map))
+ return 0;
+
+ state = earctx_cmdc_get_state(p_earc->tx_cmdc_map);
+ if (state != CMDC_ST_EARC)
+ return 0;
+
+ earctx_cmdc_get_latency(p_earc->tx_cmdc_map, &val);
+
+ ucontrol->value.integer.value[0] = val;
+
+ return 0;
+ }
+
+ int earctx_set_latency(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+ struct earc *p_earc = dev_get_drvdata(component->dev);
+ u8 latency = ucontrol->value.integer.value[0];
+ enum cmdc_st state;
+
+ if (!p_earc || IS_ERR(p_earc->tx_top_map))
+ return 0;
+
+ state = earctx_cmdc_get_state(p_earc->tx_cmdc_map);
+ if (state != CMDC_ST_EARC)
+ return 0;
+
+ earctx_cmdc_set_latency(p_earc->tx_cmdc_map, &latency);
+
+ return 0;
+ }
+
+ int earctx_get_cds(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+ struct earc *p_earc = dev_get_drvdata(component->dev);
+ struct soc_bytes_ext *bytes_ext =
+ (struct soc_bytes_ext *)kcontrol->private_value;
+ u8 *value = (u8 *)ucontrol->value.bytes.data;
+ enum cmdc_st state;
+ u8 data[256];
+ int i;
+
+ if (!p_earc || IS_ERR(p_earc->tx_top_map))
+ return 0;
+
+ state = earctx_cmdc_get_state(p_earc->tx_cmdc_map);
+ if (state != CMDC_ST_EARC)
+ return 0;
+
+ earctx_cmdc_get_cds(p_earc->tx_cmdc_map, data);
+
+ for (i = 0; i < bytes_ext->max; i++)
+ *value++ = data[i];
+
+ return 0;
+ }
+
+ static const struct snd_kcontrol_new earc_controls[] = {
+ SOC_SINGLE_BOOL_EXT("HDMI ARC Switch",
+ 0,
+ earcrx_arc_get_enable,
+ earcrx_arc_set_enable),
+
+ SOC_ENUM_EXT("eARC_RX attended type",
+ attended_type_enum,
+ earcrx_get_attend_type,
+ earcrx_set_attend_type),
+
+ SOC_ENUM_EXT("eARC_TX attended type",
+ attended_type_enum,
+ earctx_get_attend_type,
+ earctx_set_attend_type),
+
+ SND_INT("eARC_RX Latency",
+ earcrx_get_latency,
+ earcrx_set_latency),
+
+ SND_INT("eARC_TX Latency",
+ earctx_get_latency,
+ earctx_set_latency),
+
+ SND_SOC_BYTES_EXT("eARC_RX CDS",
+ CDS_MAX_BYTES,
+ earcrx_get_cds,
+ earcrx_set_cds),
+
+ SND_SOC_BYTES_EXT("eARC_TX CDS",
+ CDS_MAX_BYTES,
+ earctx_get_cds,
+ NULL),
};
static const struct snd_soc_component_driver earc_component = {
bool nonpcm_flag;
struct extn_chipinfo *chipinfo;
-
+ struct snd_kcontrol *controls[DYNC_KCNTL_CNT];
};
#define PREALLOC_BUFFER (256 * 1024)
struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
- //resample_set(RESAMPLE_A, RATE_OFF, false);
++ return;
}
static int extn_dai_prepare(
#include "resample_hw.h"
#include "spdif.h"
+ #ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
+ #include <linux/platform_data/board_odroid.h>
++#else
++#define board_is_odroidn2() (0)
+ #endif
+
#define DRV_NAME "snd_spdif"
/* Debug by PTM when bringup */
CLOCK_COM_MUX(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(1)), 0x7, 24);
CLOCK_COM_DIV(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(1)), 0, 16);
CLOCK_COM_GATE(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(1)), 31);
++
+ /* mclk_pad0 */
+ CLOCK_COM_MUX(mclk_pad0, AUD_ADDR_OFFSET(EE_AUDIO_MST_PAD_CTRL0(1)), 0x7, 8);
+ CLOCK_COM_DIV(mclk_pad0, AUD_ADDR_OFFSET(EE_AUDIO_MST_PAD_CTRL0(1)), 0, 8);
+ CLOCK_COM_GATE(mclk_pad0, AUD_ADDR_OFFSET(EE_AUDIO_MST_PAD_CTRL0(1)), 15);
+ /* mclk_pad1 */
+ CLOCK_COM_MUX(mclk_pad1, AUD_ADDR_OFFSET(EE_AUDIO_MST_PAD_CTRL0(1)), 0x7, 24);
+ CLOCK_COM_DIV(mclk_pad1, AUD_ADDR_OFFSET(EE_AUDIO_MST_PAD_CTRL0(1)), 16, 8);
+ CLOCK_COM_GATE(mclk_pad1, AUD_ADDR_OFFSET(EE_AUDIO_MST_PAD_CTRL0(1)), 31);
+
/* spdifin */
CLOCK_COM_MUX(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 0x7, 24);
CLOCK_COM_DIV(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 0, 8);
* more details.
*
*/
--#define DEBUG
#undef pr_fmt
#define pr_fmt(fmt) "spdif_info: " fmt
return 0;
}
--
/* extern int set_i2s_iec958_samesource(int enable);
*
* the I2S hw and IEC958 PCM output initiation,958 initiation here,
projects / platform / kernel / linux-amlogic.git / commitdiff