ARM: uniphier: de-couple SG macros into base address and offset

The SG_* macros represent the address of SoC-glue registers.
For a planned new SoC, its base address will be changed.

Turn the SG_* macros into the offset from the base address.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/arm32/debug_ll.S b/arch/arm/mach-uniphier/arm32/debug_ll.S
index e56e1f6..c155246 100644 (file)
--- a/arch/arm/mach-uniphier/arm32/debug_ll.S
+++ b/arch/arm/mach-uniphier/arm32/debug_ll.S
@@ -22,7 +22,7 @@
 #define DIV_ROUND(x, d)                (((x) + ((d) / 2)) / (d))
 
 .macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
-       ldr     \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
+       ldr     \ra, =(SG_BASE + SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
        ldr     \rd, [\ra]
        and     \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
        orr     \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
@@ -30,7 +30,7 @@
 .endm
 
 ENTRY(debug_ll_init)
-       ldr             r0, =SG_REVISION
+       ldr             r0, =(SG_BASE + SG_REVISION)
        ldr             r1, [r0]
        and             r1, r1, #SG_REVISION_TYPE_MASK
        mov             r1, r1, lsr #SG_REVISION_TYPE_SHIFT
@@ -40,7 +40,7 @@ ENTRY(debug_ll_init)
        cmp             r1, #0x26
        bne             ld4_end
 
-       ldr             r0, =SG_IECTRL
+       ldr             r0, =(SG_BASE + SG_IECTRL)
        ldr             r1, [r0]
        orr             r1, r1, #1
        str             r1, [r0]
@@ -59,7 +59,7 @@ ld4_end:
 
        sg_set_pinsel   128, 0, 4, 8, r0, r1    @ TXD0 -> TXD0
 
-       ldr             r0, =SG_LOADPINCTRL
+       ldr             r0, =(SG_BASE + SG_LOADPINCTRL)
        mov             r1, #1
        str             r1, [r0]
 
@@ -78,7 +78,7 @@ pro4_end:
        cmp             r1, #0x29
        bne             sld8_end
 
-       ldr             r0, =SG_IECTRL
+       ldr             r0, =(SG_BASE + SG_IECTRL)
        ldr             r1, [r0]
        orr             r1, r1, #1
        str             r1, [r0]
@@ -100,7 +100,7 @@ sld8_end:
        sg_set_pinsel   51, 0, 4, 8, r0, r1     @ TXD2 -> TXD2
        sg_set_pinsel   53, 0, 4, 8, r0, r1     @ TXD3 -> TXD3
 
-       ldr             r0, =SG_LOADPINCTRL
+       ldr             r0, =(SG_BASE + SG_LOADPINCTRL)
        mov             r1, #1
        str             r1, [r0]
 
@@ -119,7 +119,7 @@ pro5_end:
        cmp             r1, #0x2E
        bne             pxs2_end
 
-       ldr             r0, =SG_IECTRL
+       ldr             r0, =(SG_BASE + SG_IECTRL)
        ldr             r1, [r0]
        orr             r1, r1, #1
        str             r1, [r0]
@@ -144,7 +144,7 @@ pxs2_end:
        cmp             r1, #0x2F
        bne             ld6b_end
 
-       ldr             r0, =SG_IECTRL
+       ldr             r0, =(SG_BASE + SG_IECTRL)
        ldr             r1, [r0]
        orr             r1, r1, #1
        str             r1, [r0]

diff --git a/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c b/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c
index 01a72c0..2edf66d 100644 (file)
--- a/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c
+++ b/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c
@@ -36,5 +36,5 @@ const unsigned uniphier_pxs3_boot_device_count =
 
 int uniphier_pxs3_boot_device_is_usb(u32 pinmon)
 {
-       return !!(readl(SG_PINMON2) & BIT(31));
+       return !!(readl(sg_base + SG_PINMON2) & BIT(31));
 }

diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c
index c9dfe13..83f8c6a 100644 (file)
--- a/arch/arm/mach-uniphier/boot-device/boot-device.c
+++ b/arch/arm/mach-uniphier/boot-device/boot-device.c
@@ -139,7 +139,7 @@ static unsigned int __uniphier_boot_device_raw(
        if (info->boot_is_swapped && info->boot_is_swapped())
                return BOOT_DEVICE_NOR;
 
-       pinmon = readl(SG_PINMON0);
+       pinmon = readl(sg_base + SG_PINMON0);
 
        if (info->boot_device_is_sd && info->boot_device_is_sd(pinmon))
                return BOOT_DEVICE_MMC2;
@@ -200,7 +200,7 @@ int uniphier_have_internal_stm(void)
 
 int uniphier_boot_from_backend(void)
 {
-       return !!(readl(SG_PINMON0) & BIT(27));
+       return !!(readl(sg_base + SG_PINMON0) & BIT(27));
 }
 
 #ifndef CONFIG_SPL_BUILD
@@ -226,7 +226,7 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
                printf("Boot Swap: %s\n",
                       info->boot_is_swapped() ? "ON" : "OFF");
 
-       pinmon = readl(SG_PINMON0);
+       pinmon = readl(sg_base + SG_PINMON0);
 
        if (info->boot_device_is_sd)
                printf("SD Boot:  %s\n",

diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c
index e997acf..0917b33 100644 (file)
--- a/arch/arm/mach-uniphier/clk/clk-ld11.c
+++ b/arch/arm/mach-uniphier/clk/clk-ld11.c
@@ -17,16 +17,16 @@
 void uniphier_ld11_clk_init(void)
 {
        /* if booted from a device other than USB, without stand-by MPU */
-       if ((readl(SG_PINMON0) & BIT(27)) &&
+       if ((readl(sg_base + SG_PINMON0) & BIT(27)) &&
            uniphier_boot_device_raw() != BOOT_DEVICE_USB) {
-               writel(1, SG_ETPHYPSHUT);
-               writel(1, SG_ETPHYCNT);
+               writel(1, sg_base + SG_ETPHYPSHUT);
+               writel(1, sg_base + SG_ETPHYCNT);
 
                udelay(1); /* wait for regulator level 1.1V -> 2.5V */
 
-               writel(3, SG_ETPHYCNT);
-               writel(3, SG_ETPHYPSHUT);
-               writel(7, SG_ETPHYCNT);
+               writel(3, sg_base + SG_ETPHYCNT);
+               writel(3, sg_base + SG_ETPHYPSHUT);
+               writel(7, sg_base + SG_ETPHYCNT);
        }
 
        /* TODO: use "mmc-pwrseq-emmc" */
@@ -37,7 +37,7 @@ void uniphier_ld11_clk_init(void)
                int ch;
 
                for (ch = 0; ch < 3; ch++) {
-                       void __iomem *phyctrl = (void __iomem *)SG_USBPHYCTRL;
+                       void __iomem *phyctrl = sg_base + SG_USBPHYCTRL;
 
                        writel(0x82280600, phyctrl + 8 * ch);
                        writel(0x00000106, phyctrl + 8 * ch + 4);

diff --git a/arch/arm/mach-uniphier/clk/pll-ld4.c b/arch/arm/mach-uniphier/clk/pll-ld4.c
index 6a145a3..34f1c9c 100644 (file)
--- a/arch/arm/mach-uniphier/clk/pll-ld4.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld4.c
@@ -16,7 +16,7 @@ static void upll_init(void)
 {
        u32 tmp, clk_mode_upll, clk_mode_axosel;
 
-       tmp = readl(SG_PINMON0);
+       tmp = readl(sg_base + SG_PINMON0);
        clk_mode_upll   = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
        clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
 
@@ -56,7 +56,7 @@ static void vpll_init(void)
 {
        u32 tmp, clk_mode_axosel;
 
-       tmp = readl(SG_PINMON0);
+       tmp = readl(sg_base + SG_PINMON0);
        clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
 
        /* set 1 to VPLA27WP and VPLA27WP */

diff --git a/arch/arm/mach-uniphier/clk/pll-pro4.c b/arch/arm/mach-uniphier/clk/pll-pro4.c
index 2ee2ed6..312a5fc 100644 (file)
--- a/arch/arm/mach-uniphier/clk/pll-pro4.c
+++ b/arch/arm/mach-uniphier/clk/pll-pro4.c
@@ -17,7 +17,7 @@ static void vpll_init(void)
        u32 tmp, clk_mode_axosel;
 
        /* Set VPLL27A &  VPLL27B */
-       tmp = readl(SG_PINMON0);
+       tmp = readl(sg_base + SG_PINMON0);
        clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
 
        /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */

diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c
index 0d66299..9017a24 100644 (file)
--- a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c
@@ -20,7 +20,7 @@ unsigned int uniphier_pro4_debug_uart_init(void)
        sg_set_iectrl(0);
        sg_set_pinsel(128, 0, 4, 8);    /* TXD0 -> TXD0 */
 
-       writel(1, SG_LOADPINCTRL);
+       writel(1, sg_base + SG_LOADPINCTRL);
 
        tmp = readl(SC_CLKCTRL);
        tmp |= SC_CLKCTRL_CEN_PERI;

diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c
index 1a0a942..8e4d15c 100644 (file)
--- a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c
@@ -23,7 +23,7 @@ unsigned int uniphier_pro5_debug_uart_init(void)
        sg_set_pinsel(51, 0, 4, 8);     /* TXD2 -> TXD2 */
        sg_set_pinsel(53, 0, 4, 8);     /* TXD3 -> TXD3 */
 
-       writel(1, SG_LOADPINCTRL);
+       writel(1, sg_base + SG_LOADPINCTRL);
 
        tmp = readl(SC_CLKCTRL);
        tmp |= SC_CLKCTRL_CEN_PERI;

diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.c b/arch/arm/mach-uniphier/debug-uart/debug-uart.c
index bc96b2e..a70ce59 100644 (file)
--- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c
@@ -32,7 +32,8 @@ void sg_set_pinsel(unsigned int pin, unsigned int muxval,
                   unsigned int mux_bits, unsigned int reg_stride)
 {
        unsigned int shift = pin * mux_bits % 32;
-       unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
+       void __iomem *reg = sg_base + SG_PINCTRL_BASE +
+                                       pin * mux_bits / 32 * reg_stride;
        u32 mask = (1U << mux_bits) - 1;
        u32 tmp;
 
@@ -45,7 +46,7 @@ void sg_set_pinsel(unsigned int pin, unsigned int muxval,
 void sg_set_iectrl(unsigned int pin)
 {
        unsigned int bit = pin % 32;
-       unsigned long reg = SG_IECTRL + pin / 32 * 4;
+       void __iomem *reg = sg_base + SG_IECTRL + pin / 32 * 4;
        u32 tmp;
 
        tmp = readl(reg);

diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c
index fa4b3e3..eca340b 100644 (file)
--- a/arch/arm/mach-uniphier/dram_init.c
+++ b/arch/arm/mach-uniphier/dram_init.c
@@ -85,7 +85,7 @@ static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map)
                return -EINVAL;
        }
 
-       val = readl(SG_MEMCONF);
+       val = readl(sg_base + SG_MEMCONF);
 
        /* set up ch0 */
        dram_map[0].base = CONFIG_SYS_SDRAM_BASE;

diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c
index 8105368..f69b489 100644 (file)
--- a/arch/arm/mach-uniphier/memconf.c
+++ b/arch/arm/mach-uniphier/memconf.c
@@ -140,7 +140,7 @@ static int __uniphier_memconf_init(const struct uniphier_board_data *bd,
        }
 
 out:
-       writel(val, SG_MEMCONF);
+       writel(val, sg_base + SG_MEMCONF);
 
        return 0;
 }

diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h
index 39ffed5..cba02d1 100644 (file)
--- a/arch/arm/mach-uniphier/sg-regs.h
+++ b/arch/arm/mach-uniphier/sg-regs.h
@@ -10,15 +10,19 @@
 #ifndef UNIPHIER_SG_REGS_H
 #define UNIPHIER_SG_REGS_H
 
+#ifndef __ASSEMBLY__
+#include <linux/compiler.h>
+#define sg_base                        ((void __iomem *)SG_BASE)
+#endif
+
 /* Base Address */
-#define SG_CTRL_BASE                   0x5f800000
-#define SG_DBG_BASE                    0x5f900000
+#define SG_BASE                        0x5f800000
 
 /* Revision */
-#define SG_REVISION                    (SG_CTRL_BASE | 0x0000)
+#define SG_REVISION            0x0000
 
 /* Memory Configuration */
-#define SG_MEMCONF                     (SG_CTRL_BASE | 0x0400)
+#define SG_MEMCONF             0x0400
 
 #define SG_MEMCONF_CH0_SZ_MASK         ((0x1 << 10) | (0x03 << 0))
 #define SG_MEMCONF_CH0_SZ_64M          ((0x0 << 10) | (0x01 << 0))
@@ -54,22 +58,22 @@
 
 #define SG_MEMCONF_SPARSEMEM           (0x1 << 4)
 
-#define SG_USBPHYCTRL                  (SG_CTRL_BASE | 0x500)
-#define SG_ETPHYPSHUT                  (SG_CTRL_BASE | 0x554)
-#define SG_ETPHYCNT                    (SG_CTRL_BASE | 0x550)
+#define SG_USBPHYCTRL          0x0500
+#define SG_ETPHYPSHUT          0x0554
+#define SG_ETPHYCNT            0x0550
 
 /* Pin Control */
-#define SG_PINCTRL_BASE                        (SG_CTRL_BASE | 0x1000)
+#define SG_PINCTRL_BASE                0x1000
 
 /* PH1-Pro4, PH1-Pro5 */
-#define SG_LOADPINCTRL                 (SG_CTRL_BASE | 0x1700)
+#define SG_LOADPINCTRL         0x1700
 
 /* Input Enable */
-#define SG_IECTRL                      (SG_CTRL_BASE | 0x1d00)
+#define SG_IECTRL              0x1d00
 
 /* Pin Monitor */
-#define SG_PINMON0                     (SG_DBG_BASE | 0x0100)
-#define SG_PINMON2                     (SG_DBG_BASE | 0x0108)
+#define SG_PINMON0             0x00100100
+#define SG_PINMON2             0x00100108
 
 #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK       (0x3 << 19)
 #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT    (0x0 << 19)

diff --git a/arch/arm/mach-uniphier/soc-info.c b/arch/arm/mach-uniphier/soc-info.c
index ce2d4b6..f021a8c 100644 (file)
--- a/arch/arm/mach-uniphier/soc-info.c
+++ b/arch/arm/mach-uniphier/soc-info.c
@@ -13,7 +13,7 @@
 static unsigned int __uniphier_get_revision_field(unsigned int mask,
                                                  unsigned int shift)
 {
-       u32 revision = readl(SG_REVISION);
+       u32 revision = readl(sg_base + SG_REVISION);
 
        return (revision >> shift) & mask;
 }