clk: samsung: exynos542x: add clock ID for G3D performance enhancement

This patch adds clock IDs for CLKMUX_ACLK_G3D and DPLL_CTRL,
and these IDs will be used by device tree to change G3D's parent
clock to DPLL(600MHz) instead of VPLL(400MHz).

Change-Id: Ia2c11331d42a73e095fd4c9deb64e9fb162c511d
Signed-off-by: Inki Dae <inki.dae@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index f356c39f47d7e0a7e5d5e43413c6ddee7c0a2872..7e6f8e6ae91cf8efe70cf6ddcfd69b36a4a971fc 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -657,7 +657,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
        MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
        MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
 
-       MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
+       MUX(CLK_MOUT_ACLK_G3D, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
 
        MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
                        SRC_TOP3, 0, 1),
@@ -715,7 +715,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
        MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
        MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
                        CLK_SET_RATE_PARENT, 0),
-       MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
+       MUX(CLK_MOUT_DPLL, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
        MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
 
        MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,

diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 2740ae0424a97836cc3212f773fea13f4e91a53d..9e58f980a573e695f5729ad87867ace058762911 100644 (file)
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -220,6 +220,8 @@
 #define CLK_MOUT_EPLL          657
 #define CLK_MOUT_MAU_EPLL      658
 #define CLK_MOUT_USER_MAU_EPLL 659
+#define CLK_MOUT_DPLL          660
+#define CLK_MOUT_ACLK_G3D      661
 
 /* divider clocks */
 #define CLK_DOUT_PIXEL         768