mtd: nand: pxa3xx_nand: sync pxa3xx_nand_set_sdr_timing()

Since the pxa3xx_nand driver was added there has been a discrepancy in
pxa3xx_nand_set_sdr_timing() around the setting of tWP_min and tRP_min.
This brings us into line with the current Linux code.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 6295886..8e450fb 100644 (file)
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -349,9 +349,9 @@ static void pxa3xx_nand_set_sdr_timing(struct pxa3xx_nand_host *host,
        u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000);
        u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000);
        u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000);
-       u32 tWP_min = DIV_ROUND_UP(t->tWC_min - tWH_min, 1000);
+       u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000);
        u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000);
-       u32 tRP_min = DIV_ROUND_UP(t->tRC_min - tREH_min, 1000);
+       u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000);
        u32 tR = chip->chip_delay * 1000;
        u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000);
        u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000);