;; Operand type. Used to default length attribute values
(define_attr "op_type"
- "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
+ "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
(const_string "RX"))
;; Insn are devide in two classes:
(eq_attr "op_type" "SSE") (const_string "agen")
(eq_attr "op_type" "RXE") (const_string "agen")
(eq_attr "op_type" "RSE") (const_string "agen")
- (eq_attr "op_type" "RIL") (const_string "agen")]
+ (eq_attr "op_type" "RIL") (const_string "agen")
+ (eq_attr "op_type" "RXY") (const_string "agen")
+ (eq_attr "op_type" "RSY") (const_string "agen")
+ (eq_attr "op_type" "SIY") (const_string "agen")]
(const_string "reg")))
;; Generic pipeline function unit.
(eq_attr "op_type" "SSE") (const_int 6)
(eq_attr "op_type" "RXE") (const_int 6)
(eq_attr "op_type" "RSE") (const_int 6)
- (eq_attr "op_type" "RIL") (const_int 6)]
+ (eq_attr "op_type" "RIL") (const_int 6)
+ (eq_attr "op_type" "RXY") (const_int 6)
+ (eq_attr "op_type" "RSY") (const_int 6)
+ (eq_attr "op_type" "SIY") (const_int 6)]
(const_int 4)))
;; Define attributes for `asm' insns.
(define_insn "*tmqi_ext"
[(set (reg 33)
- (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q")
- (match_operand:SI 1 "const_int_operand" "n")
- (match_operand:SI 2 "const_int_operand" "n"))
+ (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,S")
+ (match_operand:SI 1 "const_int_operand" "n,n")
+ (match_operand:SI 2 "const_int_operand" "n,n"))
(const_int 0)))]
"s390_match_ccmode(insn, CCTmode)
&& INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
operands[2] = GEN_INT (block << shift);
- return \"tm\\t%0,%b2\";
+ return which_alternative == 0 ? \"tm\\t%0,%b2\" : \"tmy\\t%0,%b2\";
}"
- [(set_attr "op_type" "SI")])
+ [(set_attr "op_type" "SI,SIY")])
; Test-under-Mask instructions
(define_insn "*tmdi_mem"
[(set (reg 33)
- (compare (and:DI (match_operand:DI 0 "memory_operand" "Q")
- (match_operand:DI 1 "immediate_operand" "n"))
- (match_operand:DI 2 "immediate_operand" "n")))]
+ (compare (and:DI (match_operand:DI 0 "memory_operand" "Q,S")
+ (match_operand:DI 1 "immediate_operand" "n,n"))
+ (match_operand:DI 2 "immediate_operand" "n,n")))]
"TARGET_64BIT
&& s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
&& s390_single_qi (operands[1], DImode, 0) >= 0"
operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part));
- return \"tm\\t%0,%b1\";
+ return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
}"
- [(set_attr "op_type" "SI")])
+ [(set_attr "op_type" "SI,SIY")])
(define_insn "*tmsi_mem"
[(set (reg 33)
- (compare (and:SI (match_operand:SI 0 "memory_operand" "Q")
- (match_operand:SI 1 "immediate_operand" "n"))
- (match_operand:SI 2 "immediate_operand" "n")))]
+ (compare (and:SI (match_operand:SI 0 "memory_operand" "Q,S")
+ (match_operand:SI 1 "immediate_operand" "n,n"))
+ (match_operand:SI 2 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
&& s390_single_qi (operands[1], SImode, 0) >= 0"
"*
operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part));
- return \"tm\\t%0,%b1\";
+ return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
}"
[(set_attr "op_type" "SI")])
(define_insn "*tmhi_mem"
[(set (reg 33)
- (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0)
- (match_operand:SI 1 "immediate_operand" "n"))
- (match_operand:SI 2 "immediate_operand" "n")))]
+ (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q,S") 0)
+ (match_operand:SI 1 "immediate_operand" "n,n"))
+ (match_operand:SI 2 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
&& s390_single_qi (operands[1], HImode, 0) >= 0"
"*
operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part));
- return \"tm\\t%0,%b1\";
+ return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
}"
[(set_attr "op_type" "SI")])
(define_insn "*tmqi_mem"
[(set (reg 33)
- (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0)
- (match_operand:SI 1 "immediate_operand" "n"))
- (match_operand:SI 2 "immediate_operand" "n")))]
+ (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q,S") 0)
+ (match_operand:SI 1 "immediate_operand" "n,n"))
+ (match_operand:SI 2 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
- "tm\\t%0,%b1"
- [(set_attr "op_type" "SI")])
+ "@
+ tm\\t%0,%b1
+ tmy\\t%0,%b1"
+ [(set_attr "op_type" "SI,SIY")])
(define_insn "*tmdi_reg"
[(set (reg 33)
(define_insn "*tstsi"
[(set (reg 33)
- (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
+ (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
(match_operand:SI 1 "const0_operand" "")))
- (set (match_operand:SI 2 "register_operand" "=d,d")
+ (set (match_operand:SI 2 "register_operand" "=d,d,d")
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
"@
ltr\\t%2,%0
- icm\\t%2,15,%0"
- [(set_attr "op_type" "RR,RS")])
+ icm\\t%2,15,%0
+ icmy\\t%2,15,%0"
+ [(set_attr "op_type" "RR,RS,RSY")])
(define_insn "*tstsi_cconly"
[(set (reg 33)
- (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
+ (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
(match_operand:SI 1 "const0_operand" "")))
- (clobber (match_scratch:SI 2 "=X,d"))]
+ (clobber (match_scratch:SI 2 "=X,d,d"))]
"s390_match_ccmode(insn, CCSmode)"
"@
ltr\\t%0,%0
- icm\\t%2,15,%0"
- [(set_attr "op_type" "RR,RS")])
+ icm\\t%2,15,%0
+ icmy\\t%2,15,%0"
+ [(set_attr "op_type" "RR,RS,RSY")])
(define_insn "*tstsi_cconly2"
[(set (reg 33)
(define_insn "*tsthiCCT"
[(set (reg 33)
- (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,d")
+ (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,?S,d")
(match_operand:HI 1 "const0_operand" "")))
- (set (match_operand:HI 2 "register_operand" "=d,0")
+ (set (match_operand:HI 2 "register_operand" "=d,d,0")
(match_dup 0))]
"s390_match_ccmode(insn, CCTmode)"
"@
icm\\t%2,3,%0
+ icmy\\t%2,3,%0
tml\\t%0,65535"
- [(set_attr "op_type" "RS,RI")])
+ [(set_attr "op_type" "RS,RSY,RI")])
(define_insn "*tsthiCCT_cconly"
[(set (reg 33)
- (compare (match_operand:HI 0 "nonimmediate_operand" "Q,d")
+ (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
(match_operand:HI 1 "const0_operand" "")))
- (clobber (match_scratch:HI 2 "=d,X"))]
+ (clobber (match_scratch:HI 2 "=d,d,X"))]
"s390_match_ccmode(insn, CCTmode)"
"@
icm\\t%2,3,%0
+ icmy\\t%2,3,%0
tml\\t%0,65535"
- [(set_attr "op_type" "RS,RI")])
+ [(set_attr "op_type" "RS,RSY,RI")])
(define_insn "*tsthi"
[(set (reg 33)
- (compare (match_operand:HI 0 "s_operand" "Q")
+ (compare (match_operand:HI 0 "s_operand" "Q,S")
(match_operand:HI 1 "const0_operand" "")))
- (set (match_operand:HI 2 "register_operand" "=d")
+ (set (match_operand:HI 2 "register_operand" "=d,d")
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
- "icm\\t%2,3,%0"
- [(set_attr "op_type" "RS")])
+ "@
+ icm\\t%2,3,%0
+ icmy\\t%2,3,%0"
+ [(set_attr "op_type" "RS,RSY")])
(define_insn "*tsthi_cconly"
[(set (reg 33)
- (compare (match_operand:HI 0 "s_operand" "Q")
+ (compare (match_operand:HI 0 "s_operand" "Q,S")
(match_operand:HI 1 "const0_operand" "")))
- (clobber (match_scratch:HI 2 "=d"))]
+ (clobber (match_scratch:HI 2 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)"
- "icm\\t%2,3,%0"
- [(set_attr "op_type" "RS")])
+ "@
+ icm\\t%2,3,%0
+ icmy\\t%2,3,%0"
+ [(set_attr "op_type" "RS,RSY")])
(define_insn "*tstqiCCT"
[(set (reg 33)
- (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d")
+ (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
(match_operand:QI 1 "const0_operand" "")))
- (set (match_operand:QI 2 "register_operand" "=d,0")
+ (set (match_operand:QI 2 "register_operand" "=d,d,0")
(match_dup 0))]
"s390_match_ccmode(insn, CCTmode)"
"@
icm\\t%2,1,%0
+ icmy\\t%2,1,%0
tml\\t%0,255"
- [(set_attr "op_type" "RS,RI")])
+ [(set_attr "op_type" "RS,RSY,RI")])
(define_insn "*tstqiCCT_cconly"
[(set (reg 33)
- (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d")
+ (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
(match_operand:QI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCTmode)"
"@
cli\\t%0,0
+ cliy\\t%0,0
tml\\t%0,255"
- [(set_attr "op_type" "SI,RI")])
+ [(set_attr "op_type" "SI,SIY,RI")])
(define_insn "*tstqi"
[(set (reg 33)
- (compare (match_operand:QI 0 "s_operand" "Q")
+ (compare (match_operand:QI 0 "s_operand" "Q,S")
(match_operand:QI 1 "const0_operand" "")))
- (set (match_operand:QI 2 "register_operand" "=d")
+ (set (match_operand:QI 2 "register_operand" "=d,d")
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
- "icm\\t%2,1,%0"
- [(set_attr "op_type" "RS")])
+ "@
+ icm\\t%2,1,%0
+ icmy\\t%2,1,%0"
+ [(set_attr "op_type" "RS,RSY")])
(define_insn "*tstqi_cconly"
[(set (reg 33)
- (compare (match_operand:QI 0 "s_operand" "Q")
+ (compare (match_operand:QI 0 "s_operand" "Q,S")
(match_operand:QI 1 "const0_operand" "")))
- (clobber (match_scratch:QI 2 "=d"))]
+ (clobber (match_scratch:QI 2 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)"
- "icm\\t%2,1,%0"
- [(set_attr "op_type" "RS")])
+ "@
+ icm\\t%2,1,%0
+ icmy\\t%2,1,%0"
+ [(set_attr "op_type" "RS,RSY")])
+
; Compare (signed) instructions
"@
cgfr\\t%0,%1
cgf\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpdi_ccs"
[(set (reg 33)
cgr\\t%0,%1
cghi\\t%0,%c1
cg\\t%0,%1"
- [(set_attr "op_type" "RRE,RI,RXE")])
+ [(set_attr "op_type" "RRE,RI,RXY")])
(define_insn "*cmpsi_ccs_sign"
[(set (reg 33)
- (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
- (match_operand:SI 0 "register_operand" "d")))]
+ (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
+ (match_operand:SI 0 "register_operand" "d,d")))]
"s390_match_ccmode(insn, CCSRmode)"
- "ch\\t%0,%1"
- [(set_attr "op_type" "RX")])
+ "@
+ ch\\t%0,%1
+ chy\\t%0,%1"
+ [(set_attr "op_type" "RX,RXY")])
(define_insn "*cmpsi_ccs"
[(set (reg 33)
- (compare (match_operand:SI 0 "register_operand" "d,d,d")
- (match_operand:SI 1 "general_operand" "d,K,m")))]
+ (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
+ (match_operand:SI 1 "general_operand" "d,K,R,T")))]
"s390_match_ccmode(insn, CCSmode)"
"@
cr\\t%0,%1
chi\\t%0,%c1
- c\\t%0,%1"
- [(set_attr "op_type" "RR,RI,RX")])
+ c\\t%0,%1
+ cy\\t%0,%1"
+ [(set_attr "op_type" "RR,RI,RX,RXY")])
; Compare (unsigned) instructions
"@
clgfr\\t%0,%1
clgf\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpdi_ccu"
[(set (reg 33)
"@
clgr\\t%0,%1
clg\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpsi_ccu"
[(set (reg 33)
- (compare (match_operand:SI 0 "register_operand" "d,d")
- (match_operand:SI 1 "general_operand" "d,m")))]
+ (compare (match_operand:SI 0 "register_operand" "d,d,d")
+ (match_operand:SI 1 "general_operand" "d,R,T")))]
"s390_match_ccmode(insn, CCUmode)"
"@
clr\\t%0,%1
- cl\\t%0,%1"
- [(set_attr "op_type" "RR,RX")])
+ cl\\t%0,%1
+ cly\\t%0,%1"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*cmphi_ccu"
[(set (reg 33)
- (compare (match_operand:HI 0 "register_operand" "d")
- (match_operand:HI 1 "s_imm_operand" "Q")))]
+ (compare (match_operand:HI 0 "register_operand" "d,d")
+ (match_operand:HI 1 "s_imm_operand" "Q,S")))]
"s390_match_ccmode(insn, CCUmode)"
- "clm\\t%0,3,%1"
- [(set_attr "op_type" "RS")])
+ "@
+ clm\\t%0,3,%1
+ clmy\\t%0,3,%1"
+ [(set_attr "op_type" "RS,RSY")])
(define_insn "*cmpqi_ccu"
[(set (reg 33)
- (compare (match_operand:QI 0 "register_operand" "d")
- (match_operand:QI 1 "s_imm_operand" "Q")))]
+ (compare (match_operand:QI 0 "register_operand" "d,d")
+ (match_operand:QI 1 "s_imm_operand" "Q,S")))]
"s390_match_ccmode(insn, CCUmode)"
- "clm\\t%0,1,%1"
- [(set_attr "op_type" "RS")])
+ "@
+ clm\\t%0,1,%1
+ clmy\\t%0,1,%1"
+ [(set_attr "op_type" "RS,RSY")])
(define_insn "*cli"
[(set (reg 33)
- (compare (match_operand:QI 0 "memory_operand" "Q")
- (match_operand:QI 1 "immediate_operand" "n")))]
+ (compare (match_operand:QI 0 "memory_operand" "Q,S")
+ (match_operand:QI 1 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, CCUmode)"
- "cli\\t%0,%b1"
- [(set_attr "op_type" "SI")])
+ "@
+ cli\\t%0,%b1
+ cliy\\t%0,%b1"
+ [(set_attr "op_type" "SI,SIY")])
(define_insn "*cmpdi_ccu_mem"
[(set (reg 33)
(define_insn "*cmpdf_ccs"
[(set (reg 33)
(compare (match_operand:DF 0 "register_operand" "f,f")
- (match_operand:DF 1 "general_operand" "f,m")))]
+ (match_operand:DF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
cdbr\\t%0,%1
(define_insn "*cmpdf_ccs_ibm"
[(set (reg 33)
(compare (match_operand:DF 0 "register_operand" "f,f")
- (match_operand:DF 1 "general_operand" "f,m")))]
+ (match_operand:DF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
cdr\\t%0,%1
(define_insn "*cmpsf_ccs"
[(set (reg 33)
(compare (match_operand:SF 0 "register_operand" "f,f")
- (match_operand:SF 1 "general_operand" "f,m")))]
+ (match_operand:SF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
cebr\\t%0,%1
(define_insn "*cmpsf_ccs"
[(set (reg 33)
(compare (match_operand:SF 0 "register_operand" "f,f")
- (match_operand:SF 1 "general_operand" "f,m")))]
+ (match_operand:SF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
cer\\t%0,%1
;
(define_insn "movti"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,o,Q")
- (match_operand:TI 1 "general_operand" "Q,d,dKm,d,Q"))]
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
+ (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
"TARGET_64BIT"
"@
lmg\\t%0,%N0,%1
#
#
mvc\\t%O0(16,%R0),%1"
- [(set_attr "op_type" "RSE,RSE,NN,NN,SS")
+ [(set_attr "op_type" "RSY,RSY,NN,NN,SS")
(set_attr "type" "lm,stm,*,*,cs")])
(define_split
}"
[(set_attr "op_type" "RI")])
+(define_insn "*movdi_lay"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (match_operand:DI 1 "address_operand" "p"))]
+ "TARGET_64BIT
+ && TARGET_LONG_DISPLACEMENT
+ && GET_CODE (operands[1]) == CONST_INT
+ && !FP_REG_P (operands[0])"
+ "lay\\t%0,%a1"
+ [(set_attr "op_type" "RXY")
+ (set_attr "type" "la")])
+
(define_insn "*movdi_larl"
[(set (match_operand:DI 0 "register_operand" "=d")
(match_operand:DI 1 "larl_operand" "X"))]
(set_attr "type" "larl")])
(define_insn "*movdi_64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,?Q")
- (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,?Q"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!*f,!R,!T,?Q")
+ (match_operand:DI 1 "general_operand" "d,m,d,*f,R,T,*f,*f,?Q"))]
"TARGET_64BIT"
"@
lgr\\t%0,%1
stg\\t%1,%0
ldr\\t%0,%1
ld\\t%0,%1
+ ldy\\t%0,%1
std\\t%1,%0
+ stdy\\t%1,%0
mvc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "RRE,RXE,RXE,RR,RX,RX,SS")
- (set_attr "type" "lr,load,store,floadd,floadd,fstored,cs")])
+ [(set_attr "op_type" "RRE,RXY,RXY,RR,RX,RXY,RX,RXY,SS")
+ (set_attr "type" "lr,load,store,floadd,floadd,floadd,fstored,fstored,cs")])
(define_insn "*movdi_31"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!m,Q")
- (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f,Q"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
+ (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
"!TARGET_64BIT"
"@
lm\\t%0,%N0,%1
#
ldr\\t%0,%1
ld\\t%0,%1
+ ldy\\t%0,%1
std\\t%1,%0
+ stdy\\t%1,%0
mvc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
- (set_attr "type" "lm,stm,*,*,floadd,floadd,fstored,cs")])
+ [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RXY,RX,RXY,SS")
+ (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,cs")])
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
}"
[(set_attr "op_type" "RI")])
+(define_insn "*movsi_lay"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (match_operand:SI 1 "address_operand" "p"))]
+ "TARGET_LONG_DISPLACEMENT
+ && GET_CODE (operands[1]) == CONST_INT
+ && !FP_REG_P (operands[0])"
+ "lay\\t%0,%a1"
+ [(set_attr "op_type" "RXY")
+ (set_attr "type" "la")])
+
(define_insn "*movsi"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,?Q")
- (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,?Q"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q")
+ (match_operand:SI 1 "general_operand" "d,R,T,d,d,*f,R,T,*f,*f,?Q"))]
""
"@
lr\\t%0,%1
l\\t%0,%1
+ ly\\t%0,%1
st\\t%1,%0
+ sty\\t%1,%0
ler\\t%0,%1
le\\t%0,%1
+ ley\\t%0,%1
ste\\t%1,%0
+ stey\\t%1,%0
mvc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
- (set_attr "type" "lr,load,store,floads,floads,fstores,cs")])
+ [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
+ (set_attr "type" "lr,load,load,store,store,floads,floads,floads,fstores,fstores,cs")])
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
;
(define_insn "movhi"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,?Q")
- (match_operand:HI 1 "general_operand" "d,n,m,d,?Q"))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
+ (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
""
"@
lr\\t%0,%1
lhi\\t%0,%h1
lh\\t%0,%1
+ lhy\\t%0,%1
sth\\t%1,%0
+ sthy\\t%1,%0
mvc\\t%O0(2,%R0),%1"
- [(set_attr "op_type" "RR,RI,RX,RX,SS")
- (set_attr "type" "lr,*,*,store,cs")])
+ [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
+ (set_attr "type" "lr,*,*,*,store,store,cs")])
(define_peephole2
[(set (match_operand:HI 0 "register_operand" "")
;
(define_insn "movqi_64"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,?Q")
- (match_operand:QI 1 "general_operand" "d,n,m,d,n,?Q"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,R,T,Q,S,?Q")
+ (match_operand:QI 1 "general_operand" "d,n,m,d,d,n,n,?Q"))]
"TARGET_64BIT"
"@
lr\\t%0,%1
lhi\\t%0,%b1
llgc\\t%0,%1
stc\\t%1,%0
+ stcy\\t%1,%0
mvi\\t%0,%b1
+ mviy\\t%0,%b1
mvc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
- (set_attr "type" "lr,*,*,store,store,cs")])
+ [(set_attr "op_type" "RR,RI,RXY,RX,RXY,SI,SIY,SS")
+ (set_attr "type" "lr,*,*,store,store,store,store,cs")])
(define_insn "movqi"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,?Q")
- (match_operand:QI 1 "general_operand" "d,n,m,d,n,?Q"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
+ (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
""
"@
lr\\t%0,%1
lhi\\t%0,%b1
ic\\t%0,%1
+ icy\\t%0,%1
stc\\t%1,%0
+ stcy\\t%1,%0
mvi\\t%0,%b1
+ mviy\\t%0,%b1
mvc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")
- (set_attr "type" "lr,*,*,store,store,cs")])
+ [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
+ (set_attr "type" "lr,*,*,*,store,store,store,store,cs")])
(define_peephole2
[(set (match_operand:QI 0 "nonimmediate_operand" "")
;
(define_insn "*movstrictqi"
- [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
- (match_operand:QI 1 "memory_operand" "m"))]
+ [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
+ (match_operand:QI 1 "memory_operand" "R,T"))]
""
- "ic\\t%0,%1"
- [(set_attr "op_type" "RX")])
+ "@
+ ic\\t%0,%1
+ icy\\t%0,%1"
+ [(set_attr "op_type" "RX,RXY")])
;
; movstricthi instruction pattern(s).
;
(define_insn "*movstricthi"
- [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
- (match_operand:HI 1 "s_imm_operand" "Q"))
+ [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
+ (match_operand:HI 1 "s_imm_operand" "Q,S"))
(clobber (reg:CC 33))]
""
- "icm\\t%0,3,%1"
- [(set_attr "op_type" "RS")])
-
+ "@
+ icm\\t%0,3,%1
+ icmy\\t%0,3,%1"
+ [(set_attr "op_type" "RS,RSY")])
;
; movstrictsi instruction pattern(s).
;
(define_insn "movstrictsi"
- [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
- (match_operand:SI 1 "general_operand" "d,m"))]
+ [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d"))
+ (match_operand:SI 1 "general_operand" "d,R,T"))]
"TARGET_64BIT"
"@
lr\\t%0,%1
- l\\t%0,%1"
- [(set_attr "op_type" "RR,RS")
- (set_attr "type" "lr,load")])
-
+ l\\t%0,%1
+ ly\\t%0,%1"
+ [(set_attr "op_type" "RR,RX,RXY")
+ (set_attr "type" "lr,load,load")])
;
; movdf instruction pattern(s).
}")
(define_insn "*movdf_64"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,?Q")
- (match_operand:DF 1 "general_operand" "f,m,f,d,m,d,?Q"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q")
+ (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))]
"TARGET_64BIT"
"@
ldr\\t%0,%1
ld\\t%0,%1
+ ldy\\t%0,%1
std\\t%1,%0
+ stdy\\t%1,%0
lgr\\t%0,%1
lg\\t%0,%1
stg\\t%1,%0
mvc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "RR,RX,RX,RRE,RXE,RXE,SS")
- (set_attr "type" "floadd,floadd,fstored,lr,load,store,cs")])
+ [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
+ (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,cs")])
(define_insn "*movdf_31"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,o,Q")
- (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d,Q"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
+ (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))]
"!TARGET_64BIT"
"@
ldr\\t%0,%1
ld\\t%0,%1
+ ldy\\t%0,%1
std\\t%1,%0
+ stdy\\t%1,%0
lm\\t%0,%N0,%1
stm\\t%1,%N1,%0
#
#
mvc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
- (set_attr "type" "floadd,floadd,fstored,lm,stm,*,*,cs")])
+ [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,NN,NN,SS")
+ (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,cs")])
(define_split
[(set (match_operand:DF 0 "nonimmediate_operand" "")
}")
(define_insn "*movsf"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,?Q")
- (match_operand:SF 1 "general_operand" "f,m,f,d,m,d,?Q"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q")
+ (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))]
""
"@
ler\\t%0,%1
le\\t%0,%1
+ ley\\t%0,%1
ste\\t%1,%0
+ stey\\t%1,%0
lr\\t%0,%1
l\\t%0,%1
+ ly\\t%0,%1
st\\t%1,%0
+ sty\\t%1,%0
mvc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
- (set_attr "type" "floads,floads,fstores,lr,load,store,cs")])
+ [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
+ (set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")])
;
; load_multiple pattern(s).
(define_insn "*load_multiple_di"
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:DI 1 "register_operand" "=r")
- (match_operand:DI 2 "s_operand" "Q"))])]
+ (match_operand:DI 2 "s_operand" "QS"))])]
""
"*
{
int words = XVECLEN (operands[0], 0);
-
- if (XVECLEN (operands[0], 0) == 1)
- return \"lg\\t%1,0(%2)\";
-
operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
- return \"lmg\\t%1,%0,%2\";
+ return \"lmg\\t%1,%0,%2\";
}"
- [(set_attr "op_type" "RXE")
+ [(set_attr "op_type" "RSY")
(set_attr "type" "lm")])
(define_insn "*load_multiple_si"
[(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 1 "register_operand" "=r")
- (match_operand:SI 2 "s_operand" "Q"))])]
+ [(set (match_operand:SI 1 "register_operand" "=r,r")
+ (match_operand:SI 2 "s_operand" "Q,S"))])]
""
"*
{
int words = XVECLEN (operands[0], 0);
-
- if (XVECLEN (operands[0], 0) == 1)
- return \"l\\t%1,0(%2)\";
-
operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
- return \"lm\\t%1,%0,%2\";
+ return which_alternative == 0 ? \"lm\\t%1,%0,%2\" : \"lmy\\t%1,%0,%2\";
}"
- [(set_attr "op_type" "RXE")
+ [(set_attr "op_type" "RS,RSY")
(set_attr "type" "lm")])
;
(define_insn "*store_multiple_di"
[(match_parallel 0 "store_multiple_operation"
- [(set (match_operand:DI 1 "s_operand" "=Q")
+ [(set (match_operand:DI 1 "s_operand" "=QS")
(match_operand:DI 2 "register_operand" "r"))])]
""
"*
{
int words = XVECLEN (operands[0], 0);
-
- if (XVECLEN (operands[0], 0) == 1)
- return \"stg\\t%1,0(%2)\";
-
operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
- return \"stmg\\t%2,%0,%1\";
+ return \"stmg\\t%2,%0,%1\";
}"
- [(set_attr "op_type" "RXE")
+ [(set_attr "op_type" "RSY")
(set_attr "type" "stm")])
(define_insn "*store_multiple_si"
[(match_parallel 0 "store_multiple_operation"
- [(set (match_operand:SI 1 "s_operand" "=Q")
- (match_operand:SI 2 "register_operand" "r"))])]
+ [(set (match_operand:SI 1 "s_operand" "=Q,S")
+ (match_operand:SI 2 "register_operand" "r,r"))])]
""
"*
{
int words = XVECLEN (operands[0], 0);
-
- if (XVECLEN (operands[0], 0) == 1)
- return \"st\\t%1,0(%2)\";
-
operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
- return \"stm\\t%2,%0,%1\";
+ return which_alternative == 0 ? \"stm\\t%2,%0,%1\" : \"stmy\\t%2,%0,%1\";
}"
- [(set_attr "op_type" "RXE")
+ [(set_attr "op_type" "RS,RSY")
(set_attr "type" "stm")])
;;
;;
(define_insn "*sethighqisi"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10))
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] 10))
(clobber (reg:CC 33))]
""
- "icm\\t%0,8,%1"
- [(set_attr "op_type" "RS")])
+ "@
+ icm\\t%0,8,%1
+ icmy\\t%0,8,%1"
+ [(set_attr "op_type" "RS,RSY")])
(define_insn "*sethighhisi"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10))
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] 10))
(clobber (reg:CC 33))]
""
- "icm\\t%0,12,%1"
- [(set_attr "op_type" "RS")])
+ "@
+ icm\\t%0,12,%1
+ icmy\\t%0,12,%1"
+ [(set_attr "op_type" "RS,RSY")])
(define_insn "*sethighqidi_64"
[(set (match_operand:DI 0 "register_operand" "=d")
- (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
+ (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] 10))
(clobber (reg:CC 33))]
"TARGET_64BIT"
"icmh\\t%0,8,%1"
- [(set_attr "op_type" "RSE")])
+ [(set_attr "op_type" "RSY")])
(define_insn "*sethighqidi_31"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] 10))
(clobber (reg:CC 33))]
"!TARGET_64BIT"
- "icm\\t%0,8,%1"
- [(set_attr "op_type" "RS")])
+ "@
+ icm\\t%0,8,%1
+ icmy\\t%0,8,%1"
+ [(set_attr "op_type" "RS,RSY")])
(define_insn_and_split "*extractqi"
[(set (match_operand:SI 0 "register_operand" "=d")
"@
lgfr\\t%0,%1
lgf\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
;
; extendhidi2 instruction pattern(s).
(sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"lgh\\t%0,%1"
- [(set_attr "op_type" "RXE")])
+ [(set_attr "op_type" "RXY")])
;
; extendqidi2 instruction pattern(s).
}
")
+(define_insn "*extendqidi2"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
+ "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
+ "lgb\\t%0,%1"
+ [(set_attr "op_type" "RXY")])
+
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
- "TARGET_64BIT && !reload_completed"
+ "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT && !reload_completed"
[(parallel
[(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
(clobber (reg:CC 33))])
")
(define_insn "*extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
""
- "lh\\t%0,%1"
- [(set_attr "op_type" "RX")])
+ "@
+ lh\\t%0,%1
+ lhy\\t%0,%1"
+ [(set_attr "op_type" "RX,RXY")])
;
; extendqisi2 instruction pattern(s).
}
")
+(define_insn "*extendqisi2"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
+ "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
+ "lb\\t%0,%1"
+ [(set_attr "op_type" "RXY")])
+
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
- "!reload_completed"
+ "(!TARGET_64BIT || !TARGET_LONG_DISPLACEMENT) && !reload_completed"
[(parallel
[(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
(clobber (reg:CC 33))])
"@
llgfr\\t%0,%1
llgf\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
;
; zero_extendhidi2 instruction pattern(s).
(zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgh\\t%0,%1"
- [(set_attr "op_type" "RXE")])
+ [(set_attr "op_type" "RXY")])
;
; zero_extendqidi2 instruction pattern(s)
(zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
- [(set_attr "op_type" "RXE")])
+ [(set_attr "op_type" "RXY")])
;
; zero_extendhisi2 instruction pattern(s).
(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgh\\t%0,%1"
- [(set_attr "op_type" "RXE")])
+ [(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendhisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
- (zero_extend:SI (match_operand:HI 1 "memory_operand" "Q")))
+ (zero_extend:SI (match_operand:HI 1 "memory_operand" "QS")))
(clobber (reg:CC 33))]
"!TARGET_64BIT"
"#"
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
- [(set_attr "op_type" "RXE")])
+ [(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendqisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
- [(set_attr "op_type" "RXE")])
+ [(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendqihi2_31"
[(set (match_operand:HI 0 "register_operand" "=&d")
(define_insn "truncdfsf2_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
- (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
+ (float_truncate:SF (match_operand:DF 1 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
lrer\\t%0,%1
(define_insn "extendsfdf2_ieee"
[(set (match_operand:DF 0 "register_operand" "=f,f")
- (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
+ (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
ldebr\\t%0,%1
(define_insn "extendsfdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
- (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
+ (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
"@
agfr\\t%0,%2
agf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero_cc"
[(set (reg 33)
"@
algfr\\t%0,%2
algf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero_cconly"
[(set (reg 33)
"@
algfr\\t%0,%2
algf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
"@
algfr\\t%0,%2
algf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_imm_cc"
[(set (reg 33)
"@
algr\\t%0,%2
alg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly"
[(set (reg 33)
"@
algr\\t%0,%2
alg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly2"
[(set (reg 33)
"@
algr\\t%0,%2
alg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
agr\\t%0,%2
aghi\\t%0,%h2
ag\\t%0,%2"
- [(set_attr "op_type" "RRE,RI,RXE")])
+ [(set_attr "op_type" "RRE,RI,RXY")])
(define_insn_and_split "*adddi3_31"
[(set (match_operand:DI 0 "register_operand" "=&d")
"")
(define_insn "*la_64"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (match_operand:QI 1 "address_operand" "p"))]
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (match_operand:QI 1 "address_operand" "U,W"))]
"TARGET_64BIT"
- "la\\t%0,%a1"
- [(set_attr "op_type" "RX")
+ "@
+ la\\t%0,%a1
+ lay\\t%0,%a1"
+ [(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")])
(define_peephole2
(define_insn "*addsi3_carry1_cc"
[(set (reg 33)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
- al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ al\\t%0,%2
+ aly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry1_cconly"
[(set (reg 33)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
- (clobber (match_scratch:SI 0 "=d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
- al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ al\\t%0,%2
+ aly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry2_cc"
[(set (reg 33)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 2)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
- al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ al\\t%0,%2
+ aly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry2_cconly"
[(set (reg 33)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 2)))
- (clobber (match_scratch:SI 0 "=d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
- al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ al\\t%0,%2
+ aly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cc"
[(set (reg 33)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)"
"@
alr\\t%0,%2
- al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ al\\t%0,%2
+ aly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cconly"
[(set (reg 33)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCLmode)"
"@
alr\\t%0,%2
- al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ al\\t%0,%2
+ aly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cconly2"
[(set (reg 33)
- (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
- (clobber (match_scratch:SI 0 "=d,d"))]
+ (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCLmode)"
"@
alr\\t%0,%2
- al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ al\\t%0,%2
+ aly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_sign"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (plus:SI (match_operand:SI 1 "register_operand" "0")
- (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (plus:SI (match_operand:SI 1 "register_operand" "0,0")
+ (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
(clobber (reg:CC 33))]
""
- "ah\\t%0,%2"
- [(set_attr "op_type" "RX")])
+ "@
+ ah\\t%0,%2
+ ahy\\t%0,%2"
+ [(set_attr "op_type" "RX,RXY")])
(define_insn "*addsi3_sub"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (plus:SI (match_operand:SI 1 "register_operand" "0")
- (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (plus:SI (match_operand:SI 1 "register_operand" "0,0")
+ (subreg:SI (match_operand:HI 2 "memory_operand" "R,T") 0)))
(clobber (reg:CC 33))]
""
- "ah\\t%0,%2"
- [(set_attr "op_type" "RX")])
+ "@
+ ah\\t%0,%2
+ ahy\\t%0,%2"
+ [(set_attr "op_type" "RX,RXY")])
(define_insn "addsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d,d")
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:SI 2 "general_operand" "d,K,m")))
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:SI 2 "general_operand" "d,K,R,T")))
(clobber (reg:CC 33))]
""
"@
ar\\t%0,%2
ahi\\t%0,%h2
- a\\t%0,%2"
- [(set_attr "op_type" "RR,RI,RX")])
+ a\\t%0,%2
+ ay\\t%0,%2"
+ [(set_attr "op_type" "RR,RI,RX,RXY")])
(define_insn "*la_31"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (match_operand:QI 1 "address_operand" "p"))]
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (match_operand:QI 1 "address_operand" "U,W"))]
"!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
- "la\\t%0,%a1"
- [(set_attr "op_type" "RX")
+ "@
+ la\\t%0,%a1
+ lay\\t%0,%a1"
+ [(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")])
(define_peephole2
"")
(define_insn "*la_31_and"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (and:SI (match_operand:QI 1 "address_operand" "p")
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (and:SI (match_operand:QI 1 "address_operand" "U,W")
(const_int 2147483647)))]
"!TARGET_64BIT"
- "la\\t%0,%a1"
- [(set_attr "op_type" "RX")
+ "@
+ la\\t%0,%a1
+ lay\\t%0,%a1"
+ [(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")])
(define_insn_and_split "*la_31_and_cc"
(set_attr "type" "la")])
(define_insn "force_la_31"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (match_operand:QI 1 "address_operand" "p"))
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (match_operand:QI 1 "address_operand" "U,W"))
(use (const_int 0))]
"!TARGET_64BIT"
- "la\\t%0,%a1"
+ "@
+ la\\t%0,%a1
+ lay\\t%0,%a1"
[(set_attr "op_type" "RX")
(set_attr "type" "la")])
[(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
(define_insn "*adddf3"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
(define_insn "*adddf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
[(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
(define_insn "*addsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
(define_insn "*addsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
"@
sgfr\\t%0,%2
sgf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero_cc"
[(set (reg 33)
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero_cconly"
[(set (reg 33)
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cc"
[(set (reg 33)
"@
slgr\\t%0,%2
slg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cconly"
[(set (reg 33)
"@
slgr\\t%0,%2
slg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(define_insn "*subsi3_borrow_cc"
[(set (reg 33)
- (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d")
(minus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCL2mode)"
"@
slr\\t%0,%2
- sl\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ sl\\t%0,%2
+ sly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_borrow_cconly"
[(set (reg 33)
- (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
- (clobber (match_scratch:SI 0 "=d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCL2mode)"
"@
slr\\t%0,%2
- sl\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ sl\\t%0,%2
+ sly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXE")])
(define_insn "*subsi3_cc"
[(set (reg 33)
- (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d")
(minus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCLmode)"
"@
slr\\t%0,%2
- sl\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ sl\\t%0,%2
+ sly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_cconly"
[(set (reg 33)
- (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCLmode)"
"@
slr\\t%0,%2
- sl\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ sl\\t%0,%2
+ sly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_sign"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (minus:SI (match_operand:SI 1 "register_operand" "0")
- (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (minus:SI (match_operand:SI 1 "register_operand" "0,0")
+ (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
(clobber (reg:CC 33))]
""
- "sh\\t%0,%2"
- [(set_attr "op_type" "RX")])
+ "@
+ sh\\t%0,%2
+ shy\\t%0,%2"
+ [(set_attr "op_type" "RX,RXY")])
(define_insn "*subsi3_sub"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (minus:SI (match_operand:SI 1 "register_operand" "0")
- (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (minus:SI (match_operand:SI 1 "register_operand" "0,0")
+ (subreg:SI (match_operand:HI 2 "memory_operand" "R,T") 0)))
(clobber (reg:CC 33))]
""
- "sh\\t%0,%2"
- [(set_attr "op_type" "RX")])
+ "@
+ sh\\t%0,%2
+ shy\\t%0,%2"
+ [(set_attr "op_type" "RX,RXY")])
(define_insn "subsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (minus:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "general_operand" "d,m")))
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d")
+ (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (reg:CC 33))]
""
"@
sr\\t%0,%2
- s\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ s\\t%0,%2
+ sy\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
;
[(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
(define_insn "*subdf3"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
(define_insn "*subdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
[(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
(define_insn "*subsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
(define_insn "*subsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
"@
msgfr\\t%0,%2
msgf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
+ [(set_attr "op_type" "RRE,RXY")
(set_attr "type" "imul")])
msgr\\t%0,%2
mghi\\t%0,%h2
msg\\t%0,%2"
- [(set_attr "op_type" "RRE,RI,RXE")
+ [(set_attr "op_type" "RRE,RI,RXY")
(set_attr "type" "imul")])
;
;
(define_insn "mulsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d,d")
- (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:SI 2 "general_operand" "d,K,m")))]
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
+ (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:SI 2 "general_operand" "d,K,R,T")))]
""
"@
msr\\t%0,%2
mhi\\t%0,%h2
- ms\\t%0,%2"
- [(set_attr "op_type" "RRE,RI,RX")
+ ms\\t%0,%2
+ msy\\t%0,%2"
+ [(set_attr "op_type" "RRE,RI,RX,RXY")
(set_attr "type" "imul")])
;
(mult:DI (sign_extend:DI
(truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
(sign_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
+ (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
"!TARGET_64BIT"
"@
mr\\t%0,%2
[(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f")
(mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
(define_insn "*muldf3"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
(define_insn "*muldf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
[(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f")
(mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
(define_insn "*mulsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
(define_insn "*mulsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
"@
dsgr\\t%0,%2
dsg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
+ [(set_attr "op_type" "RRE,RXY")
(set_attr "type" "idiv")])
(define_insn "divmodtisi3"
"@
dsgfr\\t%0,%2
dsgf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
+ [(set_attr "op_type" "RRE,RXY")
(set_attr "type" "idiv")])
;
"@
dlgr\\t%0,%2
dlg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
+ [(set_attr "op_type" "RRE,RXY")
(set_attr "type" "idiv")])
;
(truncate:SI
(div:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
+ (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
(ashift:DI
(zero_extend:DI
(truncate:SI
[(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f")
(div:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
(define_insn "*divdf3"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(div:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
(define_insn "*divdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(div:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
[(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
(define_insn "*divsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
(define_insn "*divsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
"@
ngr\\t%0,%2
ng\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*anddi3_cconly"
[(set (reg 33)
"@
ngr\\t%0,%2
ng\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*anddi3_ni"
[(set (match_operand:DI 0 "register_operand" "=d")
"@
ngr\\t%0,%2
ng\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*anddi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
(define_insn "*andsi3_cc"
[(set (reg 33)
- (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d")
(and:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
nr\\t%0,%2
- n\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ n\\t%0,%2
+ ny\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*andsi3_cconly"
[(set (reg 33)
- (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
nr\\t%0,%2
- n\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ n\\t%0,%2
+ ny\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*andsi3_ni"
[(set (match_operand:SI 0 "register_operand" "=d")
[(set_attr "op_type" "RI")])
(define_insn "andsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m")))
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (reg:CC 33))]
""
"@
nr\\t%0,%2
- n\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ n\\t%0,%2
+ ny\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*andsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
[(set_attr "op_type" "RR")])
(define_insn "*andqi3_ss"
- [(set (match_operand:QI 0 "s_operand" "=Q,Q")
+ [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
(and:QI (match_dup 0)
- (match_operand:QI 1 "s_imm_operand" "n,Q")))
+ (match_operand:QI 1 "s_imm_operand" "n,n,Q")))
(clobber (reg:CC 33))]
""
"@
ni\\t%0,%b1
+ niy\\t%0,%b1
nc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SI,SS")])
+ [(set_attr "op_type" "SI,SIY,SS")])
(define_insn "*andqi3_ss_inv"
- [(set (match_operand:QI 0 "s_operand" "=Q,Q")
- (and:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
+ [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
+ (and:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q")
(match_dup 0)))
(clobber (reg:CC 33))]
""
"@
ni\\t%0,%b1
+ niy\\t%0,%b1
nc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SI,SS")])
+ [(set_attr "op_type" "SI,SIY,SS")])
;;
"@
ogr\\t%0,%2
og\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*iordi3_cconly"
[(set (reg 33)
"@
ogr\\t%0,%2
og\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*iordi3_oi"
[(set (match_operand:DI 0 "register_operand" "=d")
"@
ogr\\t%0,%2
og\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*iordi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
(define_insn "*iorsi3_cc"
[(set (reg 33)
- (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d")
(ior:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
or\\t%0,%2
- o\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ o\\t%0,%2
+ oy\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*iorsi3_cconly"
[(set (reg 33)
- (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
or\\t%0,%2
- o\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ o\\t%0,%2
+ oy\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*iorsi3_oi"
[(set (match_operand:SI 0 "register_operand" "=d")
[(set_attr "op_type" "RI")])
(define_insn "iorsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m")))
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d")
+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (reg:CC 33))]
""
"@
or\\t%0,%2
- o\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ o\\t%0,%2
+ oy\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*iorsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
[(set_attr "op_type" "RR")])
(define_insn "*iorqi3_ss"
- [(set (match_operand:QI 0 "s_operand" "=Q,Q")
+ [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
(ior:QI (match_dup 0)
- (match_operand:QI 1 "s_imm_operand" "n,Q")))
+ (match_operand:QI 1 "s_imm_operand" "n,n,Q")))
(clobber (reg:CC 33))]
""
"@
oi\\t%0,%b1
+ oiy\\t%0,%b1
oc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SI,SS")])
+ [(set_attr "op_type" "SI,SIY,SS")])
(define_insn "*iorqi3_ss_inv"
- [(set (match_operand:QI 0 "s_operand" "=Q,Q")
- (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
+ [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
+ (ior:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q")
(match_dup 0)))
(clobber (reg:CC 33))]
""
"@
oi\\t%0,%b1
+ oiy\\t%0,%b1
oc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SI,SS")])
+ [(set_attr "op_type" "SI,SIY,SS")])
;;
"@
xgr\\t%0,%2
xg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*xordi3_cconly"
[(set (reg 33)
"@
xgr\\t%0,%2
xr\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "xordi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
"@
xgr\\t%0,%2
xg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*xordi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
(define_insn "*xorsi3_cc"
[(set (reg 33)
- (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d")
(xor:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
xr\\t%0,%2
- x\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ x\\t%0,%2
+ xy\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*xorsi3_cconly"
[(set (reg 33)
- (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
xr\\t%0,%2
- x\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ x\\t%0,%2
+ xy\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "xorsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m")))
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d")
+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (reg:CC 33))]
""
"@
xr\\t%0,%2
- x\\t%0,%2"
- [(set_attr "op_type" "RR,RX")])
+ x\\t%0,%2
+ xy\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*xorsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
(clobber (reg:CC 33))]
""
"xr\\t%0,%2"
- [(set_attr "op_type" "RR")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR")])
(define_insn "*xorhi3_ss"
[(set (match_operand:HI 0 "s_operand" "=Q")
[(set_attr "op_type" "RR")])
(define_insn "*xorqi3_ss"
- [(set (match_operand:QI 0 "s_operand" "=Q,Q")
+ [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
(xor:QI (match_dup 0)
- (match_operand:QI 1 "s_imm_operand" "n,Q")))
+ (match_operand:QI 1 "s_imm_operand" "n,n,Q")))
(clobber (reg:CC 33))]
""
"@
xi\\t%0,%b1
+ xiy\\t%0,%b1
xc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SI,SS")])
+ [(set_attr "op_type" "SI,SIY,SS")])
(define_insn "*xorqi3_ss_inv"
- [(set (match_operand:QI 0 "s_operand" "=Q,Q")
- (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
+ [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
+ (xor:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q")
(match_dup 0)))
(clobber (reg:CC 33))]
""
"@
xi\\t%0,%b1
+ xiy\\t%0,%b1
xc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SI,SS")])
+ [(set_attr "op_type" "SI,SIY,SS")])
;;
(define_insn "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "=f,f")
- (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
+ (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sqdbr\\t%0,%1
sqdb\\t%0,%1"
- [(set_attr "op_type" "RRE,RSE")
- (set_attr "type" "fsqrtd")])
+ [(set_attr "op_type" "RRE,RXE")])
;
; sqrtsf2 instruction pattern(s).
(define_insn "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "=f,f")
- (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
+ (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sqebr\\t%0,%1
sqeb\\t%0,%1"
- [(set_attr "op_type" "RRE,RSE")
- (set_attr "type" "fsqrts")])
+ [(set_attr "op_type" "RRE,RXE")])
;;
;;- One complement instructions.
[(set (pc)
(if_then_else
(match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
- (match_operand 0 "address_operand" "p")
+ (match_operand 0 "address_operand" "U")
(pc)))]
""
"*
(if_then_else
(match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
(pc)
- (match_operand 0 "address_operand" "p")))]
+ (match_operand 0 "address_operand" "U")))]
""
"*
{
(if_then_else
(ne (match_operand:SI 1 "register_operand" "d,d")
(const_int 1))
- (match_operand 0 "address_operand" "p,p")
+ (match_operand 0 "address_operand" "U,U")
(pc)))
(set (match_operand:SI 2 "register_operand" "=1,?*m*d")
(plus:SI (match_dup 1) (const_int -1)))
(if_then_else
(ne (match_operand:DI 1 "register_operand" "d,d")
(const_int 1))
- (match_operand 0 "address_operand" "p,p")
+ (match_operand 0 "address_operand" "U,U")
(pc)))
(set (match_operand:DI 2 "register_operand" "=1,?*m*d")
(plus:DI (match_dup 1) (const_int -1)))
;
(define_insn "indirect_jump"
- [(set (pc) (match_operand 0 "address_operand" "p"))]
+ [(set (pc) (match_operand 0 "address_operand" "U"))]
""
"*
{
;
(define_insn "casesi_jump"
- [(set (pc) (match_operand 0 "address_operand" "p"))
+ [(set (pc) (match_operand 0 "address_operand" "U"))
(use (label_ref (match_operand 1 "" "")))]
""
"*
(set_attr "atype" "agen")])
(define_insn "bas_64"
- [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
+ [(call (mem:QI (match_operand:QI 0 "address_operand" "U"))
(match_operand:SI 1 "const_int_operand" "n"))
(clobber (match_operand:DI 2 "register_operand" "=r"))]
"TARGET_64BIT"
(set_attr "type" "jsr")])
(define_insn "bas_31"
- [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
+ [(call (mem:QI (match_operand:QI 0 "address_operand" "U"))
(match_operand:SI 1 "const_int_operand" "n"))
(clobber (match_operand:SI 2 "register_operand" "=r"))]
"!TARGET_64BIT"
(define_insn "bas_r_64"
[(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
+ (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:DI 3 "register_operand" "=r"))]
"TARGET_64BIT"
(define_insn "bas_r_31"
[(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
+ (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:SI 3 "register_operand" "=r"))]
"!TARGET_64BIT"
[(set_attr "op_type" "RXE")])
(define_insn "*tls_load_31"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
(match_operand:SI 2 "" "")]
UNSPEC_TLS_LOAD))]
"!TARGET_64BIT"
- "l\\t%0,%1%J2"
- [(set_attr "op_type" "RX")])
+ "@
+ l\\t%0,%1%J2
+ ly\\t%0,%1%J2"
+ [(set_attr "op_type" "RX,RXY")])
(define_expand "call_value_tls"
[(set (match_operand 0 "" "")
(define_insn "bas_tls_64"
[(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
+ (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:DI 3 "register_operand" "=r"))
(use (match_operand:DI 4 "" ""))]
(define_insn "bas_tls_31"
[(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
+ (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:SI 3 "register_operand" "=r"))
(use (match_operand:SI 4 "" ""))]