/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
-#define s5j_dmasetup(a, b) if((b)->setup) (b)->setup(a, b);
+#define s5j_dmasetup(a, b) if ((b)->setup) { (b)->setup(a, b) };
/************************************************************************************
* Public Types
configs.address = ALC5658_ADDR;
configs.addrlen = CONFIG_ALC5658_I2C_ADDRLEN;
- i2c = &i2c_alc5658;
+ i2c = &i2c_alc5658;
for (i = 0; i < sizeof(codec_init_script) / sizeof(t_codec_init_script_entry); i++) {
ret = i2c->modify(codec_init_script[i].addr, codec_init_script[i].val, 0xFFFF);
* Pre-processor Definitions
************************************************************************************/
-#define S5J_I2S_MAXPERCLK 26000000 /* Maximum peripheral clock frequency */
+#define S5J_I2S_MAXPERCLK 26000000 /* Maximum peripheral clock frequency */
/* I2S Register Offsets *************************************************************/
-#define S5J_I2S_CON 0x0000 /* I2S interface control */
-#define S5J_I2S_MOD 0x0004 /* I2S interface mode */
-#define S5J_I2S_FIC 0x0008 /* I2S interface TxFIFO and Rx FIFO control */
-#define S5J_I2S_PSR 0x000C /* I2S interface clock divider control */
-#define S5J_I2S_TXD 0x0010 /* I2S interface transmit sound data */
-#define S5J_I2S_RXD 0x0014 /* I2S interface receive data */
-#define S5J_I2S_FICS 0x0018 /* I2S interface secondary TxFIFO_S Control */
-#define S5J_I2S_TXDS 0x001C /* I2S interface transmit secondary data */
-#define S5J_I2S_VER 0x0044 /* I2S version */
+#define S5J_I2S_CON 0x0000 /* I2S interface control */
+#define S5J_I2S_MOD 0x0004 /* I2S interface mode */
+#define S5J_I2S_FIC 0x0008 /* I2S interface TxFIFO and Rx FIFO control */
+#define S5J_I2S_PSR 0x000C /* I2S interface clock divider control */
+#define S5J_I2S_TXD 0x0010 /* I2S interface transmit sound data */
+#define S5J_I2S_RXD 0x0014 /* I2S interface receive data */
+#define S5J_I2S_FICS 0x0018 /* I2S interface secondary TxFIFO_S Control */
+#define S5J_I2S_TXDS 0x001C /* I2S interface transmit secondary data */
+#define S5J_I2S_VER 0x0044 /* I2S version */
/* I2S Register Bit Definitions *****************************************************/
-#define I2S_CR_SW_RST_SHIFT (31)
-#define I2S_CR_SW_RST_MASK (1 << I2S_CR_SW_RST_SHIFT)
-#define I2S_CR_SW_RST_RELEASE (1 << I2S_CR_SW_RST_SHIFT)
-
-#define I2S_CR_FRXOFSTATUS (1 << 26)
-#define I2S_CR_FRXOFINTEN (1 << 25)
-#define I2S_CR_FTXSURSTATUS (1 << 24)
-#define I2S_CR_FTXSURINTEN (1 << 23)
-#define I2S_CR_FTXSEMPT (1 << 22)
-#define I2S_CR_FTXSFULL (1 << 21)
-#define I2S_CR_TXSDMAPAUSE (1 << 20)
-#define I2S_CR_TXSDMACTIVE (1 << 18)
-#define I2S_CR_FTXURSTATUS (1 << 17)
-#define I2S_CR_FTXURINTEN (1 << 16)
-#define I2S_CR_LRI (1 << 11)
-#define I2S_CR_FTX0EMPT (1 << 10)
-#define I2S_CR_FRXEMPT (1 << 9)
-#define I2S_CR_FTX0FULL (1 << 8)
-#define I2S_CR_FRXFULL (1 << 7)
-#define I2S_CR_TXDMAPAUSE (1 << 6)
-#define I2S_CR_RXDMAPAUSE (1 << 5)
-#define I2S_CR_TXCHPAUSE (1 << 4)
-#define I2S_CR_RXCHPAUSE (1 << 3)
-#define I2S_CR_TXDMACTIVE (1 << 2)
-#define I2S_CR_RXDMACTIVE (1 << 1)
-#define I2S_CR_I2SACTIVE (1 << 0)
+#define I2S_CR_SW_RST_SHIFT (31)
+#define I2S_CR_SW_RST_MASK (1 << I2S_CR_SW_RST_SHIFT)
+#define I2S_CR_SW_RST_RELEASE (1 << I2S_CR_SW_RST_SHIFT)
+
+#define I2S_CR_FRXOFSTATUS (1 << 26)
+#define I2S_CR_FRXOFINTEN (1 << 25)
+#define I2S_CR_FTXSURSTATUS (1 << 24)
+#define I2S_CR_FTXSURINTEN (1 << 23)
+#define I2S_CR_FTXSEMPT (1 << 22)
+#define I2S_CR_FTXSFULL (1 << 21)
+#define I2S_CR_TXSDMAPAUSE (1 << 20)
+#define I2S_CR_TXSDMACTIVE (1 << 18)
+#define I2S_CR_FTXURSTATUS (1 << 17)
+#define I2S_CR_FTXURINTEN (1 << 16)
+#define I2S_CR_LRI (1 << 11)
+#define I2S_CR_FTX0EMPT (1 << 10)
+#define I2S_CR_FRXEMPT (1 << 9)
+#define I2S_CR_FTX0FULL (1 << 8)
+#define I2S_CR_FRXFULL (1 << 7)
+#define I2S_CR_TXDMAPAUSE (1 << 6)
+#define I2S_CR_RXDMAPAUSE (1 << 5)
+#define I2S_CR_TXCHPAUSE (1 << 4)
+#define I2S_CR_RXCHPAUSE (1 << 3)
+#define I2S_CR_TXDMACTIVE (1 << 2)
+#define I2S_CR_RXDMACTIVE (1 << 1)
+#define I2S_CR_I2SACTIVE (1 << 0)
/* MOD register */
-#define I2S_MOD_OP_CLK_MASK (3 << 30)
-#define I2S_MOD_OP_CLK_PCLK (3 << 30)
-
-#define BLC_8BIT (1)
-#define BLC_16BIT (0)
-#define BLC_24BIT (2)
-
-#define I2S_MOD_BLC_S_MASK (3 << 26)
-#define I2S_MOD_BLC_S(x) ((x & 3) << 26)
-#define I2S_MOD_BLC_P_MASK (3 << 24)
-#define I2S_MOD_BLC_P(x) ((x & 3) << 24)
-#define I2S_MOD_LRP (1 << 15)
-#define I2S_MOD_BLC_MASK (3 << 13)
-#define I2S_MOD_BLC(x) ((x & 3) << 13)
-#define I2S_MOD_CDCLKCON_IN (1 << 12)
-#define I2S_MOD_MSS_SLAVE (1 << 11)
-#define I2S_MOD_RCLKSRC (1 << 10)
-
-#define TXR_TX 0
-#define TXR_RX 1
-#define TXR_TXRX 2
-#define I2S_MOD_TXR_MASK (3 << 8)
-#define I2S_MOD_TXR(x) ((x & 3) << 8)
-
-#define I2S_MOD_SDF_MASK (3 << 6)
-#define I2S_MOD_SDF_I2S (0 << 6)
-#define I2S_MOD_SDF_MSB_Jstf (1 << 6)
-#define I2S_MOD_SDF_LSB_Jstf (2 << 6)
-
-#define RFS_256 (0x0)
-#define RFS_192 (0x7)
-
-#define BFS_64 (0x4)
-
-#define I2S_MOD_RFS_MASK (7 << 3)
-#define I2S_MOD_RFS(x) ((x & 7) << 3)
-#define I2S_MOD_BFS_MASK (7 << 0)
-#define I2S_MOD_BFS(x) ((x & 7) << 0)
+#define I2S_MOD_OP_CLK_MASK (3 << 30)
+#define I2S_MOD_OP_CLK_PCLK (3 << 30)
+
+#define BLC_8BIT (1)
+#define BLC_16BIT (0)
+#define BLC_24BIT (2)
+
+#define I2S_MOD_BLC_S_MASK (3 << 26)
+#define I2S_MOD_BLC_S(x) ((x & 3) << 26)
+#define I2S_MOD_BLC_P_MASK (3 << 24)
+#define I2S_MOD_BLC_P(x) ((x & 3) << 24)
+#define I2S_MOD_LRP (1 << 15)
+#define I2S_MOD_BLC_MASK (3 << 13)
+#define I2S_MOD_BLC(x) ((x & 3) << 13)
+#define I2S_MOD_CDCLKCON_IN (1 << 12)
+#define I2S_MOD_MSS_SLAVE (1 << 11)
+#define I2S_MOD_RCLKSRC (1 << 10)
+
+#define TXR_TX 0
+#define TXR_RX 1
+#define TXR_TXRX 2
+#define I2S_MOD_TXR_MASK (3 << 8)
+#define I2S_MOD_TXR(x) ((x & 3) << 8)
+
+#define I2S_MOD_SDF_MASK (3 << 6)
+#define I2S_MOD_SDF_I2S (0 << 6)
+#define I2S_MOD_SDF_MSB_Jstf (1 << 6)
+#define I2S_MOD_SDF_LSB_Jstf (2 << 6)
+
+#define RFS_256 (0x0)
+#define RFS_192 (0x7)
+
+#define BFS_64 (0x4)
+
+#define I2S_MOD_RFS_MASK (7 << 3)
+#define I2S_MOD_RFS(x) ((x & 7) << 3)
+#define I2S_MOD_BFS_MASK (7 << 0)
+#define I2S_MOD_BFS(x) ((x & 7) << 0)
/* FIC register */
-#define I2S_FIC_TFLUSH (1 << 15)
-#define I2S_FIC_FTX0CNT (0x7F << 8)
-#define I2S_FIC_RFLUSH (1 << 7)
-#define I2S_FIC_FRXCNT (0x7F << 0)
-
-#define I2S_PSR_PSREN (1 << 15)
-#define I2S_PSR_PSVAL (0x3F << 8)
-
-#define I2S_FICS_TXDMA_TH_EN (1 << 31)
-#define I2S_FICS_TXDMA_TH (0x3F << 24)
-#define I2S_FICS_RXDMA_TH_EN (1 << 23)
-#define I2S_FICS_RXDMA_TH (0x3F << 16)
-#define I2S_FICS_TFLUSHS (1 << 15)
-#define I2S_FICS_FTXSCNT (0x7F << 8)
+#define I2S_FIC_TFLUSH (1 << 15)
+#define I2S_FIC_FTX0CNT (0x7F << 8)
+#define I2S_FIC_RFLUSH (1 << 7)
+#define I2S_FIC_FRXCNT (0x7F << 0)
+
+#define I2S_PSR_PSREN (1 << 15)
+#define I2S_PSR_PSVAL (0x3F << 8)
+
+#define I2S_FICS_TXDMA_TH_EN (1 << 31)
+#define I2S_FICS_TXDMA_TH (0x3F << 24)
+#define I2S_FICS_RXDMA_TH_EN (1 << 23)
+#define I2S_FICS_RXDMA_TH (0x3F << 16)
+#define I2S_FICS_TFLUSHS (1 << 15)
+#define I2S_FICS_FTXSCNT (0x7F << 8)
#endif /* __ARCH_ARM_SRC_S5JT200_CHIP_S5J_I2S_H */
#define DMAC_FSRC (0x034)
#define DMAC_FTRD (0x038)
-#define DMAC_CH_FTR(n) 0x040 + 0x04*(n)
-#define DMAC_CH_CSR(n) (u32)(0x100 + 0x08*(n))
-#define DMAC_CH_CPC(n) 0x104 + 0x08*(n)
-#define DMAC_CH_SAR(n) 0x400 + 0x20*(n)
-#define DMAC_CH_DAR(n) 0x404 + 0x20*(n)
-#define DMAC_CH_CCR(n) 0x408 + 0x20*(n)
-#define DMAC_CH_LC0(n) 0x40C + 0x20*(n)
-#define DMAC_CH_LC1(n) 0x410 + 0x20*(n)
+#define DMAC_CH_FTR(n) 0x040 + 0x04 * (n)
+#define DMAC_CH_CSR(n) (u32)(0x100 + 0x08 * (n))
+#define DMAC_CH_CPC(n) 0x104 + 0x08 * (n)
+#define DMAC_CH_SAR(n) 0x400 + 0x20 * (n)
+#define DMAC_CH_DAR(n) 0x404 + 0x20 * (n)
+#define DMAC_CH_CCR(n) 0x408 + 0x20 * (n)
+#define DMAC_CH_LC0(n) 0x40C + 0x20 * (n)
+#define DMAC_CH_LC1(n) 0x410 + 0x20 * (n)
#define DMAC_DBG_STATUS 0xD00
#define DMAC_DBG_CMD 0xD04
/* CCR BITFIELDS */
-#define NOSWAP (0)
-#define ENDIAN_SWAP_SIZE_MASK (7 << 28)
-#define ENDIAN_SWAP_SIZE(x) ((x & 7) << 28)
+#define NOSWAP (0)
+#define ENDIAN_SWAP_SIZE_MASK (7 << 28)
+#define ENDIAN_SWAP_SIZE(x) ((x & 7) << 28)
-#define AWCACHE0 (1)
-#define AWCACHE1 (2)
-#define AWCACHE2 (4)
-#define DST_CACHE_CTRL_MASK (7 << 25)
-#define DST_CACHE_CTRL(x) ((x & 7) << 25)
+#define AWCACHE0 (1)
+#define AWCACHE1 (2)
+#define AWCACHE2 (4)
+#define DST_CACHE_CTRL_MASK (7 << 25)
+#define DST_CACHE_CTRL(x) ((x & 7) << 25)
-#define AWPROT0 (1)
-#define AWPROT1 (2)
-#define AWPROT2 (4)
-#define DST_PROT_CTRL_MASK (7 << 22)
-#define DST_PROT_CTRL(x) ((x & 7) << 22)
+#define AWPROT0 (1)
+#define AWPROT1 (2)
+#define AWPROT2 (4)
+#define DST_PROT_CTRL_MASK (7 << 22)
+#define DST_PROT_CTRL(x) ((x & 7) << 22)
/* Burst Len absolute value */
-#define DST_BURST_LEN_MASK (0xf << 18)
-#define DST_BURST_LEN(x) (((x - 1) & 0xf) << 18)
-
-#define BS_1 0
-#define BS_2 1
-#define BS_4 2
-#define BS_8 3
-#define DST_BURST_SIZE_MASK (7 << 15)
-#define DST_BURST_SIZE(x) ((x & 7) << 15)
-
-#define DST_INC (1 << 14)
-
-#define ARCACHE0 (1)
-#define ARCACHE1 (2)
-#define ARCACHE2 (4)
-#define SRC_CACHE_CTRL_MASK (7 << 11)
-#define SRC_CACHE_CTRL(x) ((x & 7) << 11)
-
-#define ARPROT0 (1)
-#define ARPROT1 (2)
-#define ARPROT2 (4)
-#define SRC_PROT_CTRL_MASK (7 << 8)
-#define SRC_PROT_CTRL(x) ((x & 7) << 8)
+#define DST_BURST_LEN_MASK (0xf << 18)
+#define DST_BURST_LEN(x) (((x - 1) & 0xf) << 18)
+
+#define BS_1 0
+#define BS_2 1
+#define BS_4 2
+#define BS_8 3
+#define DST_BURST_SIZE_MASK (7 << 15)
+#define DST_BURST_SIZE(x) ((x & 7) << 15)
+
+#define DST_INC (1 << 14)
+
+#define ARCACHE0 (1)
+#define ARCACHE1 (2)
+#define ARCACHE2 (4)
+#define SRC_CACHE_CTRL_MASK (7 << 11)
+#define SRC_CACHE_CTRL(x) ((x & 7) << 11)
+
+#define ARPROT0 (1)
+#define ARPROT1 (2)
+#define ARPROT2 (4)
+#define SRC_PROT_CTRL_MASK (7 << 8)
+#define SRC_PROT_CTRL(x) ((x & 7) << 8)
/* Burst Len absolute value */
-#define SRC_BURST_LENGTH_MASK (0xf << 4)
-#define SRC_BURST_LENGTH(x) (((x - 1) & 0xf) << 4)
+#define SRC_BURST_LENGTH_MASK (0xf << 4)
+#define SRC_BURST_LENGTH(x) (((x - 1) & 0xf) << 4)
/* Burst Size absolute value */
-#define SRC_BURST_SIZE_MASK (7 << 1)
-#define SRC_BURST_SIZE(x) ((x & 7) << 1)
+#define SRC_BURST_SIZE_MASK (7 << 1)
+#define SRC_BURST_SIZE(x) ((x & 7) << 1)
-#define SRC_INC (1 << 0)
+#define SRC_INC (1 << 0)
-#define LC0 0x0
-#define LC0_END 0x10
-#define LC1 0x2
-#define LC1_END 0x14
+#define LC0 0x0
+#define LC0_END 0x10
+#define LC1 0x2
+#define LC1_END 0x14
#define CCR_M2M_DFLT (ENDIAN_SWAP_SIZE(NOSWAP) | \
DST_CACHE_CTRL(AWCACHE1) | \
SRC_PROT_CTRL(2) | \
DST_PROT_CTRL(2))
-#define DMA_MC_4B_SET(a, b) (*(unsigned int *)(a) = (unsigned int)(b))
-#define DMA_MC_1B_SET(a, b) (*(char *)(a) = (char)(b))
-#define DMA_MC_EV_SET(a, b) (*(char *)(a) = (char)(b << 3))
+#define DMA_MC_4B_SET(a, b) (*(unsigned int *)(a) = (unsigned int)(b))
+#define DMA_MC_1B_SET(a, b) (*(char *)(a) = (char)(b))
+#define DMA_MC_EV_SET(a, b) (*(char *)(a) = (char)(b << 3))
#define DMA_NOP (0x18)
************************************************************************************/
/* Microcode functions */
-inline static int DMA_Encode_DMAMOV(char *base, void **reg_addr, DMA_INST_REG rd)
+static inline int DMA_Encode_DMAMOV(char *base, void **reg_addr, DMA_INST_REG rd)
{
rd &= 0x07;
return 6;
}
-inline static int DMA_Encode_DMALP(char *base, DMA_LC lc, void **iter)
+static inline int DMA_Encode_DMALP(char *base, DMA_LC lc, void **iter)
{
base[0] = 0x20 | lc;
return 2;
}
-inline static int DMA_Encode_DMALPEND(char *base, u8 CTRL, char backwards_jump)
+static inline int DMA_Encode_DMALPEND(char *base, u8 CTRL, char backwards_jump)
{
base[0] = 0x28 | CTRL;
base[1] = backwards_jump;
return 2;
}
-inline static int DMA_Encode_DMALD(char *base, u8 CTRL)
+static inline int DMA_Encode_DMALD(char *base, u8 CTRL)
{
base[0] = 0x04 | CTRL;
return 1;
}
-inline static int DMA_Encode_DMALDP(char *base, u8 CTRL, DMA_REQ_MAP periph)
+static inline int DMA_Encode_DMALDP(char *base, u8 CTRL, DMA_REQ_MAP periph)
{
base[0] = 0x25 | CTRL;
base[1] = periph << 3;
return 2;
}
-inline static int DMA_Encode_DMAST(char *base, u8 CTRL)
+static inline int DMA_Encode_DMAST(char *base, u8 CTRL)
{
base[0] = 0x08 | CTRL;
return 1;
}
-inline static int DMA_Encode_DMASTP(char *base, u8 CTRL, DMA_REQ_MAP periph)
+static inline int DMA_Encode_DMASTP(char *base, u8 CTRL, DMA_REQ_MAP periph)
{
base[0] = 0x29 | CTRL;
base[1] = periph << 3;
return 2;
}
-inline static int DMA_Encode_DMAWFP(char *base, u8 CTRL, DMA_REQ_MAP periph)
+static inline int DMA_Encode_DMAWFP(char *base, u8 CTRL, DMA_REQ_MAP periph)
{
base[0] = 0x30 | CTRL;
base[1] = periph << 3;
return 2;
}
-inline static int DMA_Encode_DMASEV(char *base, void **event_num)
+static inline int DMA_Encode_DMASEV(char *base, void **event_num)
{
base[0] = 0x34;
base[1] = 0xe;
return 2;
}
-inline static int DMA_Encode_DMAEND(char *base)
+static inline int DMA_Encode_DMAEND(char *base)
{
base[0] = 0x00;
return 1;
}
-inline static int DMA_Encode_DMAFLUSHP(char *base, u8 periph)
+static inline int DMA_Encode_DMAFLUSHP(char *base, u8 periph)
{
base[0] = 0x35;
base[1] = periph << 3;
return 2;
}
-inline static int DMA_Encode_DMAWMB(char *base)
+static inline int DMA_Encode_DMAWMB(char *base)
{
base[0] = 0x13;
return 1;
#undef CONFIG_I2S_TXS_DMACH
#undef CONFIG_I2S_RX_DMACH
-#define CONFIG_I2S_TXP_DMACH 0
-#define CONFIG_I2S_TXS_DMACH 1
-#define CONFIG_I2S_RX_DMACH 2
+#define CONFIG_I2S_TXP_DMACH 0
+#define CONFIG_I2S_TXS_DMACH 1
+#define CONFIG_I2S_RX_DMACH 2
#endif
#if defined(I2S_HAVE_RX) || defined(I2S_HAVE_TX_P) || defined(I2S_HAVE_TX_S)
uint8_t txp_datalen; /* Data width (8, 16, or 32) */
uint8_t txs_datalen; /* Data width (8, 16, or 32) */
- uint8_t rxenab: 1; /* True: RX transfers enabled */
- uint8_t txpenab: 1; /* True: TX primary transfers enabled */
- uint8_t txsenab: 1; /* True: TX secondary transfers enabled */
+ uint8_t rxenab:1; /* True: RX transfers enabled */
+ uint8_t txpenab:1; /* True: TX primary transfers enabled */
+ uint8_t txsenab:1; /* True: TX secondary transfers enabled */
uint32_t samplerate; /* Not actually needed in slave mode */
/* Register helpers */
#ifdef CONFIG_S5J_I2S_DUMPBUFFERS
-#define i2s_init_buffer(b,s) memset(b, 0x55, s);
-#define i2s_dump_buffer(m,b,s) lib_dumpbuffer(m,b,s)
+#define i2s_init_buffer(b, s) memset(b, 0x55, s);
+#define i2s_dump_buffer(m, b, s) lib_dumpbuffer(m, b, s)
#else
-#define i2s_init_buffer(b,s)
-#define i2s_dump_buffer(m,b,s)
+#define i2s_init_buffer(b, s)
+#define i2s_dump_buffer(m, b, s)
#endif
/* Semaphore helpers */
// Hash Function
-#define SHA1 (0x1)
-#define SHA2 (0x2)
-#define SHA3 (0x3)
-
-#define HASH160 (0x1)
-#define HASH224 (0x2)
-#define HASH256 (0x3)
-#define HASH384 (0x4)
-#define HASH512 (0x5)
-#define HMAC (0x1)
-
-#define SHA1_160 (((SHA1<<4)|(HASH160))<<8) //0x00001100
-#define SHA2_224 (((SHA2<<4)|(HASH224))<<8) //0x00002200
-#define SHA2_256 (((SHA2<<4)|(HASH256))<<8) //0x00002300
-#define SHA2_384 (((SHA2<<4)|(HASH384))<<8) //0x00002400
-#define SHA2_512 (((SHA2<<4)|(HASH512))<<8) //0x00002500
-#define SHA3_224 (((SHA3<<4)|(HASH224))<<8) //0x00003200
-#define SHA3_256 (((SHA3<<4)|(HASH256))<<8) //0x00003300
-#define SHA3_384 (((SHA3<<4)|(HASH384))<<8) //0x00003400
-#define SHA3_512 (((SHA3<<4)|(HASH512))<<8) //0x00003500
-
-#define HMAC_SHA1_160 ((((SHA1<<4)|(HASH160))<<8) | (HMAC)<<16) //0x00011100
-#define HMAC_SHA2_256 ((((SHA2<<4)|(HASH256))<<8) | (HMAC)<<16) //0x00012300
-#define HMAC_SHA2_384 ((((SHA2<<4)|(HASH384))<<8) | (HMAC)<<16) //0x00012400
-#define HMAC_SHA2_512 ((((SHA2<<4)|(HASH512))<<8) | (HMAC)<<16) //0x00012500
+#define SHA1 (0x1)
+#define SHA2 (0x2)
+#define SHA3 (0x3)
+
+#define HASH160 (0x1)
+#define HASH224 (0x2)
+#define HASH256 (0x3)
+#define HASH384 (0x4)
+#define HASH512 (0x5)
+#define HMAC (0x1)
+
+#define SHA1_160 (((SHA1 << 4) | (HASH160)) << 8) //0x00001100
+#define SHA2_224 (((SHA2 << 4) | (HASH224)) << 8) //0x00002200
+#define SHA2_256 (((SHA2 << 4) | (HASH256)) << 8) //0x00002300
+#define SHA2_384 (((SHA2 << 4) | (HASH384)) << 8) //0x00002400
+#define SHA2_512 (((SHA2 << 4) | (HASH512)) << 8) //0x00002500
+#define SHA3_224 (((SHA3 << 4) | (HASH224)) << 8) //0x00003200
+#define SHA3_256 (((SHA3 << 4) | (HASH256)) << 8) //0x00003300
+#define SHA3_384 (((SHA3 << 4) | (HASH384)) << 8) //0x00003400
+#define SHA3_512 (((SHA3 << 4) | (HASH512)) << 8) //0x00003500
+
+#define HMAC_SHA1_160 ((((SHA1 << 4) | (HASH160)) << 8) | (HMAC) << 16) //0x00011100
+#define HMAC_SHA2_256 ((((SHA2 << 4) | (HASH256)) << 8) | (HMAC) << 16) //0x00012300
+#define HMAC_SHA2_384 ((((SHA2 << 4) | (HASH384)) << 8) | (HMAC) << 16) //0x00012400
+#define HMAC_SHA2_512 ((((SHA2 << 4) | (HASH512)) << 8) | (HMAC) << 16) //0x00012500
// ECC Algorithm ID
-#define ECDSA (0x1)
-#define ECDH (0x2)
-#define PKGEN (0x3)
+#define ECDSA (0x1)
+#define ECDH (0x2)
+#define PKGEN (0x3)
// ECC Curve ID
-#define ECC192 (0x1)
-#define ECC224 (0x2)
-#define ECC256 (0x3)
-#define ECC384 (0x4)
-#define ECC521 (0x5)
+#define ECC192 (0x1)
+#define ECC224 (0x2)
+#define ECC256 (0x3)
+#define ECC384 (0x4)
+#define ECC521 (0x5)
-#define ECDSA_192 ((ECDSA<<4)|(ECC192)) //0x11
-#define ECDSA_224 ((ECDSA<<4)|(ECC224)) //0x12
-#define ECDSA_256 ((ECDSA<<4)|(ECC256)) //0x13
-#define ECDSA_384 ((ECDSA<<4)|(ECC384)) //0x14
-#define ECDSA_521 ((ECDSA<<4)|(ECC521)) //0x15
+#define ECDSA_192 ((ECDSA << 4) | (ECC192)) //0x11
+#define ECDSA_224 ((ECDSA << 4) | (ECC224)) //0x12
+#define ECDSA_256 ((ECDSA << 4) | (ECC256)) //0x13
+#define ECDSA_384 ((ECDSA << 4) | (ECC384)) //0x14
+#define ECDSA_521 ((ECDSA << 4) | (ECC521)) //0x15
-#define ECDH_192 ((ECDH<<4)|(ECC192)) //0x21
-#define ECDH_224 ((ECDH<<4)|(ECC224)) //0x22
-#define ECDH_256 ((ECDH<<4)|(ECC256)) //0x23
-#define ECDH_384 ((ECDH<<4)|(ECC384)) //0x24
-#define ECDH_521 ((ECDH<<4)|(ECC521)) //0x25
+#define ECDH_192 ((ECDH << 4) | (ECC192)) //0x21
+#define ECDH_224 ((ECDH << 4) | (ECC224)) //0x22
+#define ECDH_256 ((ECDH << 4) | (ECC256)) //0x23
+#define ECDH_384 ((ECDH << 4) | (ECC384)) //0x24
+#define ECDH_521 ((ECDH << 4) | (ECC521)) //0x25
-#define GET_ECC_CURVE(OID) ((OID )&0x07)
-#define GET_ECC_ALG(OID) ((OID>> 4)&0x0F)
+#define GET_ECC_CURVE(OID) ((OID) & 0x07)
+#define GET_ECC_ALG(OID) ((OID >> 4) & 0x0F)
-#define GET_HASH_SIZE(OID) ((OID>> 8)&0x07)
-#define GET_HASH_ALG(OID) ((OID>>12)&0x0F)
+#define GET_HASH_SIZE(OID) ((OID >> 8) & 0x07)
+#define GET_HASH_ALG(OID) ((OID >> 12) & 0x0F)
-#define Is_HMAC_ALG(OID) ((OID>>16)&0x0F)
+#define Is_HMAC_ALG(OID) ((OID >> 16) & 0x0F)
-#define Is_ECC_BP(OID) (OID&0x40)
+#define Is_ECC_BP(OID) (OID & 0x40)
-#define RSP_FAIL (0xF1)
-#define RSP_SUCCESS (0xA1)
+#define RSP_FAIL (0xF1)
+#define RSP_SUCCESS (0xA1)
#endif /*ISP_DEFINE_H_ */
* @file isp_driver_error.h
* @brief Headerfile : isp driver for error messages
* @author jinsu.hyun
- * @version v0.01 : 2015.7.7
- * @version v0.10 : 2016.7.15 pre-beta release
+ * @version v0.01 : 2015.7.7
+ * @version v0.10 : 2016.7.15 pre-beta release
* @version v0.50 : 2016.8.13 Init. release version
* @version v1.00 : 2016.9.27 release version v1.0
*/
#define ISP_DRIVER_ERROR_H_
// AES
-#define ERROR_AES_INVALID_BLOCK_LEN (0x000133D1)
-#define ERROR_AES_INVALID_RSP_BLOCK_LEN (0x000233D1)
-#define ERROR_AES_INVALID_MSG_LEN (0x000333D1)
-#define ERROR_AES_INVALID_MODE (0x000433D1)
-#define ERROR_AES_INVALID_KEY_LEN (0x000533D1)
-#define ERROR_AES_INVALID_AAD_LEN (0x000633D1)
-#define ERROR_AES_INVALID_IV_LEN (0x000733D1)
-#define ERROR_AES_INVALID_INDEX (0x000833D1)
-#define ERROR_AES_INVALID_TAG_LEN (0x000933D1)
+#define ERROR_AES_INVALID_BLOCK_LEN (0x000133D1)
+#define ERROR_AES_INVALID_RSP_BLOCK_LEN (0x000233D1)
+#define ERROR_AES_INVALID_MSG_LEN (0x000333D1)
+#define ERROR_AES_INVALID_MODE (0x000433D1)
+#define ERROR_AES_INVALID_KEY_LEN (0x000533D1)
+#define ERROR_AES_INVALID_AAD_LEN (0x000633D1)
+#define ERROR_AES_INVALID_IV_LEN (0x000733D1)
+#define ERROR_AES_INVALID_INDEX (0x000833D1)
+#define ERROR_AES_INVALID_TAG_LEN (0x000933D1)
// Hash
-#define ERROR_HASH_INVALID_MODE (0x000131D1)
-#define ERROR_HASH_INVALID_BLOCK_LEN (0x000231D1)
-#define ERROR_HASH_INVALID_MSG_LEN (0x000331D1)
+#define ERROR_HASH_INVALID_MODE (0x000131D1)
+#define ERROR_HASH_INVALID_BLOCK_LEN (0x000231D1)
+#define ERROR_HASH_INVALID_MSG_LEN (0x000331D1)
// HMAC
-#define ERROR_HMAC_INVALID_MODE (0x000132D1)
-#define ERROR_HMAC_INVALID_KEY_LEN (0x000232D1)
-#define ERROR_HMAC_INVALID_BLOCK_LEN (0x000332D1)
-#define ERROR_HMAC_INVALID_INDEX (0x000432D1)
-#define ERROR_HMAC_INVALID_RSP_BLOCK_LEN (0x000532D1)
+#define ERROR_HMAC_INVALID_MODE (0x000132D1)
+#define ERROR_HMAC_INVALID_KEY_LEN (0x000232D1)
+#define ERROR_HMAC_INVALID_BLOCK_LEN (0x000332D1)
+#define ERROR_HMAC_INVALID_INDEX (0x000432D1)
+#define ERROR_HMAC_INVALID_RSP_BLOCK_LEN (0x000532D1)
// DH
-#define ERROR_DH_INVALID_PRIME_LEN (0x000125D1)
-#define ERROR_DH_INVALID_PUBKEY_LEN (0x000225D1)
-#define ERROR_DH_INVALID_GENERATOR_LEN (0x000325D1)
-#define ERROR_DH_INVALID_PRIME (0x000425D1)
-#define ERROR_DH_INVALID_PUBKEY (0x000525D1)
-#define ERROR_DH_INVALID_GENERATOR (0x000625D1)
+#define ERROR_DH_INVALID_PRIME_LEN (0x000125D1)
+#define ERROR_DH_INVALID_PUBKEY_LEN (0x000225D1)
+#define ERROR_DH_INVALID_GENERATOR_LEN (0x000325D1)
+#define ERROR_DH_INVALID_PRIME (0x000425D1)
+#define ERROR_DH_INVALID_PUBKEY (0x000525D1)
+#define ERROR_DH_INVALID_GENERATOR (0x000625D1)
// ECDSA
-#define ERROR_ECDSA_INVALID_MSG_LEN (0x000111D1)
-#define ERROR_ECDSA_INVALID_SIGNATURE_LEN (0x000311D1)
-#define ERROR_ECDH_INVALID_PUBKEY_LEN (0x000411D1)
-#define ERROR_ECDH_INVALID_PUBKEY (0x000511D1)
+#define ERROR_ECDSA_INVALID_MSG_LEN (0x000111D1)
+#define ERROR_ECDSA_INVALID_SIGNATURE_LEN (0x000311D1)
+#define ERROR_ECDH_INVALID_PUBKEY_LEN (0x000411D1)
+#define ERROR_ECDH_INVALID_PUBKEY (0x000511D1)
// RSA
-#define ERROR_RSA_INVALID_CIPHER_LEN (0x000151D1)
-#define ERROR_RSA_INVALID_MSG_LEN (0x000251D1)
-#define ERROR_RSA_INVALID_SIGN_LEN (0x000351D1)
-#define ERROR_RSA_INVALID_PUKEY (0x000551D1)
-#define ERROR_RSA_INVALID_PAD_SELECTION (0x000451D1)
+#define ERROR_RSA_INVALID_CIPHER_LEN (0x000151D1)
+#define ERROR_RSA_INVALID_MSG_LEN (0x000251D1)
+#define ERROR_RSA_INVALID_SIGN_LEN (0x000351D1)
+#define ERROR_RSA_INVALID_PUKEY (0x000551D1)
+#define ERROR_RSA_INVALID_PAD_SELECTION (0x000451D1)
// RNG
-#define ERROR_RNG_INVALID_RANDOM_REQUEST (0x000161D1)
+#define ERROR_RNG_INVALID_RANDOM_REQUEST (0x000161D1)
// Common
-#define ERROR_SSKeyID_InputID_MISSMATCH (0x000171D1)
-#define ERROR_INVALID_OID (0x000271D1)
+#define ERROR_SSKeyID_InputID_MISSMATCH (0x000171D1)
+#define ERROR_INVALID_OID (0x000271D1)
// Secure Storage
-#define ERROR_SSTORAGE_INVALID_SLOT_INDEX (0x00F1A1D1)
-#define ERROR_SSTORAGE_INVALID_DATA_LEN (0x00F2A1D1)
-#define ERROR_SSTORAGE_INVALID_TYPE (0x00F3A1D1)
-#define ERROR_SSTORAGE_DATA_INVALID_DATA_LEN (0x0002A1D1)
-#define ERROR_SSTORAGE_CERT_INVALID_DATA_LEN (0x0003A2D1)
-#define ERROR_SSTORAGE_KEY_INVALID_DATA_LEN (0x0004A3D1)
-#define ERROR_SSTORAGE_KEY_INVALID_KEY_LEN (0x0005A3D1)
-#define ERROR_SSTORAGE_KEY_INVALID_KEY_TYPE (0x0006A3D1)
-#define ERROR_SSTORAGE_FACTORYKEY_PBKEY_INVALID_DATA_LEN (0x0007A2D1)
-#define ERROR_SSTORAGE_QSPI_WRITE (0x0008A2D1)
-#define ERROR_SSTORAGE_SFS_FOPEN (0x0009A2D1)
-#define ERROR_SSTORAGE_SFS_FSEEK (0x000AA2D1)
-#define ERROR_SSTORAGE_SFS_FREAD (0x000BA2D1)
-#define ERROR_SSTORAGE_SFS_FWRITE (0x000CA2D1)
+#define ERROR_SSTORAGE_INVALID_SLOT_INDEX (0x00F1A1D1)
+#define ERROR_SSTORAGE_INVALID_DATA_LEN (0x00F2A1D1)
+#define ERROR_SSTORAGE_INVALID_TYPE (0x00F3A1D1)
+#define ERROR_SSTORAGE_DATA_INVALID_DATA_LEN (0x0002A1D1)
+#define ERROR_SSTORAGE_CERT_INVALID_DATA_LEN (0x0003A2D1)
+#define ERROR_SSTORAGE_KEY_INVALID_DATA_LEN (0x0004A3D1)
+#define ERROR_SSTORAGE_KEY_INVALID_KEY_LEN (0x0005A3D1)
+#define ERROR_SSTORAGE_KEY_INVALID_KEY_TYPE (0x0006A3D1)
+#define ERROR_SSTORAGE_FACTORYKEY_PBKEY_INVALID_DATA_LEN (0x0007A2D1)
+#define ERROR_SSTORAGE_QSPI_WRITE (0x0008A2D1)
+#define ERROR_SSTORAGE_SFS_FOPEN (0x0009A2D1)
+#define ERROR_SSTORAGE_SFS_FSEEK (0x000AA2D1)
+#define ERROR_SSTORAGE_SFS_FREAD (0x000BA2D1)
+#define ERROR_SSTORAGE_SFS_FWRITE (0x000CA2D1)
// System Function
-#define ERROR_SYSTEM_INVALID_DATA_LEN (0x000201D1)
-#define ERROR_SYSTEM_MAILBOX_BUSY (0x000100D1)
+#define ERROR_SYSTEM_INVALID_DATA_LEN (0x000201D1)
+#define ERROR_SYSTEM_MAILBOX_BUSY (0x000100D1)
// Error from FW
-#define FW_ERROR_ISP_INVALID_FUNCID00 (0x801000F1)
-#define FW_ERROR_ISP_INVALID_FUNCID01 (0x801100F1)
-#define FW_ERROR_ISP_INVALID_FUNCID02 (0x801200F1)
-#define FW_ERROR_ISP_INVALID_FUNCID03 (0x801300F1)
-#define FW_ERROR_ISP_INVALID_DATASIZE (0x801400F1)
-#define FW_ERROR_ISP_FW_BODYSIZE (0x801500F1)
-#define FW_ERROR_ISP_FW_ROLLBACK_CNT (0x801600F1)
-#define FW_ERROR_ISP_FW_INVALID_PUBLICKEY (0x801700F1)
-#define FW_ERROR_ISP_RESTORE_INTEGRITY_FAIL (0x801800F1)
-#define FW_ERROR_ISP_IP_BUSY (0x801900F1)
-#define FW_ERROR_ISP_SRAM_CMD_NOT_SUPPORTED (0x801A00F1)
+#define FW_ERROR_ISP_INVALID_FUNCID00 (0x801000F1)
+#define FW_ERROR_ISP_INVALID_FUNCID01 (0x801100F1)
+#define FW_ERROR_ISP_INVALID_FUNCID02 (0x801200F1)
+#define FW_ERROR_ISP_INVALID_FUNCID03 (0x801300F1)
+#define FW_ERROR_ISP_INVALID_DATASIZE (0x801400F1)
+#define FW_ERROR_ISP_FW_BODYSIZE (0x801500F1)
+#define FW_ERROR_ISP_FW_ROLLBACK_CNT (0x801600F1)
+#define FW_ERROR_ISP_FW_INVALID_PUBLICKEY (0x801700F1)
+#define FW_ERROR_ISP_RESTORE_INTEGRITY_FAIL (0x801800F1)
+#define FW_ERROR_ISP_IP_BUSY (0x801900F1)
+#define FW_ERROR_ISP_SRAM_CMD_NOT_SUPPORTED (0x801A00F1)
-#define FW_ERROR_INVALID_FUNCTION (0x000100f1)
-#define FW_ERROR_FW_VERIFY (0x001400f1)
-#define FW_ERROR_RESTORE_FAIL (0x001800f1)
-#define FW_ERROR_IP_BUSY (0x001900f1)
-#define FW_ERROR_INVALID_OID (0x003000f1)
-#define FW_ERROR_INVALID_INPUT (0x003400f1)
-#define FW_ERROR_INPUT_SETTING (0x004000f1)
-#define FW_ERROR_PRNG (0x005000f1)
-#define FW_FAIL_INVALID_SIGNATURE (0x006000f1)
-#define FW_FAIL_INFINITY_POINT (0x006100f1)
-#define FW_FAIL_NOT_ON_ECC_CURVE (0x006200f1)
+#define FW_ERROR_INVALID_FUNCTION (0x000100f1)
+#define FW_ERROR_FW_VERIFY (0x001400f1)
+#define FW_ERROR_RESTORE_FAIL (0x001800f1)
+#define FW_ERROR_IP_BUSY (0x001900f1)
+#define FW_ERROR_INVALID_OID (0x003000f1)
+#define FW_ERROR_INVALID_INPUT (0x003400f1)
+#define FW_ERROR_INPUT_SETTING (0x004000f1)
+#define FW_ERROR_PRNG (0x005000f1)
+#define FW_FAIL_INVALID_SIGNATURE (0x006000f1)
+#define FW_FAIL_INFINITY_POINT (0x006100f1)
+#define FW_FAIL_NOT_ON_ECC_CURVE (0x006200f1)
// SRAM error
-#define FW_ERROR_INVALID_EXEC_ORDER (0x80AF00F1)
-#define FW_ERROR_OVER_VALID_RSA_MSGLEN (0x803500F1)
-#define FW_ERROR_INVALID_RSA_MODLEN (0x803600F1)
-#define FW_ERROR_Input_Public_is_not_odd (0x803700F1)
-#define FW_ERROR_OVER_VALID_RSA_Saltlen (0x803800F1)
-#define FW_ERROR_NO_PUKEY (0x803900F1)
-#define FW_FAIL_OVER_MR_TRIALS (0x805600F1)
-#define FW_FAIL_OVER_DH_RETRIALS (0x805600F1)
-#define FW_FAIL_OVER_ECC_RETRIALS (0x805600F1)
-#define FW_FAIL_NO_OUTPUT_KEY (0x805700F1)
-#define FW_FAIL_OVER_GEN_RETRIALS (0x805800F1)
-#define FW_ERROR_INVALID_RSASIGNATURE_0xBC (0x806400F1)
-#define FW_ERROR_INVALID_RSASIGNATURE_lsb (0x806500F1)
-#define FW_ERROR_INVALID_RSANONZERO_PS (0x806600F1)
-#define FW_ERROR_INVALID_RSADB_SPLITTER (0x806700F1)
-#define FW_ERROR_INVALID_SIGNATURE_BLEN (0x806800F1)
-#define FW_ERROR_INVALID_CIPHER (0x806900F1)
-#define FW_ERROR_INVALID_SEQUENCE (0x80ff00F1)
-#define FW_ERROR_DER2INT_PARSE (0x80fe00F1)
-#define FW_ERROR_AES_INVALID_KEYSEL (0x80D000F1)
-#define FW_ERROR_AES_INVALID_KEY_LEN (0x80D100F1)
-#define FW_ERROR_AES_INVALID_DIR_MODE (0x80D200F1)
-#define FW_ERROR_AES_INVLIAD_SWAP (0x80D300F1)
-#define FW_ERROR_AES_INVALID_MODE (0x80D400F1)
-#define FW_ERROR_AES_INVALID_TAG (0x80D500F1)
-#define FW_ERROR_AES_INVALID_BLOCK_LEN (0x80D600F1)
-#define FW_ERROR_AES_KM_BUSY (0x80D700F1)
-#define FW_ERROR_AES_KM_INIT (0x80D800F1)
-#define FW_ERROR_SSTORAGE_DATA_INVALID_SLOT_INDEX (0x80E100F1)
-#define FW_ERROR_SSTORAGE_CERT_INVALID_SLOT_INDEX (0x80E200F1)
-#define FW_ERROR_SSTORAGE_KEY_INVALID_KEY_LEN (0x80E300F1)
-#define FW_ERROR_SSTORAGE_KEY_INVALID_MODE (0x80E400F1)
-#define FW_ERROR_SSTORAGE_INVALID_DATA_TYPE (0x80E500F1)
-#define FW_ERROR_SSTORAGE_KEY_INVALID_KEYTYPE (0x80E600F1)
-#define FW_ERROR_SSTORAGE_KEY_INVALID_SLOT_INDEX (0x80E700F1)
-#define FW_ERROR_SSTORAGE_FACTORYKEY_INVALID_HMAC (0x80E800F1)
-#define FW_ERROR_SSTORAGE_FACTORYKEY_INVALID_ENCODING (0x80E900F1)
-#define FW_ERROR_SSTORAGE_FACTORYKEY_INVALID_KEYTYPE (0x80EA00F1)
-#define FW_ERROR_RNG_INVALID_LEN (0x80f100F1)
-#define FW_ERROR_KEYGEN_INVALID_KEYLEN (0x80f200F1)
-#define FW_ERROR_PKA_IP_BUSY (0x80B100F1)
-#define FW_ERROR_HASH_IP_BUSY (0x80B200F1)
-#define FW_ERROR_PRNG_IP_BUSY (0x80B300F1)
+#define FW_ERROR_INVALID_EXEC_ORDER (0x80AF00F1)
+#define FW_ERROR_OVER_VALID_RSA_MSGLEN (0x803500F1)
+#define FW_ERROR_INVALID_RSA_MODLEN (0x803600F1)
+#define FW_ERROR_Input_Public_is_not_odd (0x803700F1)
+#define FW_ERROR_OVER_VALID_RSA_Saltlen (0x803800F1)
+#define FW_ERROR_NO_PUKEY (0x803900F1)
+#define FW_FAIL_OVER_MR_TRIALS (0x805600F1)
+#define FW_FAIL_OVER_DH_RETRIALS (0x805600F1)
+#define FW_FAIL_OVER_ECC_RETRIALS (0x805600F1)
+#define FW_FAIL_NO_OUTPUT_KEY (0x805700F1)
+#define FW_FAIL_OVER_GEN_RETRIALS (0x805800F1)
+#define FW_ERROR_INVALID_RSASIGNATURE_0xBC (0x806400F1)
+#define FW_ERROR_INVALID_RSASIGNATURE_lsb (0x806500F1)
+#define FW_ERROR_INVALID_RSANONZERO_PS (0x806600F1)
+#define FW_ERROR_INVALID_RSADB_SPLITTER (0x806700F1)
+#define FW_ERROR_INVALID_SIGNATURE_BLEN (0x806800F1)
+#define FW_ERROR_INVALID_CIPHER (0x806900F1)
+#define FW_ERROR_INVALID_SEQUENCE (0x80ff00F1)
+#define FW_ERROR_DER2INT_PARSE (0x80fe00F1)
+#define FW_ERROR_AES_INVALID_KEYSEL (0x80D000F1)
+#define FW_ERROR_AES_INVALID_KEY_LEN (0x80D100F1)
+#define FW_ERROR_AES_INVALID_DIR_MODE (0x80D200F1)
+#define FW_ERROR_AES_INVLIAD_SWAP (0x80D300F1)
+#define FW_ERROR_AES_INVALID_MODE (0x80D400F1)
+#define FW_ERROR_AES_INVALID_TAG (0x80D500F1)
+#define FW_ERROR_AES_INVALID_BLOCK_LEN (0x80D600F1)
+#define FW_ERROR_AES_KM_BUSY (0x80D700F1)
+#define FW_ERROR_AES_KM_INIT (0x80D800F1)
+#define FW_ERROR_SSTORAGE_DATA_INVALID_SLOT_INDEX (0x80E100F1)
+#define FW_ERROR_SSTORAGE_CERT_INVALID_SLOT_INDEX (0x80E200F1)
+#define FW_ERROR_SSTORAGE_KEY_INVALID_KEY_LEN (0x80E300F1)
+#define FW_ERROR_SSTORAGE_KEY_INVALID_MODE (0x80E400F1)
+#define FW_ERROR_SSTORAGE_INVALID_DATA_TYPE (0x80E500F1)
+#define FW_ERROR_SSTORAGE_KEY_INVALID_KEYTYPE (0x80E600F1)
+#define FW_ERROR_SSTORAGE_KEY_INVALID_SLOT_INDEX (0x80E700F1)
+#define FW_ERROR_SSTORAGE_FACTORYKEY_INVALID_HMAC (0x80E800F1)
+#define FW_ERROR_SSTORAGE_FACTORYKEY_INVALID_ENCODING (0x80E900F1)
+#define FW_ERROR_SSTORAGE_FACTORYKEY_INVALID_KEYTYPE (0x80EA00F1)
+#define FW_ERROR_RNG_INVALID_LEN (0x80f100F1)
+#define FW_ERROR_KEYGEN_INVALID_KEYLEN (0x80f200F1)
+#define FW_ERROR_PKA_IP_BUSY (0x80B100F1)
+#define FW_ERROR_HASH_IP_BUSY (0x80B200F1)
+#define FW_ERROR_PRNG_IP_BUSY (0x80B300F1)
#endif /* ISP_DRIVER_ERROR_H_ */
unsigned int type;
};
-#define KEY_PATH_BASE "/mnt"
-//#define KEY_PATH_BASE "/mnt/sss"
-
-#define SECURE_STORAGE_TYPE_FACTORYKEY_KEY (0x00)
-#define SECURE_STORAGE_TYPE_FACTORYKEY_DATA (0x01)
-
-#define SECURE_STORAGE_TYPE_KEY_AES (0x0A)
-#define SECURE_STORAGE_TYPE_KEY_HMAC (0x0B)
-#define SECURE_STORAGE_TYPE_KEY_RSA (0x0C)
-#define SECURE_STORAGE_TYPE_KEY_DH (0x0D)
-#define SECURE_STORAGE_TYPE_KEY_ECC (0x0E)
-#define SECURE_STORAGE_TYPE_DATA (0x10)
-#define SECURE_STORAGE_TYPE_CERT (0x11)
-
-#define FACTORYKEY_ARTIK_PSK (0x80000100)
-#define FACTORYKEY_ARTIK_DEVICE (0x00010120)
-#define FACTORYKEY_ARTIK_CERT (0x00010122)
-#define FACTORYKEY_DA_CA (0x00081110)
-#define FACTORYKEY_DA_DEVICE (0x00081210)
-#define FACTORYKEY_DA_PBKEY (0x00081211)
-#define FACTORYKEY_IOTIVITY_ECC (0x00011120)
-#define FACTORYKEY_IOTIVITY_ECC_CERT (0x00011122)
-#define FACTORYKEY_IOTIVITY_SUB_CA_CERT (0x00011222)
+#define KEY_PATH_BASE "/mnt"
+//#define KEY_PATH_BASE "/mnt/sss"
+
+#define SECURE_STORAGE_TYPE_FACTORYKEY_KEY (0x00)
+#define SECURE_STORAGE_TYPE_FACTORYKEY_DATA (0x01)
+
+#define SECURE_STORAGE_TYPE_KEY_AES (0x0A)
+#define SECURE_STORAGE_TYPE_KEY_HMAC (0x0B)
+#define SECURE_STORAGE_TYPE_KEY_RSA (0x0C)
+#define SECURE_STORAGE_TYPE_KEY_DH (0x0D)
+#define SECURE_STORAGE_TYPE_KEY_ECC (0x0E)
+#define SECURE_STORAGE_TYPE_DATA (0x10)
+#define SECURE_STORAGE_TYPE_CERT (0x11)
+
+#define FACTORYKEY_ARTIK_PSK (0x80000100)
+#define FACTORYKEY_ARTIK_DEVICE (0x00010120)
+#define FACTORYKEY_ARTIK_CERT (0x00010122)
+#define FACTORYKEY_DA_CA (0x00081110)
+#define FACTORYKEY_DA_DEVICE (0x00081210)
+#define FACTORYKEY_DA_PBKEY (0x00081211)
+#define FACTORYKEY_IOTIVITY_ECC (0x00011120)
+#define FACTORYKEY_IOTIVITY_ECC_CERT (0x00011122)
+#define FACTORYKEY_IOTIVITY_SUB_CA_CERT (0x00011222)
// ======================================
// Function
/*
* OID LIST
*/
-#define OIDMAX_HMAC (4)
-#define OID_HMAC_SHA1_160 (0x00011100)
-#define OID_HMAC_SHA2_256 (0x00012300)
-#define OID_HMAC_SHA2_384 (0x00012400)
-#define OID_HMAC_SHA2_512 (0x00012500)
+#define OIDMAX_HMAC (4)
+#define OID_HMAC_SHA1_160 (0x00011100)
+#define OID_HMAC_SHA2_256 (0x00012300)
+#define OID_HMAC_SHA2_384 (0x00012400)
+#define OID_HMAC_SHA2_512 (0x00012500)
-#define OIDMAX_HASH (8)
-#define OID_SHA1_160 (0x00001100)
-#define OID_SHA2_256 (0x00002300)
-#define OID_SHA2_384 (0x00002400)
-#define OID_SHA2_512 (0x00002500)
-#define OID_SHA3_224 (0x00003200)
-#define OID_SHA3_256 (0x00003300)
-#define OID_SHA3_384 (0x00003400)
-#define OID_SHA3_512 (0x00003500)
+#define OIDMAX_HASH (8)
+#define OID_SHA1_160 (0x00001100)
+#define OID_SHA2_256 (0x00002300)
+#define OID_SHA2_384 (0x00002400)
+#define OID_SHA2_512 (0x00002500)
+#define OID_SHA3_224 (0x00003200)
+#define OID_SHA3_256 (0x00003300)
+#define OID_SHA3_384 (0x00003400)
+#define OID_SHA3_512 (0x00003500)
-#define OIDMAX_DH (2)
-#define OID_DH_1024 (0x00001191)
-#define OID_DH_2048 (0x00002392)
+#define OIDMAX_DH (2)
+#define OID_DH_1024 (0x00001191)
+#define OID_DH_2048 (0x00002392)
-#define OIDMAX_ECC (6)
-#define OID_ECC_P192 (0x00000011)
-#define OID_ECC_P224 (0x00000012)
-#define OID_ECC_P256 (0x00000013)
-#define OID_ECC_P384 (0x00000014)
-#define OID_ECC_P521 (0x00000015)
-#define OID_ECC_BP256 (0x00000053)
+#define OIDMAX_ECC (6)
+#define OID_ECC_P192 (0x00000011)
+#define OID_ECC_P224 (0x00000012)
+#define OID_ECC_P256 (0x00000013)
+#define OID_ECC_P384 (0x00000014)
+#define OID_ECC_P521 (0x00000015)
+#define OID_ECC_BP256 (0x00000053)
-#define OIDMAX_RSA (2)
-#define OID_RSA_1024 (0x000000B1)
-#define OID_RSA_2048 (0x000000B2)
+#define OIDMAX_RSA (2)
+#define OID_RSA_1024 (0x000000B1)
+#define OID_RSA_2048 (0x000000B2)
-#define OIDMAX_ECDSA (24)
-#define OID_ECDSA_BP256_SHA1_160 ( OID_ECC_BP256|OID_SHA1_160 )
-#define OID_ECDSA_BP256_SHA2_256 ( OID_ECC_BP256|OID_SHA2_256 )
-#define OID_ECDSA_BP256_SHA2_384 ( OID_ECC_BP256|OID_SHA2_384 )
-#define OID_ECDSA_BP256_SHA2_512 ( OID_ECC_BP256|OID_SHA2_512 )
+#define OIDMAX_ECDSA (24)
+#define OID_ECDSA_BP256_SHA1_160 (OID_ECC_BP256 | OID_SHA1_160)
+#define OID_ECDSA_BP256_SHA2_256 (OID_ECC_BP256 | OID_SHA2_256)
+#define OID_ECDSA_BP256_SHA2_384 (OID_ECC_BP256 | OID_SHA2_384)
+#define OID_ECDSA_BP256_SHA2_512 (OID_ECC_BP256 | OID_SHA2_512)
-#define OID_ECDSA_P192_SHA1_160 ( OID_ECC_P192|OID_SHA1_160 )
-#define OID_ECDSA_P192_SHA2_256 ( OID_ECC_P192|OID_SHA2_256 )
-#define OID_ECDSA_P192_SHA2_384 ( OID_ECC_P192|OID_SHA2_384 )
-#define OID_ECDSA_P192_SHA2_512 ( OID_ECC_P192|OID_SHA2_512 )
-#define OID_ECDSA_P224_SHA1_160 ( OID_ECC_P224|OID_SHA1_160 )
-#define OID_ECDSA_P224_SHA2_256 ( OID_ECC_P224|OID_SHA2_256 )
-#define OID_ECDSA_P224_SHA2_384 ( OID_ECC_P224|OID_SHA2_384 )
-#define OID_ECDSA_P224_SHA2_512 ( OID_ECC_P224|OID_SHA2_512 )
-#define OID_ECDSA_P256_SHA1_160 ( OID_ECC_P256|OID_SHA1_160 )
-#define OID_ECDSA_P256_SHA2_256 ( OID_ECC_P256|OID_SHA2_256 )
-#define OID_ECDSA_P256_SHA2_384 ( OID_ECC_P256|OID_SHA2_384 )
-#define OID_ECDSA_P256_SHA2_512 ( OID_ECC_P256|OID_SHA2_512 )
-#define OID_ECDSA_P384_SHA1_160 ( OID_ECC_P384|OID_SHA1_160 )
-#define OID_ECDSA_P384_SHA2_256 ( OID_ECC_P384|OID_SHA2_256 )
-#define OID_ECDSA_P384_SHA2_384 ( OID_ECC_P384|OID_SHA2_384 )
-#define OID_ECDSA_P384_SHA2_512 ( OID_ECC_P384|OID_SHA2_512 )
-#define OID_ECDSA_P521_SHA1_160 ( OID_ECC_P521|OID_SHA1_160 )
-#define OID_ECDSA_P521_SHA2_256 ( OID_ECC_P521|OID_SHA2_256 )
-#define OID_ECDSA_P521_SHA2_384 ( OID_ECC_P521|OID_SHA2_384 )
-#define OID_ECDSA_P521_SHA2_512 ( OID_ECC_P521|OID_SHA2_512 )
+#define OID_ECDSA_P192_SHA1_160 (OID_ECC_P192 | OID_SHA1_160)
+#define OID_ECDSA_P192_SHA2_256 (OID_ECC_P192 | OID_SHA2_256)
+#define OID_ECDSA_P192_SHA2_384 (OID_ECC_P192 | OID_SHA2_384)
+#define OID_ECDSA_P192_SHA2_512 (OID_ECC_P192 | OID_SHA2_512)
+#define OID_ECDSA_P224_SHA1_160 (OID_ECC_P224 | OID_SHA1_160)
+#define OID_ECDSA_P224_SHA2_256 (OID_ECC_P224 | OID_SHA2_256)
+#define OID_ECDSA_P224_SHA2_384 (OID_ECC_P224 | OID_SHA2_384)
+#define OID_ECDSA_P224_SHA2_512 (OID_ECC_P224 | OID_SHA2_512)
+#define OID_ECDSA_P256_SHA1_160 (OID_ECC_P256 | OID_SHA1_160)
+#define OID_ECDSA_P256_SHA2_256 (OID_ECC_P256 | OID_SHA2_256)
+#define OID_ECDSA_P256_SHA2_384 (OID_ECC_P256 | OID_SHA2_384)
+#define OID_ECDSA_P256_SHA2_512 (OID_ECC_P256 | OID_SHA2_512)
+#define OID_ECDSA_P384_SHA1_160 (OID_ECC_P384 | OID_SHA1_160)
+#define OID_ECDSA_P384_SHA2_256 (OID_ECC_P384 | OID_SHA2_256)
+#define OID_ECDSA_P384_SHA2_384 (OID_ECC_P384 | OID_SHA2_384)
+#define OID_ECDSA_P384_SHA2_512 (OID_ECC_P384 | OID_SHA2_512)
+#define OID_ECDSA_P521_SHA1_160 (OID_ECC_P521 | OID_SHA1_160)
+#define OID_ECDSA_P521_SHA2_256 (OID_ECC_P521 | OID_SHA2_256)
+#define OID_ECDSA_P521_SHA2_384 (OID_ECC_P521 | OID_SHA2_384)
+#define OID_ECDSA_P521_SHA2_512 (OID_ECC_P521 | OID_SHA2_512)
#endif /*ISP_OID_H_ */
#define CTRL_FIELD(val) (*(volatile u32 *)(CTRL_FIELD_ADDR(val)))
#define DATA_FIELD(val) (*(volatile u32 *)(DATA_FIELD_ADDR(val)))
-#define ISP_DATA_FIELD_SET(index, value) DATA_FIELD(index) = value
-#define ISP_DATA_FIELD_GET(index, value) value = DATA_FIELD(index)
-#define ISP_CTRL_FIELD_SET(index, value) CTRL_FIELD(index) = value
-#define ISP_CTRL_FIELD_GET(index, value) value = CTRL_FIELD(index)
+#define ISP_DATA_FIELD_SET(index, value) DATA_FIELD(index) = value
+#define ISP_DATA_FIELD_GET(index, value) value = DATA_FIELD(index)
+#define ISP_CTRL_FIELD_SET(index, value) CTRL_FIELD(index) = value
+#define ISP_CTRL_FIELD_GET(index, value) value = CTRL_FIELD(index)
#endif /* ISP_SSS_MAP_H_ */
/********** types **********/
-typedef unsigned int u32;
-typedef signed int s32;
+typedef unsigned int u32;
+typedef signed int s32;
typedef unsigned char u8;
-typedef signed char s8;
+typedef signed char s8;
/********** Macro Function for SFR access **********/
-#define BIT(nbit) (0x1u << (nbit))
+#define BIT(nbit) (0x1u << (nbit))
-#define SFR_BIT_CLR(val, bit) ((val) &= (~(bit))) ///<bit clear by bit value
-#define SFR_BIT_SET(val, bit) ((val) |= (bit)) ///<bit set by bit value
+#define SFR_BIT_CLR(val, bit) ((val) &= (~(bit))) ///<bit clear by bit value
+#define SFR_BIT_SET(val, bit) ((val) |= (bit)) ///<bit set by bit value
-#define SFR_SET(sfr, val) ((sfr) = (val))
-#define SFR_GET(sfr, val) ((val) = (sfr))
+#define SFR_SET(sfr, val) ((sfr) = (val))
+#define SFR_GET(sfr, val) ((val) = (sfr))
-#define WAIT_SFR_BIT_CLR(sfr, bit) while((sfr) & (bit)) ///<wait until bit is cleared
-#define WAIT_SFR_BIT_SET(sfr, bit) while(!((sfr) & (bit))) ///<wait until bit is set
+#define WAIT_SFR_BIT_CLR(sfr, bit) while ((sfr) & (bit)) ///<wait until bit is cleared
+#define WAIT_SFR_BIT_SET(sfr, bit) while (!((sfr) & (bit))) ///<wait until bit is set
#define SET_DWORD_TO_BBUF(buf, dword) \
((u8 *)(buf))[3] = ((u8)((dword) >> 0)); \
(((val) & 0xff000000) >> 24) \
)
-#define CEIL_BY_WORD(val) (val&0x3) ? (1+(val>>2)) : (val>>2)
-#define CEIL_BY_16BYTE(val) (val&0xF) ? ((val&0xFFFFFFF0)+0x10) : (val)
+#define CEIL_BY_WORD(val) (val & 0x3) ? (1 + (val >> 2)) : (val >> 2)
+#define CEIL_BY_16BYTE(val) (val & 0xF) ? ((val & 0xFFFFFFF0) + 0x10) : (val)
/********** Defines **********/
-#define SUCCESS (0x00)
-#define FAIL (0x01)
+#define SUCCESS (0x00)
+#define FAIL (0x01)
#ifndef NULL
-#define NULL ((void *) 0)
+#define NULL ((void *) 0)
#endif
#endif /* ISP_TYPE_H_ */
#ifndef MB_CMD_AES_H_
#define MB_CMD_AES_H_
-#define AES_ENCTYPT (0x00)
-#define AES_DECRYPT (0x01)
+#define AES_ENCTYPT (0x00)
+#define AES_DECRYPT (0x01)
// Key Size field
-#define AESKEY_128 (0x10)
-#define AESKEY_192 (0x18)
-#define AESKEY_256 (0x20)
+#define AESKEY_128 (0x10)
+#define AESKEY_192 (0x18)
+#define AESKEY_256 (0x20)
// Mode
-#define AES_ECB_MODE (0x0008)
-#define AES_CBC_MODE (0x0108)
-#define AES_CTR_MODE (0x0208)
-#define AES_XTS_MODE (0x0308)
-#define AES_CCM_MODE (0x1008)
-#define AES_GCM_MODE (0x1108)
-#define AES_KW_MODE (0x1208)
+#define AES_ECB_MODE (0x0008)
+#define AES_CBC_MODE (0x0108)
+#define AES_CTR_MODE (0x0208)
+#define AES_XTS_MODE (0x0308)
+#define AES_CCM_MODE (0x1008)
+#define AES_GCM_MODE (0x1108)
+#define AES_KW_MODE (0x1208)
-#define AES_128_ECB ((AESKEY_128<<16)|(AES_ECB)) // 0x00001008
-#define AES_192_ECB ((AESKEY_192<<16)|(AES_ECB)) // 0x00001808
-#define AES_256_ECB ((AESKEY_256<<16)|(AES_ECB)) // 0x00002008
-#define AES_128_CBC ((AESKEY_128<<16)|(AES_CBC)) // 0x00101008
-#define AES_192_CBC ((AESKEY_192<<16)|(AES_CBC)) // 0x00101808
-#define AES_256_CBC ((AESKEY_256<<16)|(AES_CBC)) // 0x00102008
-#define AES_128_CTR ((AESKEY_128<<16)|(AES_CTR)) // 0x00201008
-#define AES_192_CTR ((AESKEY_192<<16)|(AES_CTR)) // 0x00201808
-#define AES_256_CTR ((AESKEY_256<<16)|(AES_CTR)) // 0x00202008
-#define AES_128_XTS ((AESKEY_128<<16)|(AES_XTS)) // 0x00301008
+#define AES_128_ECB ((AESKEY_128 << 16) | (AES_ECB)) // 0x00001008
+#define AES_192_ECB ((AESKEY_192 << 16) | (AES_ECB)) // 0x00001808
+#define AES_256_ECB ((AESKEY_256 << 16) | (AES_ECB)) // 0x00002008
+#define AES_128_CBC ((AESKEY_128 << 16) | (AES_CBC)) // 0x00101008
+#define AES_192_CBC ((AESKEY_192 << 16) | (AES_CBC)) // 0x00101808
+#define AES_256_CBC ((AESKEY_256 << 16) | (AES_CBC)) // 0x00102008
+#define AES_128_CTR ((AESKEY_128 << 16) | (AES_CTR)) // 0x00201008
+#define AES_192_CTR ((AESKEY_192 << 16) | (AES_CTR)) // 0x00201808
+#define AES_256_CTR ((AESKEY_256 << 16) | (AES_CTR)) // 0x00202008
+#define AES_128_XTS ((AESKEY_128 << 16) | (AES_XTS)) // 0x00301008
// No AES_192_XTS
-#define AES_256_XTS ((AESKEY_256<<16)|(AES_XTS)) // 0x00302008
-#define AES_128_CCM ((AESKEY_128<<16)|(AES_CCM)) // 0x01001008
-#define AES_192_CCM ((AESKEY_192<<16)|(AES_CCM)) // 0x01001808
-#define AES_256_CCM ((AESKEY_256<<16)|(AES_CCM)) // 0x01002008
-#define AES_128_GCM ((AESKEY_128<<16)|(AES_GCM)) // 0x01101008
-#define AES_192_GCM ((AESKEY_192<<16)|(AES_GCM)) // 0x01101808
-#define AES_256_GCM ((AESKEY_256<<16)|(AES_GCM)) // 0x01102008
+#define AES_256_XTS ((AESKEY_256 << 16) | (AES_XTS)) // 0x00302008
+#define AES_128_CCM ((AESKEY_128 << 16) | (AES_CCM)) // 0x01001008
+#define AES_192_CCM ((AESKEY_192 << 16) | (AES_CCM)) // 0x01001808
+#define AES_256_CCM ((AESKEY_256 << 16) | (AES_CCM)) // 0x01002008
+#define AES_128_GCM ((AESKEY_128 << 16) | (AES_GCM)) // 0x01101008
+#define AES_192_GCM ((AESKEY_192 << 16) | (AES_GCM)) // 0x01101808
+#define AES_256_GCM ((AESKEY_256 << 16) | (AES_GCM)) // 0x01102008
-#define MAX_MB_AES_BLOCK_BLEN (240)
-#define MAX_AES_AAD_BLEN (128)
+#define MAX_MB_AES_BLOCK_BLEN (240)
+#define MAX_AES_AAD_BLEN (128)
// ======================================
// Structure
#ifndef MB_CMD_ECDSA_H_
#define MB_CMD_ECDSA_H_
-#define MAX_ECDSA_BLOCK_BLEN (128)
-#define MAX_ECDSA_KEY_BLEN (244)
+#define MAX_ECDSA_BLOCK_BLEN (128)
+#define MAX_ECDSA_KEY_BLEN (244)
// ======================================
// Structure
unsigned int msg_type;
};
-#define MAX_HASH_BLOCK_BLEN (144)
-#define GET_HASH_SIZE(OID) ((OID>> 8)&0x07)
+#define MAX_HASH_BLOCK_BLEN (144)
+#define GET_HASH_SIZE(OID) ((OID >> 8) & 0x07)
// ======================================
// Function
// ======================================
// Mailbox Command
// ======================================
-#define FUNC_HASH_INIT (0x00103102)
-#define FUNC_HASH_UPDATE (0x00203102)
-#define FUNC_HASH_FINAL (0x00303102)
-#define FUNC_HASH_DMA (0x01013102)
-#define FUNC_HASH_DESCRIPTOR (0x02013102)
+#define FUNC_HASH_INIT (0x00103102)
+#define FUNC_HASH_UPDATE (0x00203102)
+#define FUNC_HASH_FINAL (0x00303102)
+#define FUNC_HASH_DMA (0x01013102)
+#define FUNC_HASH_DESCRIPTOR (0x02013102)
#endif /* MB_CMD_HASH_H_ */
#ifndef MB_CMD_HMAC_H_
#define MB_CMD_HMAC_H_
-#define MAX_HMAC_BLOCK_BLEN (128)
+#define MAX_HMAC_BLOCK_BLEN (128)
//! @struct sHMAC_MSG
//! @brief struct of message for HMAC
// ======================================
// Mailbox Command
// ======================================
-#define FUNC_RSA_ENCRYPT_SECUREKEY1 (0x00015102)
-#define FUNC_RSA_ENCRYPT_SECUREKEY2 (0x01025102)
-#define FUNC_RSA_ENCRYPT_SECUREKEY3 (0x00035102)
+#define FUNC_RSA_ENCRYPT_SECUREKEY1 (0x00015102)
+#define FUNC_RSA_ENCRYPT_SECUREKEY2 (0x01025102)
+#define FUNC_RSA_ENCRYPT_SECUREKEY3 (0x00035102)
-#define FUNC_RSA_DECRYPT_SECUREKEY1 (0x00015202)
-#define FUNC_RSA_DECRYPT_SECUREKEY2 (0x01025202)
+#define FUNC_RSA_DECRYPT_SECUREKEY1 (0x00015202)
+#define FUNC_RSA_DECRYPT_SECUREKEY2 (0x01025202)
//skip 03rd when securekey
-#define FUNC_RSA_DECRYPT_SECUREKEY3 (0x00045202)
+#define FUNC_RSA_DECRYPT_SECUREKEY3 (0x00045202)
-#define FUNC_RSA_SIGN_SECUREKEY1 (0x00011502)
-#define FUNC_RSA_SIGN_SECUREKEY2 (0x01021502)
+#define FUNC_RSA_SIGN_SECUREKEY1 (0x00011502)
+#define FUNC_RSA_SIGN_SECUREKEY2 (0x01021502)
//skip 03rd when secure key
-#define FUNC_RSA_SIGN_SECUREKEY3 (0x00041502)
-#define FUNC_RSA_SIGN_SECUREKEY3_PKCS (0x01041502)
-#define FUNC_RSA_SIGN_SECUREKEY3_PSS (0x00041502)
-
-#define FUNC_RSA_VERIFY_SECUREKEY1 (0x00011602)
-#define FUNC_RSA_VERIFY_SECUREKEY2 (0x01021602)
-#define FUNC_RSA_VERIFY_SECUREKEY3 (0x00031602)
-#define FUNC_RSA_VERIFY_SECUREKEY4 (0x00041602)
+#define FUNC_RSA_SIGN_SECUREKEY3 (0x00041502)
+#define FUNC_RSA_SIGN_SECUREKEY3_PKCS (0x01041502)
+#define FUNC_RSA_SIGN_SECUREKEY3_PSS (0x00041502)
+
+#define FUNC_RSA_VERIFY_SECUREKEY1 (0x00011602)
+#define FUNC_RSA_VERIFY_SECUREKEY2 (0x01021602)
+#define FUNC_RSA_VERIFY_SECUREKEY3 (0x00031602)
+#define FUNC_RSA_VERIFY_SECUREKEY4 (0x00041602)
#define FUNC_RSA_GENKEY_SECUREKEY1_RNDPK (0x01011702)
#define FUNC_RSA_GENKEY_SECUREKEY1_USERPK (0x03011702)
// ======================================
// Mailbox Command
// ======================================
-#define FUNC_SYSTEM_GET_INFO (0x00000102)
-#define FUNC_SYSTEM_CLEAR (0x00000202)
+#define FUNC_SYSTEM_GET_INFO (0x00000102)
+#define FUNC_SYSTEM_CLEAR (0x00000202)
#endif /* MB_CMD_SYSTEM_H_ */
/* Device geometry description, compact form (2 bytes per entry) */
struct ee_geom_s {
- uint8_t bytes : 4; /* Power of two of 128 bytes (0:128 1:256 2:512 etc) */
- uint8_t org : 4; /* Organization, bytes */
- uint8_t addrlen : 4; /* Number of bytes in command address field */
- uint8_t flags : 4; /* Special Features ??? */
+ uint8_t bytes:4; /* Power of two of 128 bytes (0:128 1:256 2:512 etc) */
+ uint8_t org:4; /* Organization, bytes */
+ uint8_t addrlen:4; /* Number of bytes in command address field */
+ uint8_t flags:4; /* Special Features ??? */
};
static const struct ee_geom_s g_ee_devices[] = {
#define TIMER_SYNC_SYNCT1_TB TIMER_SYNC_SYNCT1(TIMER_SYNC_TB)
#define TIMER_SYNC_SYNCT1_TATB TIMER_SYNC_SYNCT1(TIMER_SYNC_TATB)
#define TIMER_SYNC_SYNCT2_SHIFT (4) /* Synchronize GPTM timer 2 */
-#define TIMER_SYNC_SYNCT2_MASK (3 << )
+#define TIMER_SYNC_SYNCT2_MASK (3 <<)
#define TIMER_SYNC_SYNCT2(n) ((uint32_t)(n) << TIMER_SYNC_SYNCT2_SHIFT)
#define TIMER_SYNC_SYNCT2_NONE TIMER_SYNC_SYNCT2(TIMER_SYNC_NONE)
#define TIMER_SYNC_SYNCT2_TA TIMER_SYNC_SYNCT2(TIMER_SYNC_TA)
#define TIMER_SYNC_SYNCT2_TB TIMER_SYNC_SYNCT2(TIMER_SYNC_TB)
#define TIMER_SYNC_SYNCT2_TATB TIMER_SYNC_SYNCT2(TIMER_SYNC_TATB)
#define TIMER_SYNC_SYNCT3_SHIFT (6) /* Synchronize GPTM timer 3 */
-#define TIMER_SYNC_SYNCT3_MASK (3 << )
+#define TIMER_SYNC_SYNCT3_MASK (3 <<)
#define TIMER_SYNC_SYNCT3(n) ((uint32_t)(n) << TIMER_SYNC_SYNCT3_SHIFT)
#define TIMER_SYNC_SYNCT3_NONE TIMER_SYNC_SYNCT3(TIMER_SYNC_NONE)
#define TIMER_SYNC_SYNCT3_TA TIMER_SYNC_SYNCT3(TIMER_SYNC_TA)
#define TIMER_SYNC_SYNCT3_TB TIMER_SYNC_SYNCT3(TIMER_SYNC_TB)
#define TIMER_SYNC_SYNCT3_TATB TIMER_SYNC_SYNCT3(TIMER_SYNC_TATB)
#define TIMER_SYNC_SYNCT4_SHIFT (8) /* Synchronize GPTM timer 4 */
-#define TIMER_SYNC_SYNCT4_MASK (3 << )
+#define TIMER_SYNC_SYNCT4_MASK (3 <<)
#define TIMER_SYNC_SYNCT4(n) ((uint32_t)(n) << TIMER_SYNC_SYNCT4_SHIFT)
#define TIMER_SYNC_SYNCT4_NONE TIMER_SYNC_SYNCT4(TIMER_SYNC_NONE)
#define TIMER_SYNC_SYNCT4_TA TIMER_SYNC_SYNCT4(TIMER_SYNC_TA)
#define TIMER_SYNC_SYNCT4_TB TIMER_SYNC_SYNCT4(TIMER_SYNC_TB)
#define TIMER_SYNC_SYNCT4_TATB TIMER_SYNC_SYNCT4(TIMER_SYNC_TATB)
#define TIMER_SYNC_SYNCT5_SHIFT (10) /* Synchronize GPTM timer 5 */
-#define TIMER_SYNC_SYNCT5_MASK (3 << )
+#define TIMER_SYNC_SYNCT5_MASK (3 <<)
#define TIMER_SYNC_SYNCT5(n) ((uint32_t)(n) << TIMER_SYNC_SYNCT5_SHIFT)
#define TIMER_SYNC_SYNCT5_NONE TIMER_SYNC_SYNCT5(TIMER_SYNC_NONE)
#define TIMER_SYNC_SYNCT5_TA TIMER_SYNC_SYNCT5(TIMER_SYNC_TA)
#define TIMER_SYNC_SYNCT5_TB TIMER_SYNC_SYNCT5(TIMER_SYNC_TB)
#define TIMER_SYNC_SYNCT5_TATB TIMER_SYNC_SYNCT5(TIMER_SYNC_TATB)
#define TIMER_SYNC_SYNCT6_SHIFT (12) /* Synchronize GPTM timer 6 */
-#define TIMER_SYNC_SYNCT6_MASK (3 << )
+#define TIMER_SYNC_SYNCT6_MASK (3 <<)
#define TIMER_SYNC_SYNCT6(n) ((uint32_t)(n) << TIMER_SYNC_SYNCT6_SHIFT)
#define TIMER_SYNC_SYNCT6_NONE TIMER_SYNC_SYNCT6(TIMER_SYNC_NONE)
#define TIMER_SYNC_SYNCT6_TA TIMER_SYNC_SYNCT6(TIMER_SYNC_TA)
#define TIMER_SYNC_SYNCT6_TB TIMER_SYNC_SYNCT6(TIMER_SYNC_TB)
#define TIMER_SYNC_SYNCT6_TATB TIMER_SYNC_SYNCT6(TIMER_SYNC_TATB)
#define TIMER_SYNC_SYNCT7_SHIFT (14) /* Synchronize GPTM timer 7 */
-#define TIMER_SYNC_SYNCT7_MASK (3 << )
+#define TIMER_SYNC_SYNCT7_MASK (3 <<)
#define TIMER_SYNC_SYNCT7(n) ((uint32_t)(n) << TIMER_SYNC_SYNCT7_SHIFT)
#define TIMER_SYNC_SYNCT7_NONE TIMER_SYNC_SYNCT7(TIMER_SYNC_NONE)
#define TIMER_SYNC_SYNCT7_TA TIMER_SYNC_SYNCT7(TIMER_SYNC_TA)
#define TIMER_SYNC_SYNCWT0_TB TIMER_SYNC_SYNCWT0(TIMER_SYNC_TB)
#define TIMER_SYNC_SYNCWT0_TATB TIMER_SYNC_SYNCWT0(TIMER_SYNC_TATB)
#define TIMER_SYNC_SYNCWT1_SHIFT (14) /* Synchronize WTM 32/64-Bit wide timer 1 */
-#define TIMER_SYNC_SYNCWT1_MASK (3 << )
+#define TIMER_SYNC_SYNCWT1_MASK (3 <<)
#define TIMER_SYNC_SYNCWT1(n) ((uint32_t)(n) << TIMER_SYNC_SYNCWT1_SHIFT)
#define TIMER_SYNC_SYNCWT1_NONE TIMER_SYNC_SYNCWT1(TIMER_SYNC_NONE)
#define TIMER_SYNC_SYNCWT1_TA TIMER_SYNC_SYNCWT1(TIMER_SYNC_TA)
#define TIMER_SYNC_SYNCWT1_TB TIMER_SYNC_SYNCWT1(TIMER_SYNC_TB)
#define TIMER_SYNC_SYNCWT1_TATB TIMER_SYNC_SYNCWT1(TIMER_SYNC_TATB)
#define TIMER_SYNC_SYNCWT2_SHIFT (16) /* Synchronize WTM 32/64-Bit wide timer 2 */
-#define TIMER_SYNC_SYNCWT2_MASK (3 << )
+#define TIMER_SYNC_SYNCWT2_MASK (3 <<)
#define TIMER_SYNC_SYNCWT2(n) ((uint32_t)(n) << TIMER_SYNC_SYNCWT2_SHIFT)
#define TIMER_SYNC_SYNCWT2_NONE TIMER_SYNC_SYNCWT2(TIMER_SYNC_NONE)
#define TIMER_SYNC_SYNCWT2_TA TIMER_SYNC_SYNCWT2(TIMER_SYNC_TA)
#define TIMER_SYNC_SYNCWT2_TB TIMER_SYNC_SYNCWT2(TIMER_SYNC_TB)
#define TIMER_SYNC_SYNCWT2_TATB TIMER_SYNC_SYNCWT2(TIMER_SYNC_TATB)
#define TIMER_SYNC_SYNCWT3_SHIFT (18) /* Synchronize WTM 32/64-Bit wide timer 3 */
-#define TIMER_SYNC_SYNCWT3_MASK (3 << )
+#define TIMER_SYNC_SYNCWT3_MASK (3 <<)
#define TIMER_SYNC_SYNCWT3(n) ((uint32_t)(n) << TIMER_SYNC_SYNCWT3_SHIFT)
#define TIMER_SYNC_SYNCWT3_NONE TIMER_SYNC_SYNCWT3(TIMER_SYNC_NONE)
#define TIMER_SYNC_SYNCWT3_TA TIMER_SYNC_SYNCWT3(TIMER_SYNC_TA)
#define TIMER_SYNC_SYNCWT3_TB TIMER_SYNC_SYNCWT3(TIMER_SYNC_TB)
#define TIMER_SYNC_SYNCWT3_TATB TIMER_SYNC_SYNCWT3(TIMER_SYNC_TATB)
#define TIMER_SYNC_SYNCWT4_SHIFT (20) /* Synchronize WTM 32/64-Bit wide timer 4 */
-#define TIMER_SYNC_SYNCWT4_MASK (3 << )
+#define TIMER_SYNC_SYNCWT4_MASK (3 <<)
#define TIMER_SYNC_SYNCWT4(n) ((uint32_t)(n) << TIMER_SYNC_SYNCWT4_SHIFT)
#define TIMER_SYNC_SYNCWT4_NONE TIMER_SYNC_SYNCWT4(TIMER_SYNC_NONE)
#define TIMER_SYNC_SYNCWT4_TA TIMER_SYNC_SYNCWT4(TIMER_SYNC_TA)
#define TIMER_SYNC_SYNCWT4_TB TIMER_SYNC_SYNCWT4(TIMER_SYNC_TB)
#define TIMER_SYNC_SYNCWT4_TATB TIMER_SYNC_SYNCWT4(TIMER_SYNC_TATB)
#define TIMER_SYNC_SYNCWT5_SHIFT (22) /* Synchronize WTM 32/64-Bit wide timer 5 */
-#define TIMER_SYNC_SYNCWT5_MASK (3 << )
+#define TIMER_SYNC_SYNCWT5_MASK (3 <<)
#define TIMER_SYNC_SYNCWT5(n) ((uint32_t)(n) << TIMER_SYNC_SYNCWT5_SHIFT)
#define TIMER_SYNC_SYNCWT5_NONE TIMER_SYNC_SYNCWT5(TIMER_SYNC_NONE)
#define TIMER_SYNC_SYNCWT5_TA TIMER_SYNC_SYNCWT5(TIMER_SYNC_TA)
/* Watchdog Timer Power Control */
#ifdef TIVA_SYSCON_PRWD
-#define tiva_wdt_periphrdy(p) tiva_periphrdy(TIVA_SYSCON_PRWD,SYSCON_PRWD(p))
+#define tiva_wdt_periphrdy(p) tiva_periphrdy(TIVA_SYSCON_PRWD, SYSCON_PRWD(p))
#else
#define tiva_wdt_periphrdy(p) (true)
#endif
*/
enum tiva_timer32mode_e {
- TIMER16_MODE = 0, /* Use 16-bit timers, not 32-bit timer */
- TIMER32_MODE_ONESHOT, /* 32-bit programmable one-shot timer */
- TIMER32_MODE_PERIODIC, /* 32-bit programmable periodic timer */
- TIMER32_MODE_RTC /* 32-bit RTC with external 32.768-KHz input */
+ TIMER16_MODE = 0, /* Use 16-bit timers, not 32-bit timer */
+ TIMER32_MODE_ONESHOT, /* 32-bit programmable one-shot timer */
+ TIMER32_MODE_PERIODIC, /* 32-bit programmable periodic timer */
+ TIMER32_MODE_RTC /* 32-bit RTC with external 32.768-KHz input */
};
/* This enumeration identifies all supported 16-bit timer A/B modes of
*/
enum tiva_timer16mode_e {
- TIMER16_MODE_NONE = 0, /* 16-bit timer not used */
- TIMER16_MODE_ONESHOT, /* 16-bit programmable one-shot timer */
- TIMER16_MODE_PERIODIC, /* 16-bit programmable periodic timer */
- TIMER16_MODE_COUNT_CAPTURE, /* 16-bit input edge-count capture mode w/8-bit prescaler */
- TIMER16_MODE_TIME_CAPTURE, /* 16-bit input time capture mode w/8-bit prescaler */
- TIMER16_MODE_PWM /* 16-bit PWM output mode w/8-bit prescaler */
+ TIMER16_MODE_NONE = 0, /* 16-bit timer not used */
+ TIMER16_MODE_ONESHOT, /* 16-bit programmable one-shot timer */
+ TIMER16_MODE_PERIODIC, /* 16-bit programmable periodic timer */
+ TIMER16_MODE_COUNT_CAPTURE, /* 16-bit input edge-count capture mode w/8-bit prescaler */
+ TIMER16_MODE_TIME_CAPTURE, /* 16-bit input time capture mode w/8-bit prescaler */
+ TIMER16_MODE_PWM /* 16-bit PWM output mode w/8-bit prescaler */
};
/* This type represents the opaque handler returned by tiva_gptm_configure() */
/* Often defined and re-defined macros */
#ifndef MIN
-#define MIN(a,b) (((a) < (b)) ? (a) : (b))
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#ifndef MAX
-#define MAX(a,b) (((a) > (b)) ? (a) : (b))
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
-#define ALC5658_DEFAULT_SAMPRATE 48000
-#define ALC5658_DEFAULT_NCHANNELS 2
-#define ALC5658_DEFAULT_BPSAMP 16
+#define ALC5658_DEFAULT_SAMPRATE 48000
+#define ALC5658_DEFAULT_NCHANNELS 2
+#define ALC5658_DEFAULT_BPSAMP 16
#define FAIL 0xFFFF
/****************************************************************************
/* Commonly defined and redefined macros */
#ifndef MIN
-#define MIN(a,b) (((a) < (b)) ? (a) : (b))
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#ifndef MAX
-#define MAX(a,b) (((a) > (b)) ? (a) : (b))
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
/****************************************************************************
* @brief Structure of pthread mutex attr configuration
*/
struct pthread_mutexattr_s {
- uint8_t pshared : 1; /* PTHREAD_PROCESS_PRIVATE or PTHREAD_PROCESS_SHARED */
+ uint8_t pshared:1; /* PTHREAD_PROCESS_PRIVATE or PTHREAD_PROCESS_SHARED */
#ifdef CONFIG_PRIORITY_INHERITANCE
- uint8_t proto : 2; /* See PTHREAD_PRIO_* definitions */
+ uint8_t proto:2; /* See PTHREAD_PRIO_* definitions */
#endif
#ifdef CONFIG_PTHREAD_MUTEX_TYPES
- uint8_t type : 2; /* Type of the mutex. See PTHREAD_MUTEX_* definitions */
+ uint8_t type:2; /* Type of the mutex. See PTHREAD_MUTEX_* definitions */
#endif
#if defined(CONFIG_PTHREAD_MUTEX_BOTH) || defined(CONFIG_PTHREAD_MUTEX_ROBUST)
- uint8_t robust : 1; /* PTHREAD_MUTEX_STALLED or PTHREAD_MUTEX_ROBUST */
+ uint8_t robust:1; /* PTHREAD_MUTEX_STALLED or PTHREAD_MUTEX_ROBUST */
#endif
};
typedef struct pthread_mutexattr_s pthread_mutexattr_t;
#if defined(CONFIG_PTHREAD_MUTEX_TYPES) && !defined(CONFIG_PTHREAD_MUTEX_UNSAFE)
#define PTHREAD_MUTEX_INITIALIZER {NULL, SEM_INITIALIZER(1), -1, \
- __PTHREAD_MUTEX_DEFAULT_FLAGS, \
- PTHREAD_MUTEX_DEFAULT, 0}
+ __PTHREAD_MUTEX_DEFAULT_FLAGS, \
+ PTHREAD_MUTEX_DEFAULT, 0}
#elif defined(CONFIG_PTHREAD_MUTEX_TYPES)
#define PTHREAD_MUTEX_INITIALIZER {SEM_INITIALIZER(1), -1, \
- PTHREAD_MUTEX_DEFAULT, 0}
+ PTHREAD_MUTEX_DEFAULT, 0}
#elif !defined(CONFIG_PTHREAD_MUTEX_UNSAFE)
#define PTHREAD_MUTEX_INITIALIZER {NULL, SEM_INITIALIZER(1), -1,\
- __PTHREAD_MUTEX_DEFAULT_FLAGS}
+ __PTHREAD_MUTEX_DEFAULT_FLAGS}
#else
#define PTHREAD_MUTEX_INITIALIZER {SEM_INITIALIZER(1), -1}
#endif
typedef int pthread_rwlockattr_t;
-#define PTHREAD_RWLOCK_INITIALIZER {PTHREAD_MUTEX_INITIALIZER, \
- PTHREAD_COND_INITIALIZER, \
- 0, 0, false}
+#define PTHREAD_RWLOCK_INITIALIZER {PTHREAD_MUTEX_INITIALIZER, \
+ PTHREAD_COND_INITIALIZER, \
+ 0, 0, false}
/* Forware references */
#define ADC_SETUP(dev) ((dev)->ad_ops->ao_setup((dev)))
#define ADC_SHUTDOWN(dev) ((dev)->ad_ops->ao_shutdown((dev)))
#define ADC_RXINT(dev) ((dev)->ad_ops->ao_rxint((dev)))
-#define ADC_IOCTL(dev,cmd,arg) ((dev)->ad_ops->ao_ioctl((dev),(cmd),(arg)))
+#define ADC_IOCTL(dev, cmd, arg) ((dev)->ad_ops->ao_ioctl((dev), (cmd), (arg)))
/****************************************************************************
* Public Types
sem_t af_sem; /* Counting semaphore */
uint8_t af_head; /* Index to the head [IN] index in the circular buffer */
uint8_t af_tail; /* Index to the tail [OUT] index in the circular buffer */
- /* Circular buffer of CAN messages */
+ /* Circular buffer of CAN messages */
struct dac_msg_s af_buffer[CONFIG_DAC_FIFOSIZE];
};
/* Helper macros ************************************************************/
-#define ALC5658_ATTACH(s,isr,arg) ((s)->attach(s,isr,arg))
-#define ALC5658_DETACH(s) ((s)->attach(s,NULL,NULL))
-#define ALC5658_ENABLE(s) ((s)->enable(s,true))
-#define ALC5658_DISABLE(s) ((s)->enable(s,false))
-#define ALC5658_RESTORE(s,e) ((s)->enable(s,e))
+#define ALC5658_ATTACH(s, isr, arg) ((s)->attach(s, isr, arg))
+#define ALC5658_DETACH(s) ((s)->attach(s, NULL, NULL))
+#define ALC5658_ENABLE(s) ((s)->enable(s, true))
+#define ALC5658_DISABLE(s) ((s)->enable(s, false))
+#define ALC5658_RESTORE(s, e) ((s)->enable(s, e))
/****************************************************************************
* Public Types
* including file.
*/
-#define alc5658_dump_registers(d,m)
+#define alc5658_dump_registers(d, m)
#endif
/****************************************************************************
* including file.
*/
-#define alc5658_clock_analysis(d,m)
+#define alc5658_clock_analysis(d, m)
#endif
#undef EXTERN
*
****************************************************************************/
-#define I2S_RXSAMPLERATE(d,f) ((d)->ops->i2s_rxsamplerate(d,r))
+#define I2S_RXSAMPLERATE(d, f) ((d)->ops->i2s_rxsamplerate(d, r))
/****************************************************************************
* Name: I2S_RXDATAWIDTH
*
****************************************************************************/
-#define I2S_RXDATAWIDTH(d,b) ((d)->ops->i2s_rxdatawidth(d,b))
+#define I2S_RXDATAWIDTH(d, b) ((d)->ops->i2s_rxdatawidth(d, b))
/****************************************************************************
* Name: I2S_RECEIVE
*
****************************************************************************/
-#define I2S_RECEIVE(d,b,c,a,t) ((d)->ops->i2s_receive(d,b,c,a,t))
+#define I2S_RECEIVE(d, b, c, a, t) ((d)->ops->i2s_receive(d, b, c, a, t))
/****************************************************************************
* Name: I2S_TXSAMPLERATE
*
****************************************************************************/
-#define I2S_TXSAMPLERATE(d,f) ((d)->ops->i2s_txsamplerate(d,r))
+#define I2S_TXSAMPLERATE(d, f) ((d)->ops->i2s_txsamplerate(d, r))
/****************************************************************************
* Name: I2S_TXDATAWIDTH
*
****************************************************************************/
-#define I2S_TXDATAWIDTH(d,b) ((d)->ops->i2s_txdatawidth(d,b))
+#define I2S_TXDATAWIDTH(d, b) ((d)->ops->i2s_txdatawidth(d, b))
/****************************************************************************
* Name: I2S_SEND
*
****************************************************************************/
-#define I2S_SEND(d,b,c,a,t) ((d)->ops->i2s_send(d,b,c,a,t))
+#define I2S_SEND(d, b, c, a, t) ((d)->ops->i2s_send(d, b, c, a, t))
/****************************************************************************
* Public Types
#endif
#if !defined(_POSIX_SOURCE) && !defined(_POSIX_C_SOURCE) \
- && !defined(_XOPEN_SOURCE) && !defined(_GNU_SOURCE) \
- && !defined(_BSD_SOURCE) && !defined(__STRICT_ANSI__)
+ && !defined(_XOPEN_SOURCE) && !defined(_GNU_SOURCE) \
+ && !defined(_BSD_SOURCE) && !defined(__STRICT_ANSI__)
#define _BSD_SOURCE 1
#define _XOPEN_SOURCE 700
#endif
/* Audio driver ioctl definitions *************************************/
/* (see tinyara/audio/audio.h) */
-#define _AUDIOIOCVALID(c) (_IOC_TYPE(c)==_AUDIOIOCBASE)
-#define _AUDIOIOC(nr) _IOC(_AUDIOIOCBASE,nr)
+#define _AUDIOIOCVALID(c) (_IOC_TYPE(c) ==_AUDIOIOCBASE)
+#define _AUDIOIOC(nr) _IOC(_AUDIOIOCBASE, nr)
/* Application Config Data driver ioctl definitions *************************/
/* (see include/tinyara/configdata.h */
#endif
#define signbit(x) ( \
- sizeof(x) == sizeof(float) ? (int)(__FLOAT_BITS(x)>>31) : \
- sizeof(x) == sizeof(double) ? (int)(__DOUBLE_BITS(x)>>63) : \
- (int)(__DOUBLE_BITS(x)>>63) )
+ sizeof(x) == sizeof(float) ? (int)(__FLOAT_BITS(x) >> 31) : \
+ sizeof(x) == sizeof(double) ? (int)(__DOUBLE_BITS(x) >> 63) : \
+ (int)(__DOUBLE_BITS(x) >> 63))
/* Exponential and Logarithmic constants ************************************/
* structure be cast compatible with struct tm! They must be interchangeable.
*/
-struct rtc_time
-{
+struct rtc_time {
int tm_sec; /* Seconds (0-61, allows for leap seconds) */
int tm_min; /* Minutes (0-59) */
int tm_hour; /* Hours (0-23) */
* rdalarm() method.
*/
-struct rtc_rdalarm_s
-{
+struct rtc_rdalarm_s {
uint8_t id; /* Indicates the alarm being queried */
bool active; /* Alarm actively timing or disabled */
struct rtc_time time; /* Current RTC time (if enabled) */
/* Structure used with the RTC_SET_ALARM IOCTL command. */
-struct rtc_setalarm_s
-{
+struct rtc_setalarm_s {
uint8_t id; /* Indicates the alarm to be set */
uint8_t signo; /* Signal number for alarm notification */
pid_t pid; /* Identifies task to be notified (0=caller) */
/* Structure used with the RTC_SET_RELATIVE IOCTL command. */
-struct rtc_setrelative_s
-{
+struct rtc_setrelative_s {
uint8_t id; /* Indicates the alarm to be set */
uint8_t signo; /* Signal number for alarm notification */
pid_t pid; /* Identifies task to be notified (0=caller) */
/* Structure used with the setalarm method */
-struct lower_setalarm_s
-{
+struct lower_setalarm_s {
uint8_t id; /* Indicates the alarm to be set */
rtc_alarm_callback_t cb; /* Callback when the alarm expires */
FAR void *priv; /* Private argurment to accompany callback */
/* Structure used with the setrelative method */
-struct lower_setrelative_s
-{
+struct lower_setrelative_s {
uint8_t id; /* Indicates the alarm to be set */
rtc_alarm_callback_t cb; /* Callback when the alarm expires */
FAR void *priv; /* Private argurment to accompany callback */
*/
struct rtc_lowerhalf_s;
-struct rtc_ops_s
-{
+struct rtc_ops_s {
/* rdtime() returns the current RTC time. */
CODE int (*rdtime)(FAR struct rtc_lowerhalf_s *lower,
* struct rtc_lowerhalf_s that is understood by the upper half driver.
*/
-struct rtc_lowerhalf_s
-{
+struct rtc_lowerhalf_s {
/*
* This is the contained reference to the read-only, lower-half
* operations vtable (which may lie in FLASH or ROM)
/* Robust mutex support *********************************************/
#ifndef CONFIG_PTHREAD_MUTEX_UNSAFE
- FAR struct pthread_mutex_s *mhead; /* List of mutexes held by thread */
+ FAR struct pthread_mutex_s *mhead; /* List of mutexes held by thread */
#endif
/* Clean-up stack ***************************************************/
/* Inquiry */
#define SCSICMD_INQUIRYFLAGS_EVPD 0x01 /* Bit 0: EVPD */
- /* Bits 5-7: Peripheral Qualifier */
+ /* Bits 5-7: Peripheral Qualifier */
#define SCSIRESP_INQUIRYPQ_CONNECTED 0x00 /* 000: Device is connected */
#define SCSIRESP_INQUIRYPQ_NOTCONNECTED 0x20 /* 001: Device is NOT connected */
#define SCSIRESP_INQUIRYPQ_NOTCAPABLE 0x60 /* 011: LUN not supported */
- /* Bits 0-4: Peripheral Device */
+ /* Bits 0-4: Peripheral Device */
#define SCSIRESP_INQUIRYPD_DIRECTACCESS 0x00 /* Direct-access block device */
#define SCSIRESP_INQUIRYPD_SEQUENTIALACCESS 0x01 /* Sequential-access block device */
#define SCSIRESP_INQUIRYPD_PRINTER 0x02 /* Printer device */
#define SCSICMD_MODESENSE_PGCODEMASK 0x3f /* Bits 0-5: Page code */
#define SCSICMD_MODESENSE6_PCDEFAULT 0x80 /* Default values */
- /* Direct-access device page codes */
+ /* Direct-access device page codes */
#define SCSIRESP_MODESENSE_PGCCODE_VENDOR 0x00 /* Vendor-specific */
#define SCSIRESP_MODESENSE_PGCCODE_RWERROR 0x01 /* Read/Write error recovery mode page */
#define SCSIRESP_MODESENSE_PGCCODE_RECONNECT 0x02 /* Disconnect-reconnect mode page */
#define SCSIRESP_MODESENSE_PGCCODE_IE 0x1c /* Informational exceptions control mode page (0x1c/0x00) */
#define SCSIRESP_MODESENSE_PGCCODE_BC 0x1c /* Background control mode page (0x1c/0x01) */
#define SCSIRESP_MODESENSE_PGCCODE_RETURNALL 0x3f /* Return all mode pages */
- /* Direct-access caching mode page */
+ /* Direct-access caching mode page */
#define SCSIRESP_CACHINGMODEPG_PS 0x80 /* Byte 0, Bit 7: PS */
#define SCSIRESP_CACHINGMODEPG_SPF 0x60 /* Byte 0, Bit 6: SPF */
#define SCSIRESP_CACHINGMODEPG_IC 0x80 /* Byte 2, Bit 7: IC */
uint8_t qual2; /* 13: Additional sense code qualifier */
uint8_t fru; /* 14: Field replacement unit code */
uint8_t key[3]; /* 15-17: Sense key specific */
- /* 18-: Additional bytes may follow */
+ /* 18-: Additional bytes may follow */
};
#define SCSIRESP_FIXEDSENSEDATA_SIZEOF 18 /* Minimum size */
uint8_t version7[2]; /* 70-71: Version Descriptor 7 */
uint8_t version8[2]; /* 72-73: Version Descriptor 8 */
uint8_t reserved2[22]; /* 74-95: Reserved */
- /* 96-: Vendor-specific parameters may follow */
+ /* 96-: Vendor-specific parameters may follow */
};
#define SCSIRESP_INQUIRY_SIZEOF 36 /* Minimum size */
/* This is the type of the argument passed to the TCIOC_NOTIFICATION ioctl */
-struct timer_notify_s
-{
+struct timer_notify_s {
FAR void *arg; /* An argument to pass with the signal */
pid_t pid; /* The ID of the task/thread to receive the signal */
uint8_t signo; /* The signal number to use in the notification */
}
/****************************************************************************
- * Name: pthread_sem_take, pthread_sem_trytake, and
- * pthread_sem_give
+ * Name: pthread_sem_take, pthread_sem_trytake, and pthread_sem_give
*
* Description:
* Support managed access to the private data sets.
wdog->next = NULL;
wdog->flags = 0;
- }
- else {
+ } else {
/* If wdog is Null, g_wdnfree must be zero, else assert */
DEBUGASSERT(g_wdnfree == 0);
}
projects / rtos / tinyara.git / commitdiff