arm64: dts: imx8-ss-lsio: Add PWM interrupts

[ Upstream commit 6c32f75d67a8c1ea94295234db7c11a29c189e6f ]

The PWM interrupt is mandatory per imx-pwm.yaml.

Add them.

This also fixes the followig schema warning:

imx8qm-apalis-v1.1-ixora-v1.2.dtb: pwm@5d000000: 'oneOf' conditional failed, one must be fixed:
	'interrupts' is a required property
	'interrupts-extended' is a required property
	from schema $id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#

Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Stable-dep-of: d863a2f4f475 ("arm64: dts: freescale: imx8-ss-lsio: Fix #pwm-cells")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index ea8c93757521b3e6b93280e6f00326fe885e97f9..7b8bbf5e6a867c9ae81dc79bf886f5b63e3c1191 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -37,6 +37,7 @@ lsio_subsys: bus@5d000000 {
                assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
                assigned-clock-rates = <24000000>;
                #pwm-cells = <2>;
+               interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
 
@@ -49,6 +50,7 @@ lsio_subsys: bus@5d000000 {
                assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
                assigned-clock-rates = <24000000>;
                #pwm-cells = <2>;
+               interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
 
@@ -61,6 +63,7 @@ lsio_subsys: bus@5d000000 {
                assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
                assigned-clock-rates = <24000000>;
                #pwm-cells = <2>;
+               interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
 
@@ -73,6 +76,7 @@ lsio_subsys: bus@5d000000 {
                assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
                assigned-clock-rates = <24000000>;
                #pwm-cells = <2>;
+               interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };