Add mulslq and mululq opcodes

diff --git a/orc/opcodes.h b/orc/opcodes.h
index 4956a2e..b05cc6e 100644 (file)
--- a/orc/opcodes.h
+++ b/orc/opcodes.h
@@ -122,9 +122,11 @@ UNARY_LW(convussql, "ORC_CLAMP_SL((orc_uint64)%s)")
 UNARY_LW(convuusql, "ORC_CLAMP_UL((orc_uint64)%s)")
 
 BINARY_BW(mulsbw, "%s * %s")
-BINARY_BW(mulubw, "(orc_uint8)%s * (orc_uint8)%s")
+BINARY_BW(mulubw, "((orc_uint8)%s) * ((orc_uint8)%s)")
 BINARY_WL(mulswl, "%s * %s")
-BINARY_WL(muluwl, "(orc_uint16)%s * (orc_uint16)%s")
+BINARY_WL(muluwl, "((orc_uint16)%s) * ((orc_uint16)%s)")
+BINARY_LQ(mulslq, "((orc_int64)%s) * ((orc_int64)%s)")
+BINARY_LQ(mululq, "((orc_uint64)((orc_uint32)%s)) * ((orc_uint64)((orc_uint32)%s))")
 
 BINARY_LQ(mergelq, "((orc_uint64)%s & ORC_UINT64_C(0xffffffff)) | ((orc_uint64)%s << 32)")
 BINARY_WL(mergewl, "((orc_uint16)%s & 0x0000ffff) | ((orc_uint16)%s << 16)")

diff --git a/orc/orcemulateopcodes.c b/orc/orcemulateopcodes.c
index 7a25339..c618eee 100644 (file)
--- a/orc/orcemulateopcodes.c
+++ b/orc/orcemulateopcodes.c
@@ -3808,7 +3808,7 @@ emulate_mulubw (OrcOpcodeExecutor *ex, int offset, int n)
     /* 1: loadb */
     var33 = ptr5[i];
     /* 2: mulubw */
-    var34.i = (orc_uint8)var32 * (orc_uint8)var33;
+    var34.i = ((orc_uint8)var32) * ((orc_uint8)var33);
     /* 3: storew */
     ptr0[i] = var34;
   }
@@ -3866,7 +3866,7 @@ emulate_muluwl (OrcOpcodeExecutor *ex, int offset, int n)
     /* 1: loadw */
     var33 = ptr5[i];
     /* 2: muluwl */
-    var34.i = (orc_uint16)var32.i * (orc_uint16)var33.i;
+    var34.i = ((orc_uint16)var32.i) * ((orc_uint16)var33.i);
     /* 3: storel */
     ptr0[i] = var34;
   }
@@ -3874,6 +3874,64 @@ emulate_muluwl (OrcOpcodeExecutor *ex, int offset, int n)
 }
 
 void
+emulate_mulslq (OrcOpcodeExecutor *ex, int offset, int n)
+{
+  int i;
+  orc_union64 * ORC_RESTRICT ptr0;
+  const orc_union32 * ORC_RESTRICT ptr4;
+  const orc_union32 * ORC_RESTRICT ptr5;
+  orc_union32 var32;
+  orc_union32 var33;
+  orc_union64 var34;
+
+  ptr0 = (orc_union64 *)ex->dest_ptrs[0];
+  ptr4 = (orc_union32 *)ex->src_ptrs[0];
+  ptr5 = (orc_union32 *)ex->src_ptrs[1];
+
+
+  for (i = 0; i < n; i++) {
+    /* 0: loadl */
+    var32 = ptr4[i];
+    /* 1: loadl */
+    var33 = ptr5[i];
+    /* 2: mulslq */
+    var34.i = ((orc_int64)var32.i) * ((orc_int64)var33.i);
+    /* 3: storeq */
+    ptr0[i] = var34;
+  }
+
+}
+
+void
+emulate_mululq (OrcOpcodeExecutor *ex, int offset, int n)
+{
+  int i;
+  orc_union64 * ORC_RESTRICT ptr0;
+  const orc_union32 * ORC_RESTRICT ptr4;
+  const orc_union32 * ORC_RESTRICT ptr5;
+  orc_union32 var32;
+  orc_union32 var33;
+  orc_union64 var34;
+
+  ptr0 = (orc_union64 *)ex->dest_ptrs[0];
+  ptr4 = (orc_union32 *)ex->src_ptrs[0];
+  ptr5 = (orc_union32 *)ex->src_ptrs[1];
+
+
+  for (i = 0; i < n; i++) {
+    /* 0: loadl */
+    var32 = ptr4[i];
+    /* 1: loadl */
+    var33 = ptr5[i];
+    /* 2: mululq */
+    var34.i = ((orc_uint64)((orc_uint32)var32.i)) * ((orc_uint64)((orc_uint32)var33.i));
+    /* 3: storeq */
+    ptr0[i] = var34;
+  }
+
+}
+
+void
 emulate_accw (OrcOpcodeExecutor *ex, int offset, int n)
 {
   int i;

diff --git a/orc/orcemulateopcodes.h b/orc/orcemulateopcodes.h
index df84191..b02050e 100644 (file)
--- a/orc/orcemulateopcodes.h
+++ b/orc/orcemulateopcodes.h
@@ -150,6 +150,8 @@ void emulate_mulsbw (OrcOpcodeExecutor *ex, int i, int n);
 void emulate_mulubw (OrcOpcodeExecutor *ex, int i, int n);
 void emulate_mulswl (OrcOpcodeExecutor *ex, int i, int n);
 void emulate_muluwl (OrcOpcodeExecutor *ex, int i, int n);
+void emulate_mulslq (OrcOpcodeExecutor *ex, int i, int n);
+void emulate_mululq (OrcOpcodeExecutor *ex, int i, int n);
 void emulate_accw (OrcOpcodeExecutor *ex, int i, int n);
 void emulate_accl (OrcOpcodeExecutor *ex, int i, int n);
 void emulate_accsadubl (OrcOpcodeExecutor *ex, int i, int n);

diff --git a/orc/orcopcodes.c b/orc/orcopcodes.c
index 113d342..eda8610 100644 (file)
--- a/orc/orcopcodes.c
+++ b/orc/orcopcodes.c
@@ -443,10 +443,8 @@ static OrcStaticOpcode opcodes[] = {
   { "mulubw", 0, { 2 }, { 1, 1 }, emulate_mulubw },
   { "mulswl", 0, { 4 }, { 2, 2 }, emulate_mulswl },
   { "muluwl", 0, { 4 }, { 2, 2 }, emulate_muluwl },
-#ifdef ENABLE_64BIT
   { "mulslq", 0, { 8 }, { 4, 4 }, emulate_mulslq },
   { "mululq", 0, { 8 }, { 4, 4 }, emulate_mululq },
-#endif
 
   /* accumulators */
   { "accw", ORC_STATIC_OPCODE_ACCUMULATOR, { 2 }, { 2 }, emulate_accw },