gas/

2013-06-08  Catherine Moore  <clm@codesourcery.com>

	* config/tc-mips.c (is_opcode_valid):  Build ASE mask.
	(is_opcode_valid_16): Pass ase value to opcode_is_member.
	(append_insn): Change INSN_xxxx to ASE_xxxx.

include/
2013-06-08  Catherine Moore  <clm@codesourcery.com>

	* opcode/mips.h (mips_opcode): Add ase field.
	(INSN_ASE_MASK): Delete.
	(INSN_DSP): Rename to ASE_DSP.  Provide new value.
	(INSN_DSPR2): Rename to ASE_DSPR2.  Provide new value.
	(INSN_MCU): Rename to ASE_MCU.  Provide new value.
	(INSN_MDMX): Rename to ASE_MDMX.  Provide new value.
	(INSN_MIPS3d): Rename to ASE_MIPS3D.  Provide new value.
	(INSN_MT): Rename to ASE_MT.  Provide new value.
	(INSN_SMARTMIPS): Rename to ASE_SMARTMIPS.  Provide new value.
	(INSN_VIRT): Rename to ASE_VIRT.  Provide new value.
	(INSN_VIRT64): Rename to ASE_VIRT64.  Provide new value.
	(opcode_is_member): Add ase argument.  Check ase.

opcodes/
2013-06-08  Catherine Moore  <clm@codesourcery.com>
	    Richard Sandiford  <rdsandiford@googlemail.com>

	* micromips-opc.c (D32, D33, MC): Update definitions.
 	(micromips_opcodes):  Initialize ase field.
	* mips-dis.c (mips_arch_choice): Add ase field.
	(mips_arch_choices): Initialize ase field.
	(set_default_mips_dis_options): Declare and setup mips_ase.
	* mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
	MT32, MC): Update definitions.
	(mips_builtin_opcodes): Initialize ase field.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 5c63135..5e7964d 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2013-06-08  Catherine Moore  <clm@codesourcery.com>
+
+       * config/tc-mips.c (is_opcode_valid):  Build ASE mask.
+       (is_opcode_valid_16): Pass ase value to opcode_is_member.
+       (append_insn): Change INSN_xxxx to ASE_xxxx.
+
 2013-06-01  George Thomas <george.thomas@atmel.com>
 
         * gas/config/tc-avr.c: Change ISA for devices with USB support to

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 0e2e5f7..8ba290c 100644 (file)
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -2247,37 +2247,38 @@ reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
   return ok && reglist != 0;
 }
 
-/* Return TRUE if opcode MO is valid on the currently selected ISA and
-   architecture.  Use is_opcode_valid_16 for MIPS16 opcodes.  */
+/* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
+   and architecture.  Use is_opcode_valid_16 for MIPS16 opcodes.  */
 
 static bfd_boolean
 is_opcode_valid (const struct mips_opcode *mo)
 {
   int isa = mips_opts.isa;
+  int ase = 0;
   int fp_s, fp_d;
 
   if (mips_opts.ase_mdmx)
-    isa |= INSN_MDMX;
+    ase |= ASE_MDMX;
   if (mips_opts.ase_dsp)
-    isa |= INSN_DSP;
+    ase |= ASE_DSP;
   if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
-    isa |= INSN_DSP64;
+    ase |= ASE_DSP64;
   if (mips_opts.ase_dspr2)
-    isa |= INSN_DSPR2;
+    ase |= ASE_DSPR2;
   if (mips_opts.ase_mt)
-    isa |= INSN_MT;
+    ase |= ASE_MT;
   if (mips_opts.ase_mips3d)
-    isa |= INSN_MIPS3D;
+    ase |= ASE_MIPS3D;
   if (mips_opts.ase_smartmips)
-    isa |= INSN_SMARTMIPS;
+    ase |= ASE_SMARTMIPS;
   if (mips_opts.ase_mcu)
-    isa |= INSN_MCU;
+    ase |= ASE_MCU;
   if (mips_opts.ase_virt)
-    isa |= INSN_VIRT;
+    ase |= ASE_VIRT;
   if (mips_opts.ase_virt && ISA_SUPPORTS_VIRT64_ASE)
-    isa |= INSN_VIRT64;
+    ase |= ASE_VIRT64;
 
-  if (!opcode_is_member (mo, isa, mips_opts.arch))
+  if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
     return FALSE;
 
   /* Check whether the instruction or macro requires single-precision or
@@ -2309,7 +2310,7 @@ is_opcode_valid (const struct mips_opcode *mo)
 static bfd_boolean
 is_opcode_valid_16 (const struct mips_opcode *mo)
 {
-  return opcode_is_member (mo, mips_opts.isa, mips_opts.arch);
+  return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
 }
 
 /* Return TRUE if the size of the microMIPS opcode MO matches one
@@ -4395,7 +4396,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
             && (mips_opts.at || mips_pic == NO_PIC)
             /* Don't relax BPOSGE32/64 as they have no complementing
                branches.  */
-            && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)));
+            && !(ip->insn_mo->ase & (ASE_DSP64 | ASE_DSP)));
 
   if (!HAVE_CODE_COMPRESSION
       && address_expr

diff --git a/include/ChangeLog b/include/ChangeLog
index 4d02320..df6716b 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,18 @@
+2013-06-08  Catherine Moore  <clm@codesourcery.com>
+
+       * opcode/mips.h (mips_opcode): Add ase field.
+       (INSN_ASE_MASK): Delete.
+       (INSN_DSP): Rename to ASE_DSP.  Provide new value.
+       (INSN_DSPR2): Rename to ASE_DSPR2.  Provide new value.
+       (INSN_MCU): Rename to ASE_MCU.  Provide new value.
+       (INSN_MDMX): Rename to ASE_MDMX.  Provide new value.
+       (INSN_MIPS3d): Rename to ASE_MIPS3D.  Provide new value.
+       (INSN_MT): Rename to ASE_MT.  Provide new value.
+       (INSN_SMARTMIPS): Rename to ASE_SMARTMIPS.  Provide new value.
+       (INSN_VIRT): Rename to ASE_VIRT.  Provide new value.
+       (INSN_VIRT64): Rename to ASE_VIRT64.  Provide new value.
+       (opcode_is_member): Add ase argument.  Check ase.
+
 2013-05-06  Paul Brook  <paul@codesourcery.com>
 
         include/elf/

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 07259ea..0bb9c11 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -357,6 +357,9 @@ struct mips_opcode
   /* A collection of bits describing the instruction sets of which this
      instruction or macro is a member. */
   unsigned long membership;
+  /* A collection of bits describing the ASE of which this instruction
+     or macro is a member.  */
+  unsigned long ase;
   /* A collection of bits describing the instruction sets of which this
      instruction or macro is not a member.  */
   unsigned long exclusions;
@@ -733,20 +736,9 @@ static const unsigned int mips_isa_table[] =
 /* Masks used for MIPS-defined ASEs.  */
 #define INSN_ASE_MASK            0x3c00f0d0
 
-/* DSP ASE */ 
-#define INSN_DSP                  0x00001000
-#define INSN_DSP64                0x00002000
-
 /* MIPS R5900 instruction */
 #define INSN_5900                 0x00004000
 
-/* Virtualization ASE */
-#define INSN_VIRT                0x00000080
-#define INSN_VIRT64              0x00000040
-
-/* MIPS-3D ASE */
-#define INSN_MIPS3D               0x00008000
-
 /* MIPS R4650 instruction.  */
 #define INSN_4650                 0x00010000
 /* LSI R4010 instruction.  */
@@ -768,14 +760,6 @@ static const unsigned int mips_isa_table[] =
 /* NEC VR5500 instruction.  */
 #define INSN_5500                0x02000000
 
-/* MDMX ASE */ 
-#define INSN_MDMX                 0x04000000
-/* MT ASE */
-#define INSN_MT                   0x08000000
-/* SmartMIPS ASE  */
-#define INSN_SMARTMIPS            0x10000000
-/* DSP R2 ASE  */
-#define INSN_DSPR2                0x20000000
 /* ST Microelectronics Loongson 2E.  */
 #define INSN_LOONGSON_2E          0x40000000
 /* ST Microelectronics Loongson 2F.  */
@@ -783,10 +767,26 @@ static const unsigned int mips_isa_table[] =
 /* Loongson 3A.  */
 #define INSN_LOONGSON_3A          0x00000400
 /* RMI Xlr instruction */
-#define INSN_XLR                 0x00000020
+#define INSN_XLR                 0x00000020
 
+/* DSP ASE */
+#define ASE_DSP                        0x00000001
+#define ASE_DSP64              0x00000002
+/* DSP R2 ASE  */
+#define ASE_DSPR2              0x00000004
 /* MCU (MicroController) ASE */
-#define INSN_MCU                 0x00000010
+#define ASE_MCU                        0x00000010
+/* MDMX ASE */
+#define ASE_MDMX               0x00000020
+/* MIPS-3D ASE */
+#define ASE_MIPS3D             0x00000040
+/* MT ASE */
+#define ASE_MT                 0x00000080
+/* SmartMIPS ASE  */
+#define ASE_SMARTMIPS          0x00000100
+/* Virtualization ASE */
+#define ASE_VIRT               0x00000200
+#define ASE_VIRT64             0x00000400
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
@@ -923,7 +923,7 @@ cpu_is_member (int cpu, unsigned int mask)
    if instruction INSN is available to the given ISA and CPU. */
 
 static inline bfd_boolean
-opcode_is_member (const struct mips_opcode *insn, int isa, int cpu)
+opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
 {
   if (!cpu_is_member (cpu, insn->exclusions))
     {
@@ -935,7 +935,7 @@ opcode_is_member (const struct mips_opcode *insn, int isa, int cpu)
        return TRUE;
 
       /* Test for ASE compatibility.  */
-      if (((isa & ~INSN_ISA_MASK) & (insn->membership & ~INSN_ISA_MASK)) != 0)
+      if ((ase & insn->ase) != 0)
        return TRUE;
 
       /* Test for processor-specific extensions.  */

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 570ebb9..35ce609 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,15 @@
+2013-06-08  Catherine Moore  <clm@codesourcery.com>
+           Richard Sandiford  <rdsandiford@googlemail.com>
+
+       * micromips-opc.c (D32, D33, MC): Update definitions.
+       (micromips_opcodes):  Initialize ase field.
+       * mips-dis.c (mips_arch_choice): Add ase field.
+       (mips_arch_choices): Initialize ase field.
+       (set_default_mips_dis_options): Declare and setup mips_ase.
+       * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
+       MT32, MC): Update definitions.
+       (mips_builtin_opcodes): Initialize ase field.
+
 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 
        * s390-opc.txt (flogr): Require a register pair destination.

diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 5e71dfb..e7294de 100644 (file)
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -104,18 +104,18 @@
 #define RD_a   RD_HILO         /* Read DSP accumulators (reuse RD_HILO).  */
 #define MOD_a  WR_a|RD_a
 #define DSP_VOLA INSN_NO_DELAY_SLOT
-#define D32    INSN_DSP
-#define D33    INSN_DSPR2
+#define D32    ASE_DSP
+#define D33    ASE_DSPR2
 
 /* MIPS MCU (MicroController) ASE support.  */
-#define MC     INSN_MCU
+#define MC     ASE_MCU
 
 const struct mips_opcode micromips_opcodes[] =
 {
 /* These instructions appear first so that the disassembler will find
    them first.  The assemblers uses a hash table based on the
    instruction name anyhow.  */
-/* name,    args,      match,      mask,       pinfo,                  pinfo2,         membership,     [exclusions] */
+/* name,    args,      match,      mask,       pinfo,                  pinfo2,         membership,     [ase],  [exclusions] */
 {"pref",    "k,~(b)",  0x60002000, 0xfc00f000, RD_b,                   0,              I1      },
 {"pref",    "k,o(b)",  0,    (int) M_PREF_OB,  INSN_MACRO,             0,              I1      },
 {"pref",    "k,A(b)",  0,    (int) M_PREF_AB,  INSN_MACRO,             0,              I1      },
@@ -149,9 +149,9 @@ const struct mips_opcode micromips_opcodes[] =
 {"abs.d",   "T,V",     0x5400237b, 0xfc00ffff, WR_T|RD_S|FP_D,         0,              I1      },
 {"abs.s",   "T,V",     0x5400037b, 0xfc00ffff, WR_T|RD_S|FP_S,         0,              I1      },
 {"abs.ps",  "T,V",     0x5400437b, 0xfc00ffff, WR_T|RD_S|FP_D,         0,              I1      },
-{"aclr",    "\\,~(b)", 0x2000b000, 0xff00f000, SM|RD_b|NODS,           0,              MC      },
-{"aclr",    "\\,o(b)", 0,    (int) M_ACLR_OB,  INSN_MACRO,             0,              MC      },
-{"aclr",    "\\,A(b)", 0,    (int) M_ACLR_AB,  INSN_MACRO,             0,              MC      },
+{"aclr",    "\\,~(b)", 0x2000b000, 0xff00f000, SM|RD_b|NODS,           0,              0,      MC      },
+{"aclr",    "\\,o(b)", 0,    (int) M_ACLR_OB,  INSN_MACRO,             0,              0,      MC      },
+{"aclr",    "\\,A(b)", 0,    (int) M_ACLR_AB,  INSN_MACRO,             0,              0,      MC      },
 {"add",     "d,v,t",   0x00000110, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"add",     "t,r,I",   0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1      },
 {"add.d",   "D,V,T",   0x54000130, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
@@ -184,9 +184,9 @@ const struct mips_opcode micromips_opcodes[] =
 {"and",     "t,r,I",   0,    (int) M_AND_I,    INSN_MACRO,             0,              I1      },
 {"andi",    "md,mc,mC",            0x2c00,     0xfc00, 0,                      WR_md|RD_mc,    I1      },
 {"andi",    "t,r,i",   0xd0000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
-{"aset",    "\\,~(b)", 0x20003000, 0xff00f000, SM|RD_b|NODS,           0,              MC      },
-{"aset",    "\\,o(b)", 0,    (int) M_ASET_OB,  INSN_MACRO,             0,              MC      },
-{"aset",    "\\,A(b)", 0,    (int) M_ASET_AB,  INSN_MACRO,             0,              MC      },
+{"aset",    "\\,~(b)", 0x20003000, 0xff00f000, SM|RD_b|NODS,           0,              0,      MC      },
+{"aset",    "\\,o(b)", 0,    (int) M_ASET_OB,  INSN_MACRO,             0,              0,      MC      },
+{"aset",    "\\,A(b)", 0,    (int) M_ASET_AB,  INSN_MACRO,             0,              0,      MC      },
 /* b is at the top of the table.  */
 /* bal is at the top of the table.  */
 {"bc1f",    "p",       0x43800000, 0xffff0000, CBD|RD_CC|FP_S,         0,              I1      },
@@ -525,7 +525,7 @@ const struct mips_opcode micromips_opcodes[] =
 {"floor.w.d", "T,V",   0x54004b3b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D,    0,              I1      },
 {"floor.w.s", "T,V",   0x54000b3b, 0xfc00ffff, WR_T|RD_S|FP_S,         0,              I1      },
 {"ins",     "t,r,+A,+B", 0x0000000c, 0xfc00003f, WR_t|RD_s,            0,              I1      },
-{"iret",    "",                0x0000d37c, 0xffffffff, NODS,                   0,              MC      },
+{"iret",    "",                0x0000d37c, 0xffffffff, NODS,                   0,              0,      MC      },
 {"jr",      "mj",          0x4580,     0xffe0, UBD,                    RD_mj,          I1      },
 {"jr",      "s",       0x00000f3c, 0xffe0ffff, UBD|RD_s,               BD32,           I1      }, /* jalr */
 {"jrs",     "s",       0x00004f3c, 0xffe0ffff, UBD|RD_s,               BD16,           I1      }, /* jalrs */
@@ -658,12 +658,12 @@ const struct mips_opcode micromips_opcodes[] =
 {"flush",   "t,A(b)",  0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I1      },
 {"lwxs",    "d,t(b)",  0x00000118, 0xfc0007ff, RD_b|RD_t|WR_d,         0,              I1      },
 {"madd",    "s,t",     0x0000cb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              I1      },
-{"madd",    "7,s,t",   0x00000abc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              D32     },
+{"madd",    "7,s,t",   0x00000abc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              0,      D32     },
 {"madd.d",  "D,R,S,T", 0x54000009, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I1      },
 {"madd.s",  "D,R,S,T", 0x54000001, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I1      },
 {"madd.ps", "D,R,S,T", 0x54000011, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I1      },
 {"maddu",   "s,t",     0x0000db3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              I1      },
-{"maddu",   "7,s,t",   0x00001abc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              D32     },
+{"maddu",   "7,s,t",   0x00001abc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              0,      D32     },
 {"mfc0",    "t,G",     0x000000fc, 0xfc00ffff, WR_t|RD_C0,             0,              I1      },
 {"mfc0",    "t,+D",    0x000000fc, 0xfc00c7ff, WR_t|RD_C0,             0,              I1      },
 {"mfc0",    "t,G,H",   0x000000fc, 0xfc00c7ff, WR_t|RD_C0,             0,              I1      },
@@ -675,10 +675,10 @@ const struct mips_opcode micromips_opcodes[] =
 {"mfhc2",   "t,G",     0x00008d3c, 0xfc00ffff, WR_t|RD_C2,             0,              I1      },
 {"mfhi",    "mj",          0x4600,     0xffe0, RD_HI,                  WR_mj,          I1      },
 {"mfhi",    "s",       0x00000d7c, 0xffe0ffff, WR_s|RD_HI,             0,              I1      },
-{"mfhi",    "s,7",     0x0000007c, 0xffe03fff, WR_s|RD_HI,             0,              D32     },
+{"mfhi",    "s,7",     0x0000007c, 0xffe03fff, WR_s|RD_HI,             0,              0,      D32     },
 {"mflo",    "mj",          0x4640,     0xffe0, RD_LO,                  WR_mj,          I1      },
 {"mflo",    "s",       0x00001d7c, 0xffe0ffff, WR_s|RD_LO,             0,              I1      },
-{"mflo",    "s,7",     0x0000107c, 0xffe03fff, WR_s|RD_LO,             0,              D32     },
+{"mflo",    "s,7",     0x0000107c, 0xffe03fff, WR_s|RD_LO,             0,              0,      D32     },
 {"mov.d",   "T,S",     0x5400207b, 0xfc00ffff, WR_T|RD_S|FP_D,         0,              I1      },
 {"mov.s",   "T,S",     0x5400007b, 0xfc00ffff, WR_T|RD_S|FP_S,         0,              I1      },
 {"mov.ps",  "T,S",     0x5400407b, 0xfc00ffff, WR_T|RD_S|FP_D,         0,              I1      },
@@ -700,12 +700,12 @@ const struct mips_opcode micromips_opcodes[] =
 {"movz.s",  "D,S,t",   0x54000078, 0xfc0007ff, WR_D|RD_S|RD_t|FP_S,    0,              I1      },
 {"movz.ps", "D,S,t",   0x54000278, 0xfc0007ff, WR_D|RD_S|RD_t|FP_D,    0,              I1      },
 {"msub",    "s,t",     0x0000eb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              I1      },
-{"msub",    "7,s,t",   0x00002abc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              D32     },
+{"msub",    "7,s,t",   0x00002abc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              0,      D32     },
 {"msub.d",  "D,R,S,T", 0x54000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I1      },
 {"msub.s",  "D,R,S,T", 0x54000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I1      },
 {"msub.ps", "D,R,S,T", 0x54000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I1      },
 {"msubu",   "s,t",     0x0000fb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              I1      },
-{"msubu",   "7,s,t",   0x00003abc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              D32     },
+{"msubu",   "7,s,t",   0x00003abc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              0,      D32     },
 {"mtc0",    "t,G",     0x000002fc, 0xfc00ffff, RD_t|WR_C0|WR_CC,       0,              I1      },
 {"mtc0",    "t,+D",    0x000002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC,       0,              I1      },
 {"mtc0",    "t,G,H",   0x000002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC,       0,              I1      },
@@ -716,9 +716,9 @@ const struct mips_opcode micromips_opcodes[] =
 {"mthc1",   "t,G",     0x5400383b, 0xfc00ffff, RD_t|WR_S|FP_D,         0,              I1      },
 {"mthc2",   "t,G",     0x00009d3c, 0xfc00ffff, RD_t|WR_C2|WR_CC,       0,              I1      },
 {"mthi",    "s",       0x00002d7c, 0xffe0ffff, RD_s|WR_HI,             0,              I1      },
-{"mthi",    "s,7",     0x0000207c, 0xffe03fff, RD_s|WR_HI,             0,              D32     },
+{"mthi",    "s,7",     0x0000207c, 0xffe03fff, RD_s|WR_HI,             0,              0,      D32     },
 {"mtlo",    "s",       0x00003d7c, 0xffe0ffff, RD_s|WR_LO,             0,              I1      },
-{"mtlo",    "s,7",     0x0000307c, 0xffe03fff, RD_s|WR_LO,             0,              D32     },
+{"mtlo",    "s,7",     0x0000307c, 0xffe03fff, RD_s|WR_LO,             0,              0,      D32     },
 {"mul",     "d,v,t",   0x00000210, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              I1      },
 {"mul",     "d,v,I",   0,    (int) M_MUL_I,    INSN_MACRO,             0,              I1      },
 {"mul.d",   "D,V,T",   0x540001b0, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
@@ -729,9 +729,9 @@ const struct mips_opcode micromips_opcodes[] =
 {"mulou",   "d,v,t",   0,    (int) M_MULOU,    INSN_MACRO,             0,              I1      },
 {"mulou",   "d,v,I",   0,    (int) M_MULOU_I,  INSN_MACRO,             0,              I1      },
 {"mult",    "s,t",     0x00008b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
-{"mult",    "7,s,t",   0x00000cbc, 0xfc003fff, WR_a|RD_s|RD_t,         0,              D32     },
+{"mult",    "7,s,t",   0x00000cbc, 0xfc003fff, WR_a|RD_s|RD_t,         0,              0,      D32     },
 {"multu",   "s,t",     0x00009b3c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
-{"multu",   "7,s,t",   0x00001cbc, 0xfc003fff, WR_a|RD_s|RD_t,         0,              D32     },
+{"multu",   "7,s,t",   0x00001cbc, 0xfc003fff, WR_a|RD_s|RD_t,         0,              0,      D32     },
 {"neg",     "d,w",     0x00000190, 0xfc1f07ff, WR_d|RD_t,              0,              I1      }, /* sub 0 */
 {"negu",    "d,w",     0x000001d0, 0xfc1f07ff, WR_d|RD_t,              0,              I1      }, /* subu 0 */
 {"neg.d",   "T,V",     0x54002b7b, 0xfc00ffff, WR_T|RD_S|FP_D,         0,              I1      },
@@ -984,159 +984,159 @@ const struct mips_opcode micromips_opcodes[] =
 {"xor",     "t,r,I",   0,    (int) M_XOR_I,    INSN_MACRO,             0,              I1      },
 {"xori",    "t,r,i",   0x70000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
 /* MIPS DSP ASE.  */
-{"absq_s.ph", "t,s",   0x0000113c, 0xfc00ffff, WR_t|RD_s,              0,              D32     },
-{"absq_s.w", "t,s",    0x0000213c, 0xfc00ffff, WR_t|RD_s,              0,              D32     },
-{"addq.ph", "d,s,t",   0x0000000d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"addq_s.ph", "d,s,t", 0x0000040d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"addq_s.w", "d,s,t",  0x00000305, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"addsc",   "d,s,t",   0x00000385, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"addu.qb", "d,s,t",   0x000000cd, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"addu_s.qb", "d,s,t", 0x000004cd, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"addwc",   "d,s,t",   0x000003c5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"bitrev",  "t,s",     0x0000313c, 0xfc00ffff, WR_t|RD_s,              0,              D32     },
-{"bposge32", "p",      0x43600000, 0xffff0000, CBD,                    0,              D32     },
-{"cmp.eq.ph", "s,t",   0x00000005, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
-{"cmpgu.eq.qb", "d,s,t", 0x000000c5, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D32     },
-{"cmp.le.ph", "s,t",   0x00000085, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
-{"cmpgu.le.qb", "d,s,t", 0x00000145, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D32     },
-{"cmp.lt.ph", "s,t",   0x00000045, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
-{"cmpgu.lt.qb", "d,s,t", 0x00000105, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D32     },
-{"cmpu.eq.qb", "s,t",  0x00000245, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
-{"cmpu.le.qb", "s,t",  0x000002c5, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
-{"cmpu.lt.qb", "s,t",  0x00000285, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
-{"dpaq_sa.l.w", "7,s,t", 0x000012bc, 0xfc003fff, MOD_a|RD_s|RD_t,      0,              D32     },
-{"dpaq_s.w.ph", "7,s,t", 0x000002bc, 0xfc003fff, MOD_a|RD_s|RD_t,      0,              D32     },
-{"dpau.h.qbl", "7,s,t", 0x000020bc, 0xfc003fff,        MOD_a|RD_s|RD_t,        0,              D32     },
-{"dpau.h.qbr", "7,s,t", 0x000030bc, 0xfc003fff,        MOD_a|RD_s|RD_t,        0,              D32     },
-{"dpsq_sa.l.w", "7,s,t", 0x000016bc, 0xfc003fff, MOD_a|RD_s|RD_t,      0,              D32     },
-{"dpsq_s.w.ph", "7,s,t", 0x000006bc, 0xfc003fff, MOD_a|RD_s|RD_t,      0,              D32     },
-{"dpsu.h.qbl", "7,s,t",        0x000024bc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              D32     },
-{"dpsu.h.qbr", "7,s,t",        0x000034bc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              D32     },
-{"extpdp",  "t,7,6",   0x0000367c, 0xfc003fff, WR_t|RD_a|DSP_VOLA,     0,              D32     },
-{"extpdpv", "t,7,s",   0x000038bc, 0xfc003fff, WR_t|RD_a|RD_s|DSP_VOLA, 0,             D32     },
-{"extp",    "t,7,6",   0x0000267c, 0xfc003fff, WR_t|RD_a,              0,              D32     },
-{"extpv",   "t,7,s",   0x000028bc, 0xfc003fff, WR_t|RD_a|RD_s,         0,              D32     },
-{"extr_rs.w", "t,7,6", 0x00002e7c, 0xfc003fff, WR_t|RD_a,              0,              D32     },
-{"extr_r.w", "t,7,6",  0x00001e7c, 0xfc003fff, WR_t|RD_a,              0,              D32     },
-{"extr_s.h", "t,7,6",  0x00003e7c, 0xfc003fff, WR_t|RD_a,              0,              D32     },
-{"extrv_rs.w", "t,7,s",        0x00002ebc, 0xfc003fff, WR_t|RD_a|RD_s,         0,              D32     },
-{"extrv_r.w", "t,7,s", 0x00001ebc, 0xfc003fff, WR_t|RD_a|RD_s,         0,              D32     },
-{"extrv_s.h", "t,7,s", 0x00003ebc, 0xfc003fff, WR_t|RD_a|RD_s,         0,              D32     },
-{"extrv.w", "t,7,s",   0x00000ebc, 0xfc003fff, WR_t|RD_a|RD_s,         0,              D32     },
-{"extr.w",  "t,7,6",   0x00000e7c, 0xfc003fff, WR_t|RD_a,              0,              D32     },
-{"insv",    "t,s",     0x0000413c, 0xfc00ffff, WR_t|RD_s,              0,              D32     },
-{"lbux",    "d,t(b)",  0x00000225, 0xfc0007ff, WR_d|RD_b|RD_t,         0,              D32     },
-{"lhx",     "d,t(b)",  0x00000165, 0xfc0007ff, WR_d|RD_b|RD_t,         0,              D32     },
-{"lwx",     "d,t(b)",  0x000001a5, 0xfc0007ff, WR_d|RD_b|RD_t,         0,              D32     },
-{"maq_sa.w.phl", "7,s,t", 0x00003a7c, 0xfc003fff, MOD_a|RD_s|RD_t,     0,              D32     },
-{"maq_sa.w.phr", "7,s,t", 0x00002a7c, 0xfc003fff, MOD_a|RD_s|RD_t,     0,              D32     },
-{"maq_s.w.phl", "7,s,t", 0x00001a7c, 0xfc003fff, MOD_a|RD_s|RD_t,      0,              D32     },
-{"maq_s.w.phr", "7,s,t", 0x00000a7c, 0xfc003fff, MOD_a|RD_s|RD_t,      0,              D32     },
-{"modsub",  "d,s,t",   0x00000295, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"mthlip",  "s,7",     0x0000027c, 0xffe03fff, RD_s|MOD_a|DSP_VOLA,    0,              D32     },
-{"muleq_s.w.phl", "d,s,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D32     },
-{"muleq_s.w.phr", "d,s,t", 0x00000065, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D32     },
-{"muleu_s.ph.qbl", "d,s,t", 0x00000095, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,         D32     },
-{"muleu_s.ph.qbr", "d,s,t", 0x000000d5, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,         D32     },
-{"mulq_rs.ph", "d,s,t",        0x00000115, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D32     },
-{"mulsaq_s.w.ph", "7,s,t", 0x00003cbc, 0xfc003fff, MOD_a|RD_s|RD_t,    0,              D32     },
-{"packrl.ph", "d,s,t", 0x000001ad, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"pick.ph", "d,s,t",   0x0000022d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"pick.qb", "d,s,t",   0x000001ed, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"precequ.ph.qbla", "t,s", 0x0000733c, 0xfc00ffff, WR_t|RD_s,          0,              D32     },
-{"precequ.ph.qbl", "t,s", 0x0000713c, 0xfc00ffff, WR_t|RD_s,           0,              D32     },
-{"precequ.ph.qbra", "t,s", 0x0000933c, 0xfc00ffff, WR_t|RD_s,          0,              D32     },
-{"precequ.ph.qbr", "t,s", 0x0000913c, 0xfc00ffff, WR_t|RD_s,           0,              D32     },
-{"preceq.w.phl", "t,s",        0x0000513c, 0xfc00ffff, WR_t|RD_s,              0,              D32     },
-{"preceq.w.phr", "t,s",        0x0000613c, 0xfc00ffff, WR_t|RD_s,              0,              D32     },
-{"preceu.ph.qbla", "t,s", 0x0000b33c, 0xfc00ffff, WR_t|RD_s,           0,              D32     },
-{"preceu.ph.qbl", "t,s", 0x0000b13c, 0xfc00ffff, WR_t|RD_s,            0,              D32     },
-{"preceu.ph.qbra", "t,s",0x0000d33c, 0xfc00ffff, WR_t|RD_s,            0,              D32     },
-{"preceu.ph.qbr", "t,s", 0x0000d13c, 0xfc00ffff, WR_t|RD_s,            0,              D32     },
-{"precrq.ph.w", "d,s,t", 0x000000ed, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D32     },
-{"precrq.qb.ph", "d,s,t", 0x000000ad, 0xfc0007ff, WR_d|RD_s|RD_t,      0,              D32     },
-{"precrq_rs.ph.w", "d,s,t", 0x0000012d, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D32     },
-{"precrqu_s.qb.ph", "d,s,t", 0x0000016d, 0xfc0007ff, WR_d|RD_s|RD_t,   0,              D32     },
-{"raddu.w.qb", "t,s",  0x0000f13c, 0xfc00ffff, WR_t|RD_s,              0,              D32     },
-{"rddsp",   "t",       0x000fc67c, 0xfc1fffff, WR_t,                   0,              D32     },
-{"rddsp",   "t,8",     0x0000067c, 0xfc103fff, WR_t,                   0,              D32     },
-{"repl.ph", "d,@",     0x0000003d, 0xfc0007ff, WR_d,                   0,              D32     },
-{"repl.qb", "t,5",     0x000005fc, 0xfc001fff, WR_t,                   0,              D32     },
-{"replv.ph", "t,s",    0x0000033c, 0xfc00ffff, WR_t|RD_s,              0,              D32     },
-{"replv.qb", "t,s",    0x0000133c, 0xfc00ffff, WR_t|RD_s,              0,              D32     },
-{"shilo",   "7,0",     0x0000001d, 0xffc03fff, MOD_a,                  0,              D32     },
-{"shilov",  "7,s",     0x0000127c, 0xffe03fff, MOD_a|RD_s,             0,              D32     },
-{"shll.ph", "t,s,4",   0x000003b5, 0xfc000fff, WR_t|RD_s,              0,              D32     },
-{"shll.qb", "t,s,3",   0x0000087c, 0xfc001fff, WR_t|RD_s,              0,              D32     },
-{"shll_s.ph", "t,s,4", 0x00000bb5, 0xfc000fff, WR_t|RD_s,              0,              D32     },
-{"shll_s.w", "t,s,^",  0x000003f5, 0xfc0007ff, WR_t|RD_s,              0,              D32     },
-{"shllv.ph", "d,t,s",  0x0000038d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"shllv.qb", "d,t,s",  0x00000395, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"shllv_s.ph", "d,t,s",        0x0000078d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"shllv_s.w", "d,t,s", 0x000003d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"shra.ph", "t,s,4",   0x00000335, 0xfc000fff, WR_t|RD_s,              0,              D32     },
-{"shra_r.ph", "t,s,4", 0x00000735, 0xfc000fff, WR_t|RD_s,              0,              D32     },
-{"shra_r.w", "t,s,^",  0x000002f5, 0xfc0007ff, WR_t|RD_s,              0,              D32     },
-{"shrav.ph", "d,t,s",  0x0000018d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"shrav_r.ph", "d,t,s",        0x0000058d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"shrav_r.w", "d,t,s", 0x000002d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"shrl.qb", "t,s,3",   0x0000187c, 0xfc001fff, WR_t|RD_s,              0,              D32     },
-{"shrlv.qb", "d,t,s",  0x00000355, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"subq.ph", "d,s,t",   0x0000020d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"subq_s.ph", "d,s,t", 0x0000060d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"subq_s.w", "d,s,t",  0x00000345, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"subu.qb", "d,s,t",   0x000002cd, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"subu_s.qb", "d,s,t", 0x000006cd, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"wrdsp",   "t",       0x000fd67c, 0xfc1fffff, RD_t|DSP_VOLA,          0,              D32     },
-{"wrdsp",   "t,8",     0x0000167c, 0xfc103fff, RD_t|DSP_VOLA,          0,              D32     },
+{"absq_s.ph", "t,s",   0x0000113c, 0xfc00ffff, WR_t|RD_s,              0,              0,      D32     },
+{"absq_s.w", "t,s",    0x0000213c, 0xfc00ffff, WR_t|RD_s,              0,              0,      D32     },
+{"addq.ph", "d,s,t",   0x0000000d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"addq_s.ph", "d,s,t", 0x0000040d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"addq_s.w", "d,s,t",  0x00000305, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"addsc",   "d,s,t",   0x00000385, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"addu.qb", "d,s,t",   0x000000cd, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"addu_s.qb", "d,s,t", 0x000004cd, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"addwc",   "d,s,t",   0x000003c5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"bitrev",  "t,s",     0x0000313c, 0xfc00ffff, WR_t|RD_s,              0,              0,      D32     },
+{"bposge32", "p",      0x43600000, 0xffff0000, CBD,                    0,              0,      D32     },
+{"cmp.eq.ph", "s,t",   0x00000005, 0xfc00ffff, RD_s|RD_t,              0,              0,      D32     },
+{"cmpgu.eq.qb", "d,s,t", 0x000000c5, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              0,      D32     },
+{"cmp.le.ph", "s,t",   0x00000085, 0xfc00ffff, RD_s|RD_t,              0,              0,      D32     },
+{"cmpgu.le.qb", "d,s,t", 0x00000145, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              0,      D32     },
+{"cmp.lt.ph", "s,t",   0x00000045, 0xfc00ffff, RD_s|RD_t,              0,              0,      D32     },
+{"cmpgu.lt.qb", "d,s,t", 0x00000105, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              0,      D32     },
+{"cmpu.eq.qb", "s,t",  0x00000245, 0xfc00ffff, RD_s|RD_t,              0,              0,      D32     },
+{"cmpu.le.qb", "s,t",  0x000002c5, 0xfc00ffff, RD_s|RD_t,              0,              0,      D32     },
+{"cmpu.lt.qb", "s,t",  0x00000285, 0xfc00ffff, RD_s|RD_t,              0,              0,      D32     },
+{"dpaq_sa.l.w", "7,s,t", 0x000012bc, 0xfc003fff, MOD_a|RD_s|RD_t,      0,              0,      D32     },
+{"dpaq_s.w.ph", "7,s,t", 0x000002bc, 0xfc003fff, MOD_a|RD_s|RD_t,      0,              0,      D32     },
+{"dpau.h.qbl", "7,s,t", 0x000020bc, 0xfc003fff,        MOD_a|RD_s|RD_t,        0,              0,      D32     },
+{"dpau.h.qbr", "7,s,t", 0x000030bc, 0xfc003fff,        MOD_a|RD_s|RD_t,        0,              0,      D32     },
+{"dpsq_sa.l.w", "7,s,t", 0x000016bc, 0xfc003fff, MOD_a|RD_s|RD_t,      0,              0,      D32     },
+{"dpsq_s.w.ph", "7,s,t", 0x000006bc, 0xfc003fff, MOD_a|RD_s|RD_t,      0,              0,      D32     },
+{"dpsu.h.qbl", "7,s,t",        0x000024bc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              0,      D32     },
+{"dpsu.h.qbr", "7,s,t",        0x000034bc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              0,      D32     },
+{"extpdp",  "t,7,6",   0x0000367c, 0xfc003fff, WR_t|RD_a|DSP_VOLA,     0,              0,      D32     },
+{"extpdpv", "t,7,s",   0x000038bc, 0xfc003fff, WR_t|RD_a|RD_s|DSP_VOLA, 0,             0,      D32     },
+{"extp",    "t,7,6",   0x0000267c, 0xfc003fff, WR_t|RD_a,              0,              0,      D32     },
+{"extpv",   "t,7,s",   0x000028bc, 0xfc003fff, WR_t|RD_a|RD_s,         0,              0,      D32     },
+{"extr_rs.w", "t,7,6", 0x00002e7c, 0xfc003fff, WR_t|RD_a,              0,              0,      D32     },
+{"extr_r.w", "t,7,6",  0x00001e7c, 0xfc003fff, WR_t|RD_a,              0,              0,      D32     },
+{"extr_s.h", "t,7,6",  0x00003e7c, 0xfc003fff, WR_t|RD_a,              0,              0,      D32     },
+{"extrv_rs.w", "t,7,s",        0x00002ebc, 0xfc003fff, WR_t|RD_a|RD_s,         0,              0,      D32     },
+{"extrv_r.w", "t,7,s", 0x00001ebc, 0xfc003fff, WR_t|RD_a|RD_s,         0,              0,      D32     },
+{"extrv_s.h", "t,7,s", 0x00003ebc, 0xfc003fff, WR_t|RD_a|RD_s,         0,              0,      D32     },
+{"extrv.w", "t,7,s",   0x00000ebc, 0xfc003fff, WR_t|RD_a|RD_s,         0,              0,      D32     },
+{"extr.w",  "t,7,6",   0x00000e7c, 0xfc003fff, WR_t|RD_a,              0,              0,      D32     },
+{"insv",    "t,s",     0x0000413c, 0xfc00ffff, WR_t|RD_s,              0,              0,      D32     },
+{"lbux",    "d,t(b)",  0x00000225, 0xfc0007ff, WR_d|RD_b|RD_t,         0,              0,      D32     },
+{"lhx",     "d,t(b)",  0x00000165, 0xfc0007ff, WR_d|RD_b|RD_t,         0,              0,      D32     },
+{"lwx",     "d,t(b)",  0x000001a5, 0xfc0007ff, WR_d|RD_b|RD_t,         0,              0,      D32     },
+{"maq_sa.w.phl", "7,s,t", 0x00003a7c, 0xfc003fff, MOD_a|RD_s|RD_t,     0,              0,      D32     },
+{"maq_sa.w.phr", "7,s,t", 0x00002a7c, 0xfc003fff, MOD_a|RD_s|RD_t,     0,              0,      D32     },
+{"maq_s.w.phl", "7,s,t", 0x00001a7c, 0xfc003fff, MOD_a|RD_s|RD_t,      0,              0,      D32     },
+{"maq_s.w.phr", "7,s,t", 0x00000a7c, 0xfc003fff, MOD_a|RD_s|RD_t,      0,              0,      D32     },
+{"modsub",  "d,s,t",   0x00000295, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"mthlip",  "s,7",     0x0000027c, 0xffe03fff, RD_s|MOD_a|DSP_VOLA,    0,              0,      D32     },
+{"muleq_s.w.phl", "d,s,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          0,      D32     },
+{"muleq_s.w.phr", "d,s,t", 0x00000065, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          0,      D32     },
+{"muleu_s.ph.qbl", "d,s,t", 0x00000095, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,         0,      D32     },
+{"muleu_s.ph.qbr", "d,s,t", 0x000000d5, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,         0,      D32     },
+{"mulq_rs.ph", "d,s,t",        0x00000115, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              0,      D32     },
+{"mulsaq_s.w.ph", "7,s,t", 0x00003cbc, 0xfc003fff, MOD_a|RD_s|RD_t,    0,              0,      D32     },
+{"packrl.ph", "d,s,t", 0x000001ad, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"pick.ph", "d,s,t",   0x0000022d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"pick.qb", "d,s,t",   0x000001ed, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"precequ.ph.qbla", "t,s", 0x0000733c, 0xfc00ffff, WR_t|RD_s,          0,              0,      D32     },
+{"precequ.ph.qbl", "t,s", 0x0000713c, 0xfc00ffff, WR_t|RD_s,           0,              0,      D32     },
+{"precequ.ph.qbra", "t,s", 0x0000933c, 0xfc00ffff, WR_t|RD_s,          0,              0,      D32     },
+{"precequ.ph.qbr", "t,s", 0x0000913c, 0xfc00ffff, WR_t|RD_s,           0,              0,      D32     },
+{"preceq.w.phl", "t,s",        0x0000513c, 0xfc00ffff, WR_t|RD_s,              0,              0,      D32     },
+{"preceq.w.phr", "t,s",        0x0000613c, 0xfc00ffff, WR_t|RD_s,              0,              0,      D32     },
+{"preceu.ph.qbla", "t,s", 0x0000b33c, 0xfc00ffff, WR_t|RD_s,           0,              0,      D32     },
+{"preceu.ph.qbl", "t,s", 0x0000b13c, 0xfc00ffff, WR_t|RD_s,            0,              0,      D32     },
+{"preceu.ph.qbra", "t,s",0x0000d33c, 0xfc00ffff, WR_t|RD_s,            0,              0,      D32     },
+{"preceu.ph.qbr", "t,s", 0x0000d13c, 0xfc00ffff, WR_t|RD_s,            0,              0,      D32     },
+{"precrq.ph.w", "d,s,t", 0x000000ed, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              0,      D32     },
+{"precrq.qb.ph", "d,s,t", 0x000000ad, 0xfc0007ff, WR_d|RD_s|RD_t,      0,              0,      D32     },
+{"precrq_rs.ph.w", "d,s,t", 0x0000012d, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              0,      D32     },
+{"precrqu_s.qb.ph", "d,s,t", 0x0000016d, 0xfc0007ff, WR_d|RD_s|RD_t,   0,              0,      D32     },
+{"raddu.w.qb", "t,s",  0x0000f13c, 0xfc00ffff, WR_t|RD_s,              0,              0,      D32     },
+{"rddsp",   "t",       0x000fc67c, 0xfc1fffff, WR_t,                   0,              0,      D32     },
+{"rddsp",   "t,8",     0x0000067c, 0xfc103fff, WR_t,                   0,              0,      D32     },
+{"repl.ph", "d,@",     0x0000003d, 0xfc0007ff, WR_d,                   0,              0,      D32     },
+{"repl.qb", "t,5",     0x000005fc, 0xfc001fff, WR_t,                   0,              0,      D32     },
+{"replv.ph", "t,s",    0x0000033c, 0xfc00ffff, WR_t|RD_s,              0,              0,      D32     },
+{"replv.qb", "t,s",    0x0000133c, 0xfc00ffff, WR_t|RD_s,              0,              0,      D32     },
+{"shilo",   "7,0",     0x0000001d, 0xffc03fff, MOD_a,                  0,              0,      D32     },
+{"shilov",  "7,s",     0x0000127c, 0xffe03fff, MOD_a|RD_s,             0,              0,      D32     },
+{"shll.ph", "t,s,4",   0x000003b5, 0xfc000fff, WR_t|RD_s,              0,              0,      D32     },
+{"shll.qb", "t,s,3",   0x0000087c, 0xfc001fff, WR_t|RD_s,              0,              0,      D32     },
+{"shll_s.ph", "t,s,4", 0x00000bb5, 0xfc000fff, WR_t|RD_s,              0,              0,      D32     },
+{"shll_s.w", "t,s,^",  0x000003f5, 0xfc0007ff, WR_t|RD_s,              0,              0,      D32     },
+{"shllv.ph", "d,t,s",  0x0000038d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"shllv.qb", "d,t,s",  0x00000395, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"shllv_s.ph", "d,t,s",        0x0000078d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"shllv_s.w", "d,t,s", 0x000003d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"shra.ph", "t,s,4",   0x00000335, 0xfc000fff, WR_t|RD_s,              0,              0,      D32     },
+{"shra_r.ph", "t,s,4", 0x00000735, 0xfc000fff, WR_t|RD_s,              0,              0,      D32     },
+{"shra_r.w", "t,s,^",  0x000002f5, 0xfc0007ff, WR_t|RD_s,              0,              0,      D32     },
+{"shrav.ph", "d,t,s",  0x0000018d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"shrav_r.ph", "d,t,s",        0x0000058d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"shrav_r.w", "d,t,s", 0x000002d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"shrl.qb", "t,s,3",   0x0000187c, 0xfc001fff, WR_t|RD_s,              0,              0,      D32     },
+{"shrlv.qb", "d,t,s",  0x00000355, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"subq.ph", "d,s,t",   0x0000020d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"subq_s.ph", "d,s,t", 0x0000060d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"subq_s.w", "d,s,t",  0x00000345, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"subu.qb", "d,s,t",   0x000002cd, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"subu_s.qb", "d,s,t", 0x000006cd, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"wrdsp",   "t",       0x000fd67c, 0xfc1fffff, RD_t|DSP_VOLA,          0,              0,      D32     },
+{"wrdsp",   "t,8",     0x0000167c, 0xfc103fff, RD_t|DSP_VOLA,          0,              0,      D32     },
 /* MIPS DSP ASE Rev2.  */
-{"absq_s.qb", "t,s",   0x0000013c, 0xfc00ffff, WR_t|RD_s,              0,              D33     },
-{"addqh.ph", "d,s,t",  0x0000004d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"addqh_r.ph", "d,s,t",        0x0000044d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"addqh.w", "d,s,t",   0x0000008d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"addqh_r.w", "d,s,t", 0x0000048d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"addu.ph", "d,s,t",   0x0000010d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"addu_s.ph", "d,s,t", 0x0000050d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"adduh.qb", "d,s,t",  0x0000014d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"adduh_r.qb", "d,s,t",        0x0000054d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"append",  "t,s,h",   0x00000215, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33     },
-{"balign",  "t,s,I",   0,    (int) M_BALIGN,   INSN_MACRO,             0,              D33     },
-{"balign",  "t,s,2",   0x000008bc, 0xfc003fff, WR_t|RD_t|RD_s,         0,              D33     },
-{"cmpgdu.eq.qb", "d,s,t", 0x00000185, 0xfc0007ff, WR_d|RD_s|RD_t,      0,              D33     },
-{"cmpgdu.lt.qb", "d,s,t", 0x000001c5, 0xfc0007ff, WR_d|RD_s|RD_t,      0,              D33     },
-{"cmpgdu.le.qb", "d,s,t", 0x00000205, 0xfc0007ff, WR_d|RD_s|RD_t,      0,              D33     },
-{"dpa.w.ph", "7,s,t",  0x000000bc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              D33     },
-{"dpaqx_s.w.ph", "7,s,t", 0x000022bc, 0xfc003fff, MOD_a|RD_s|RD_t,     0,              D33     },
-{"dpaqx_sa.w.ph", "7,s,t", 0x000032bc, 0xfc003fff, MOD_a|RD_s|RD_t,    0,              D33     },
-{"dpax.w.ph", "7,s,t", 0x000010bc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              D33     },
-{"dps.w.ph", "7,s,t",  0x000004bc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              D33     },
-{"dpsqx_s.w.ph", "7,s,t", 0x000026bc, 0xfc003fff, MOD_a|RD_s|RD_t,     0,              D33     },
-{"dpsqx_sa.w.ph", "7,s,t", 0x000036bc, 0xfc003fff, MOD_a|RD_s|RD_t,    0,              D33     },
-{"dpsx.w.ph", "7,s,t", 0x000014bc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              D33     },
-{"mul.ph",  "d,s,t",   0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
-{"mul_s.ph", "d,s,t",  0x0000042d, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
-{"mulq_rs.w", "d,s,t", 0x00000195, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
-{"mulq_s.ph", "d,s,t", 0x00000155, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
-{"mulq_s.w", "d,s,t",  0x000001d5, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
-{"mulsa.w.ph", "7,s,t",        0x00002cbc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              D33     },
-{"precr.qb.ph", "d,s,t", 0x0000006d, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
-{"precr_sra.ph.w", "t,s,h", 0x000003cd, 0xfc0007ff, WR_t|RD_t|RD_s,    0,              D33     },
-{"precr_sra_r.ph.w", "t,s,h", 0x000007cd, 0xfc0007ff, WR_t|RD_t|RD_s,  0,              D33     },
-{"prepend", "t,s,h",   0x00000255, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33     },
-{"shra.qb", "t,s,3",   0x000001fc, 0xfc001fff, WR_t|RD_s,              0,              D33     },
-{"shra_r.qb", "t,s,3", 0x000011fc, 0xfc001fff, WR_t|RD_s,              0,              D33     },
-{"shrav.qb", "d,t,s",  0x000001cd, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"shrav_r.qb", "d,t,s",        0x000005cd, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"shrl.ph", "t,s,4",   0x000003fc, 0xfc000fff, WR_t|RD_s,              0,              D33     },
-{"shrlv.ph", "d,t,s",  0x00000315, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"subu.ph", "d,s,t",   0x0000030d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"subu_s.ph", "d,s,t", 0x0000070d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"subuh.qb", "d,s,t",  0x0000034d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"subuh_r.qb", "d,s,t",        0x0000074d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"subqh.ph", "d,s,t",  0x0000024d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"subqh_r.ph", "d,s,t",        0x0000064d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"subqh.w", "d,s,t",   0x0000028d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"subqh_r.w", "d,s,t", 0x0000068d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
+{"absq_s.qb", "t,s",   0x0000013c, 0xfc00ffff, WR_t|RD_s,              0,              0,      D33     },
+{"addqh.ph", "d,s,t",  0x0000004d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"addqh_r.ph", "d,s,t",        0x0000044d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"addqh.w", "d,s,t",   0x0000008d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"addqh_r.w", "d,s,t", 0x0000048d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"addu.ph", "d,s,t",   0x0000010d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"addu_s.ph", "d,s,t", 0x0000050d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"adduh.qb", "d,s,t",  0x0000014d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"adduh_r.qb", "d,s,t",        0x0000054d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"append",  "t,s,h",   0x00000215, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              0,      D33     },
+{"balign",  "t,s,I",   0,    (int) M_BALIGN,   INSN_MACRO,             0,              0,      D33     },
+{"balign",  "t,s,2",   0x000008bc, 0xfc003fff, WR_t|RD_t|RD_s,         0,              0,      D33     },
+{"cmpgdu.eq.qb", "d,s,t", 0x00000185, 0xfc0007ff, WR_d|RD_s|RD_t,      0,              0,      D33     },
+{"cmpgdu.lt.qb", "d,s,t", 0x000001c5, 0xfc0007ff, WR_d|RD_s|RD_t,      0,              0,      D33     },
+{"cmpgdu.le.qb", "d,s,t", 0x00000205, 0xfc0007ff, WR_d|RD_s|RD_t,      0,              0,      D33     },
+{"dpa.w.ph", "7,s,t",  0x000000bc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              0,      D33     },
+{"dpaqx_s.w.ph", "7,s,t", 0x000022bc, 0xfc003fff, MOD_a|RD_s|RD_t,     0,              0,      D33     },
+{"dpaqx_sa.w.ph", "7,s,t", 0x000032bc, 0xfc003fff, MOD_a|RD_s|RD_t,    0,              0,      D33     },
+{"dpax.w.ph", "7,s,t", 0x000010bc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              0,      D33     },
+{"dps.w.ph", "7,s,t",  0x000004bc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              0,      D33     },
+{"dpsqx_s.w.ph", "7,s,t", 0x000026bc, 0xfc003fff, MOD_a|RD_s|RD_t,     0,              0,      D33     },
+{"dpsqx_sa.w.ph", "7,s,t", 0x000036bc, 0xfc003fff, MOD_a|RD_s|RD_t,    0,              0,      D33     },
+{"dpsx.w.ph", "7,s,t", 0x000014bc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              0,      D33     },
+{"mul.ph",  "d,s,t",   0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              0,      D33     },
+{"mul_s.ph", "d,s,t",  0x0000042d, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              0,      D33     },
+{"mulq_rs.w", "d,s,t", 0x00000195, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              0,      D33     },
+{"mulq_s.ph", "d,s,t", 0x00000155, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              0,      D33     },
+{"mulq_s.w", "d,s,t",  0x000001d5, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              0,      D33     },
+{"mulsa.w.ph", "7,s,t",        0x00002cbc, 0xfc003fff, MOD_a|RD_s|RD_t,        0,              0,      D33     },
+{"precr.qb.ph", "d,s,t", 0x0000006d, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              0,      D33     },
+{"precr_sra.ph.w", "t,s,h", 0x000003cd, 0xfc0007ff, WR_t|RD_t|RD_s,    0,              0,      D33     },
+{"precr_sra_r.ph.w", "t,s,h", 0x000007cd, 0xfc0007ff, WR_t|RD_t|RD_s,  0,              0,      D33     },
+{"prepend", "t,s,h",   0x00000255, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              0,      D33     },
+{"shra.qb", "t,s,3",   0x000001fc, 0xfc001fff, WR_t|RD_s,              0,              0,      D33     },
+{"shra_r.qb", "t,s,3", 0x000011fc, 0xfc001fff, WR_t|RD_s,              0,              0,      D33     },
+{"shrav.qb", "d,t,s",  0x000001cd, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"shrav_r.qb", "d,t,s",        0x000005cd, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"shrl.ph", "t,s,4",   0x000003fc, 0xfc000fff, WR_t|RD_s,              0,              0,      D33     },
+{"shrlv.ph", "d,t,s",  0x00000315, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"subu.ph", "d,s,t",   0x0000030d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"subu_s.ph", "d,s,t", 0x0000070d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"subuh.qb", "d,s,t",  0x0000034d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"subuh_r.qb", "d,s,t",        0x0000074d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"subqh.ph", "d,s,t",  0x0000024d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"subqh_r.ph", "d,s,t",        0x0000064d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"subqh.w", "d,s,t",   0x0000028d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"subqh_r.w", "d,s,t", 0x0000068d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
 };
 
 const int bfd_micromips_num_opcodes =

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 834fd5c..3395f1a 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -517,6 +517,7 @@ struct mips_arch_choice
   unsigned long bfd_mach;
   int processor;
   int isa;
+  int ase;
   const char * const *cp0_names;
   const struct mips_cp0sel_name *cp0sel_names;
   unsigned int cp0sel_names_len;
@@ -525,56 +526,56 @@ struct mips_arch_choice
 
 const struct mips_arch_choice mips_arch_choices[] =
 {
-  { "numeric", 0, 0, 0, 0,
+  { "numeric", 0, 0, 0, 0, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
 
-  { "r3000",   1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
+  { "r3000",   1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0,
     mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
-  { "r3900",   1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
+  { "r3900",   1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "r4000",   1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
+  { "r4000",   1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0,
     mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
-  { "r4010",   1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
+  { "r4010",   1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "vr4100",  1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
+  { "vr4100",  1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "vr4111",  1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
+  { "vr4111",  1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "vr4120",  1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
+  { "vr4120",  1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "r4300",   1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
+  { "r4300",   1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "r4400",   1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
+  { "r4400",   1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0,
     mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
-  { "r4600",   1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
+  { "r4600",   1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "r4650",   1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
+  { "r4650",   1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "r5000",   1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
+  { "r5000",   1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "vr5400",  1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
+  { "vr5400",  1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "vr5500",  1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
+  { "vr5500",  1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "r5900",   1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3,
+  { "r5900",   1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0,
     mips_cp0_names_r5900, NULL, 0, mips_hwr_names_numeric },
-  { "r6000",   1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
+  { "r6000",   1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "rm7000",  1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
+  { "rm7000",  1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "rm9000",  1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
+  { "rm9000",  1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "r8000",   1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
+  { "r8000",   1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "r10000",  1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
+  { "r10000",  1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "r12000",  1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
+  { "r12000",  1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "r14000",  1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4,
+  { "r14000",  1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "r16000",  1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4,
+  { "r16000",  1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-  { "mips5",   1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
+  { "mips5",   1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
 
   /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
@@ -583,64 +584,66 @@ const struct mips_arch_choice mips_arch_choices[] =
      MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
      page 1.  */
   { "mips32",  1, bfd_mach_mipsisa32, CPU_MIPS32,
-    ISA_MIPS32 | INSN_SMARTMIPS,
+    ISA_MIPS32,  ASE_SMARTMIPS,
     mips_cp0_names_mips3264,
     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
     mips_hwr_names_numeric },
 
   { "mips32r2",        1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
-    (ISA_MIPS32R2 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
-     | INSN_MIPS3D | INSN_MT | INSN_MCU | INSN_VIRT),
+    ISA_MIPS32R2,
+    (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_MIPS3D | ASE_MT
+     | ASE_MCU | ASE_VIRT),
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_hwr_names_mips3264r2 },
 
   /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs.  */
   { "mips64",  1, bfd_mach_mipsisa64, CPU_MIPS64,
-    ISA_MIPS64 | INSN_MIPS3D | INSN_MDMX,
+    ISA_MIPS64,  ASE_MIPS3D | ASE_MDMX,
     mips_cp0_names_mips3264,
     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
     mips_hwr_names_numeric },
 
   { "mips64r2",        1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
-    (ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
-     | INSN_DSP64 | INSN_MT | INSN_MDMX | INSN_MCU | INSN_VIRT | INSN_VIRT64),
+    ISA_MIPS64R2,
+    (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_MT | ASE_MDMX
+     | ASE_MCU | ASE_VIRT | ASE_VIRT64),
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_hwr_names_mips3264r2 },
 
   { "sb1",     1, bfd_mach_mips_sb1, CPU_SB1,
-    ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
+    ISA_MIPS64 | INSN_SB1,  ASE_MIPS3D,
     mips_cp0_names_sb1,
     mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
     mips_hwr_names_numeric },
 
   { "loongson2e",   1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
-    ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric, 
+    ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric,
     NULL, 0, mips_hwr_names_numeric },
 
   { "loongson2f",   1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
-    ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric, 
+    ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric,
     NULL, 0, mips_hwr_names_numeric },
 
   { "loongson3a",   1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
-    ISA_MIPS64 | INSN_LOONGSON_3A, mips_cp0_names_numeric, 
+    ISA_MIPS64 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric,
     NULL, 0, mips_hwr_names_numeric },
 
   { "octeon",   1, bfd_mach_mips_octeon, CPU_OCTEON,
-    ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
+    ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
     mips_hwr_names_numeric },
 
   { "octeon+",   1, bfd_mach_mips_octeonp, CPU_OCTEONP,
-    ISA_MIPS64R2 | INSN_OCTEONP, mips_cp0_names_numeric,
+    ISA_MIPS64R2 | INSN_OCTEONP, 0, mips_cp0_names_numeric,
     NULL, 0, mips_hwr_names_numeric },
 
   { "octeon2",   1, bfd_mach_mips_octeon2, CPU_OCTEON2,
-    ISA_MIPS64R2 | INSN_OCTEON2, mips_cp0_names_numeric,
+    ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric,
     NULL, 0, mips_hwr_names_numeric },
 
   { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
-    ISA_MIPS64 | INSN_XLR,
+    ISA_MIPS64 | INSN_XLR, 0,
     mips_cp0_names_xlr,
     mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
     mips_hwr_names_numeric },
@@ -648,14 +651,14 @@ const struct mips_arch_choice mips_arch_choices[] =
   /* XLP is mostly like XLR, with the prominent exception it is being
      MIPS64R2.  */
   { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR,
-    ISA_MIPS64R2 | INSN_XLR,
+    ISA_MIPS64R2 | INSN_XLR, 0,
     mips_cp0_names_xlr,
     mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
     mips_hwr_names_numeric },
 
   /* This entry, mips16, is here only for ISA/processor selection; do
      not print its name.  */
-  { "",                1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3,
+  { "",                1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
 };
 
@@ -664,6 +667,7 @@ const struct mips_arch_choice mips_arch_choices[] =
    values.  */
 static int mips_processor;
 static int mips_isa;
+static int mips_ase;
 static int micromips_ase;
 static const char * const *mips_gpr_names;
 static const char * const *mips_fpr_names;
@@ -769,6 +773,7 @@ set_default_mips_dis_options (struct disassemble_info *info)
   mips_isa = ISA_MIPS3;
   mips_processor = CPU_R3000;
   micromips_ase = 0;
+  mips_ase = 0;
   mips_gpr_names = mips_gpr_names_oldabi;
   mips_fpr_names = mips_fpr_names_numeric;
   mips_cp0_names = mips_cp0_names_numeric;
@@ -796,12 +801,14 @@ set_default_mips_dis_options (struct disassemble_info *info)
      FIXME: Where does mips_target_info come from?  */
   target_processor = mips_target_info.processor;
   mips_isa = mips_target_info.isa;
+  mips_ase = mips_target_info.ase;
 #else
   chosen_arch = choose_arch_by_number (info->mach);
   if (chosen_arch != NULL)
     {
       mips_processor = chosen_arch->processor;
       mips_isa = chosen_arch->isa;
+      mips_ase = chosen_arch->ase;
       mips_cp0_names = chosen_arch->cp0_names;
       mips_cp0sel_names = chosen_arch->cp0sel_names;
       mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
@@ -827,9 +834,9 @@ parse_mips_dis_option (const char *option, unsigned int len)
 
   if (CONST_STRNEQ (option, "virt"))
     {
-      mips_isa |= INSN_VIRT;
+      mips_ase |= ASE_VIRT;
       if (mips_isa & ISA_MIPS64R2)
-       mips_isa |= INSN_VIRT64;
+       mips_ase |= ASE_VIRT64;
       return;
     }
   
@@ -1514,7 +1521,7 @@ print_insn_mips (bfd_vma memaddr,
              const char *d;
 
              /* We always allow to disassemble the jalx instruction.  */
-             if (!opcode_is_member (op, mips_isa, mips_processor)
+             if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor)
                  && strcmp (op->name, "jalx"))
                continue;
 

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index c22156d..fcfa020 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -99,13 +99,13 @@
 #define I5_33   INSN_ISA5_32R2
 
 /* MIPS64 MIPS-3D ASE support.  */
-#define M3D     INSN_MIPS3D
+#define M3D     ASE_MIPS3D
 
 /* MIPS32 SmartMIPS ASE support.  */
-#define SMT    INSN_SMARTMIPS
+#define SMT    ASE_SMARTMIPS
 
 /* MIPS64 MDMX ASE support.  */
-#define MX      INSN_MDMX
+#define MX      ASE_MDMX
 
 #define IL2E    (INSN_LOONGSON_2E)
 #define IL2F    (INSN_LOONGSON_2F)
@@ -128,8 +128,8 @@
 #define IOCTP  (INSN_OCTEONP | INSN_OCTEON2)
 #define IOCT2  INSN_OCTEON2
 #define XLR     INSN_XLR
-#define IVIRT  INSN_VIRT
-#define IVIRT64        INSN_VIRT64
+#define IVIRT  ASE_VIRT
+#define IVIRT64        ASE_VIRT64
 
 #define G1      (T3             \
                  |EE            \
@@ -177,12 +177,12 @@
 #define RD_a   RD_HILO /* Read dsp accumulators (reuse RD_HILO)  */
 #define MOD_a  WR_a|RD_a
 #define DSP_VOLA INSN_NO_DELAY_SLOT
-#define D32    INSN_DSP
-#define D33    INSN_DSPR2
-#define D64    INSN_DSP64
+#define D32    ASE_DSP
+#define D33    ASE_DSPR2
+#define D64    ASE_DSP64
 
 /* MIPS MT ASE support.  */
-#define MT32   INSN_MT
+#define MT32   ASE_MT
 
 /* Loongson support.  */
 #define WR_z   INSN2_WRITE_GPR_Z
@@ -192,7 +192,7 @@
 #define RD_d   INSN2_READ_GPR_D
 
 /* MIPS MCU (MicroController) ASE support.  */
-#define MC     INSN_MCU
+#define MC     ASE_MCU
 
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
@@ -212,7 +212,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* These instructions appear first so that the disassembler will find
    them first.  The assemblers uses a hash table based on the
    instruction name anyhow.  */
-/* name,    args,      match,      mask,       pinfo,                  pinfo2,         membership,     [exclusions] */
+/* name,    args,      match,      mask,       pinfo,                  pinfo2,         membership,     [ase],  [exclusions] */
 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                  0,              I4_32|G3        },
 {"pref",    "k,A(b)",  0,    (int) M_PREF_AB,  INSN_MACRO,             0,              I4_32|G3        },
 {"prefx",   "h,t(b)",  0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S,         0,              I4_33   },
@@ -290,56 +290,56 @@ const struct mips_opcode mips_builtin_opcodes[] =
 
 {"abs",     "d,v",     0,    (int) M_ABS,      INSN_MACRO,             0,              I1      },
 {"abs.s",   "D,V",     0x46000005, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
-{"abs.d",   "D,V",     0x46200005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1,     SF      },
+{"abs.d",   "D,V",     0x46200005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1,     0,      SF      },
 {"abs.ps",  "D,V",     0x46c00005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5_33|IL2F      },
 {"abs.ps",  "D,V",     0x45600005, 0xffff003f, WR_D|RD_S|FP_D,         0,              IL2E    },
-{"aclr",    "\\,~(b)", 0x04070000, 0xfc1f8000, SM|RD_b|NODS,           0,              MC      },
-{"aclr",    "\\,o(b)", 0,    (int) M_ACLR_OB,  INSN_MACRO,             0,              MC      },
-{"aclr",    "\\,A(b)", 0,    (int) M_ACLR_AB,  INSN_MACRO,             0,              MC      },
+{"aclr",    "\\,~(b)", 0x04070000, 0xfc1f8000, SM|RD_b|NODS,           0,              0,      MC      },
+{"aclr",    "\\,o(b)", 0,    (int) M_ACLR_OB,  INSN_MACRO,             0,              0,      MC      },
+{"aclr",    "\\,A(b)", 0,    (int) M_ACLR_AB,  INSN_MACRO,             0,              0,      MC      },
 {"add",     "d,v,t",   0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"add",     "t,r,I",   0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1      },
 {"add",        "D,S,T",        0x45c00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
 {"add",        "D,S,T",        0x4b40000c,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F|IL3A       },
 {"add.s",   "D,V,T",   0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
-{"add.d",   "D,V,T",   0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1,     SF      },
-{"add.ob",  "X,Y,Q",   0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
+{"add.d",   "D,V,T",   0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1,     0,      SF      },
+{"add.ob",  "X,Y,Q",   0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1,    MX      },
 {"add.ob",  "D,S,T",   0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"add.ob",  "D,S,T[e]",        0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"add.ob",  "D,S,k",   0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"add.ps",  "D,V,T",   0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33|IL2F      },
 {"add.ps",  "D,V,T",   0x45600000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              IL2E    },
-{"add.qh",  "X,Y,Q",   0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
-{"adda.ob", "Y,Q",     0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
-{"adda.qh", "Y,Q",     0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
+{"add.qh",  "X,Y,Q",   0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      MX      },
+{"adda.ob", "Y,Q",     0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        SB1,    MX      },
+{"adda.qh", "Y,Q",     0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        0,      MX      },
 {"adda.s",  "V,T",     0x46000018, 0xffe007ff, RD_S|RD_T|FP_S,         0,              EE      },
 {"addi",    "t,r,j",   0x20000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
 {"addiu",   "t,r,j",   0x24000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
-{"addl.ob", "Y,Q",     0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
-{"addl.qh", "Y,Q",     0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
-{"addr.ps", "D,S,T",   0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
+{"addl.ob", "Y,Q",     0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        SB1,    MX      },
+{"addl.qh", "Y,Q",     0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        0,      MX      },
+{"addr.ps", "D,S,T",   0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      M3D     },
 {"addu",    "d,v,t",   0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"addu",    "t,r,I",   0,    (int) M_ADDU_I,   INSN_MACRO,             0,              I1      },
 {"addu",       "D,S,T",        0x45800000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
 {"addu",       "D,S,T",        0x4b00000c,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F|IL3A       },
-{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
+{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1,    MX      },
 {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T,         0,              N54     },
-{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
+{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      MX      },
 {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            I5_33   },
-{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            MX|SB1  },
-{"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            MX      },
+{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            SB1,    MX      },
+{"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            0,      MX      },
 {"and",     "d,v,t",   0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"and",     "t,r,I",   0,    (int) M_AND_I,    INSN_MACRO,             0,              I1      },
 {"and",        "D,S,T",        0x47c00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
 {"and",        "D,S,T",        0x4bc00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
-{"and.ob",  "X,Y,Q",   0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
+{"and.ob",  "X,Y,Q",   0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1,    MX      },
 {"and.ob",  "D,S,T",   0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"and.ob",  "D,S,T[e]",        0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"and.ob",  "D,S,k",   0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
-{"and.qh",  "X,Y,Q",   0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
+{"and.qh",  "X,Y,Q",   0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      MX      },
 {"andi",    "t,r,i",   0x30000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
-{"aset",    "\\,~(b)", 0x04078000, 0xfc1f8000, SM|RD_b|NODS,           0,              MC      },
-{"aset",    "\\,o(b)", 0,    (int) M_ASET_OB,  INSN_MACRO,             0,              MC      },
-{"aset",    "\\,A(b)", 0,    (int) M_ASET_AB,  INSN_MACRO,             0,              MC      },
+{"aset",    "\\,~(b)", 0x04078000, 0xfc1f8000, SM|RD_b|NODS,           0,              0,      MC      },
+{"aset",    "\\,o(b)", 0,    (int) M_ASET_OB,  INSN_MACRO,             0,              0,      MC      },
+{"aset",    "\\,A(b)", 0,    (int) M_ASET_AB,  INSN_MACRO,             0,              0,      MC      },
 {"baddu",   "d,v,t",   0x70000028, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              IOCT    },
 /* b is at the top of the table.  */
 /* bal is at the top of the table.  */
@@ -350,10 +350,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"bbit1",   "s,+X,p",  0xf8000000, 0xfc000000, RD_s|CBD,               0,              IOCT    }, /* bbit132 */
 {"bbit1",   "s,+x,p",  0xe8000000, 0xfc000000, RD_s|CBD,               0,              IOCT    },
 /* bc0[tf]l? are at the bottom of the table.  */
-{"bc1any2f", "N,p",    0x45200000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
-{"bc1any2t", "N,p",    0x45210000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
-{"bc1any4f", "N,p",    0x45400000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
-{"bc1any4t", "N,p",    0x45410000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
+{"bc1any2f", "N,p",    0x45200000, 0xffe30000, CBD|RD_CC|FP_S,         0,              0,      M3D     },
+{"bc1any2t", "N,p",    0x45210000, 0xffe30000, CBD|RD_CC|FP_S,         0,              0,      M3D     },
+{"bc1any4f", "N,p",    0x45400000, 0xffe30000, CBD|RD_CC|FP_S,         0,              0,      M3D     },
+{"bc1any4t", "N,p",    0x45410000, 0xffe30000, CBD|RD_CC|FP_S,         0,              0,      M3D     },
 {"bc1f",    "p",       0x45000000, 0xffff0000, CBD|RD_CC|FP_S,         0,              I1      },
 {"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S,        0,              I4_32   },
 {"bc1fl",   "p",       0x45020000, 0xffff0000, CBL|RD_CC|FP_S,         0,              I2|T3   },
@@ -423,183 +423,183 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"break",   "",                0x0000000d, 0xffffffff, TRAP,                   0,              I1      },
 {"break",   "c",       0x0000000d, 0xfc00ffff, TRAP,                   0,              I1      },
 {"break",   "c,q",     0x0000000d, 0xfc00003f, TRAP,                   0,              I1      },
-{"c.f.d",   "S,T",     0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     SF      },
+{"c.f.d",   "S,T",     0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     0,      SF      },
 {"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
 {"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
 {"c.f.ps",  "S,T",     0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
 {"c.f.ps",  "S,T",     0x45600030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.f.ps",  "M,S,T",   0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
-{"c.un.d",  "S,T",     0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     SF      },
+{"c.un.d",  "S,T",     0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     0,      SF      },
 {"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
-{"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     EE      },
+{"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     0,      EE      },
 {"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
 {"c.un.ps", "S,T",     0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
 {"c.un.ps", "S,T",     0x45600031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.un.ps", "M,S,T",   0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
-{"c.eq.d",  "S,T",     0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     SF      },
+{"c.eq.d",  "S,T",     0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     0,      SF      },
 {"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
 {"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
-{"c.eq.ob", "Y,Q",     0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
+{"c.eq.ob", "Y,Q",     0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              SB1,    MX      },
 {"c.eq.ob", "S,T",     0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.eq.ob", "S,T[e]",  0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.eq.ob", "S,k",     0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.eq.ps", "S,T",     0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
 {"c.eq.ps", "S,T",     0x45600032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.eq.ps", "M,S,T",   0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
-{"c.eq.qh", "Y,Q",     0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
-{"c.ueq.d", "S,T",     0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     SF      },
+{"c.eq.qh", "Y,Q",     0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              0,      MX      },
+{"c.ueq.d", "S,T",     0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     0,      SF      },
 {"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
-{"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     EE      },
+{"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     0,      EE      },
 {"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
 {"c.ueq.ps","S,T",     0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
 {"c.ueq.ps","S,T",     0x45600033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.ueq.ps","M,S,T",   0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
-{"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,             I1,     SF      },
+{"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,             I1,     0,      SF      },
 {"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
-{"c.olt.s", "S,T",     0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1,     EE      },
+{"c.olt.s", "S,T",     0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1,     0,      EE      },
 {"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
 {"c.olt.ps","S,T",     0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
 {"c.olt.ps","S,T",     0x45600034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.olt.ps","M,S,T",   0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
-{"c.ult.d", "S,T",     0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     SF      },
+{"c.ult.d", "S,T",     0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     0,      SF      },
 {"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
-{"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     EE      },
+{"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     0,      EE      },
 {"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
 {"c.ult.ps","S,T",     0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
 {"c.ult.ps","S,T",     0x45600035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.ult.ps","M,S,T",   0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
-{"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,             I1,     SF      },
+{"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,             I1,     0,      SF      },
 {"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
-{"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     EE      },
+{"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     0,      EE      },
 {"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
 {"c.ole.ps","S,T",     0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
 {"c.ole.ps","S,T",     0x45600036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.ole.ps","M,S,T",   0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
-{"c.ule.d", "S,T",     0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     SF      },
+{"c.ule.d", "S,T",     0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     0,      SF      },
 {"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
-{"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     EE      },
+{"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     0,      EE      },
 {"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
 {"c.ule.ps","S,T",     0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
 {"c.ule.ps","S,T",     0x45600037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.ule.ps","M,S,T",   0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
-{"c.sf.d",  "S,T",     0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     SF      },
+{"c.sf.d",  "S,T",     0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     0,      SF      },
 {"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
-{"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     EE      },
+{"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     0,      EE      },
 {"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
 {"c.sf.ps", "S,T",     0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
 {"c.sf.ps", "S,T",     0x45600038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.sf.ps", "M,S,T",   0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
-{"c.ngle.d","S,T",     0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     SF      },
+{"c.ngle.d","S,T",     0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     0,      SF      },
 {"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
-{"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     EE      },
+{"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     0,      EE      },
 {"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
 {"c.ngle.ps","S,T",    0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
 {"c.ngle.ps","S,T",    0x45600039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.ngle.ps","M,S,T",  0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
-{"c.seq.d", "S,T",     0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     SF      },
+{"c.seq.d", "S,T",     0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     0,      SF      },
 {"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
-{"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     EE      },
+{"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     0,      EE      },
 {"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
 {"c.seq.ps","S,T",     0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
 {"c.seq.ps","S,T",     0x4560003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.seq.ps","M,S,T",   0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
-{"c.ngl.d", "S,T",     0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     SF      },
+{"c.ngl.d", "S,T",     0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     0,      SF      },
 {"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
-{"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     EE      },
+{"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     0,      EE      },
 {"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
 {"c.ngl.ps","S,T",     0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
 {"c.ngl.ps","S,T",     0x4560003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.ngl.ps","M,S,T",   0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
-{"c.lt.d",  "S,T",     0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     SF      },
+{"c.lt.d",  "S,T",     0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     0,      SF      },
 {"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.lt.s",  "S,T",     0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              EE      },
-{"c.lt.s",  "S,T",     0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1,     EE      },
+{"c.lt.s",  "S,T",     0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1,     0,      EE      },
 {"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
-{"c.lt.ob", "Y,Q",     0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
+{"c.lt.ob", "Y,Q",     0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              SB1,    MX      },
 {"c.lt.ob", "S,T",     0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.lt.ob", "S,T[e]",  0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.lt.ob", "S,k",     0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.lt.ps", "S,T",     0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
 {"c.lt.ps", "S,T",     0x4560003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.lt.ps", "M,S,T",   0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
-{"c.lt.qh", "Y,Q",     0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
-{"c.nge.d", "S,T",     0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     SF      },
+{"c.lt.qh", "Y,Q",     0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              0,      MX      },
+{"c.nge.d", "S,T",     0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     0,      SF      },
 {"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
-{"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     EE      },
+{"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     0,      EE      },
 {"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
 {"c.nge.ps","S,T",     0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
 {"c.nge.ps","S,T",     0x4560003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.nge.ps","M,S,T",   0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
-{"c.le.d",  "S,T",     0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     SF      },
+{"c.le.d",  "S,T",     0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     0,      SF      },
 {"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.le.s",  "S,T",     0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              EE      },
-{"c.le.s",  "S,T",     0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1,     EE      },
+{"c.le.s",  "S,T",     0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1,     0,      EE      },
 {"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
-{"c.le.ob", "Y,Q",     0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
+{"c.le.ob", "Y,Q",     0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              SB1,    MX      },
 {"c.le.ob", "S,T",     0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.le.ob", "S,T[e]",  0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.le.ob", "S,k",     0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.le.ps", "S,T",     0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
 {"c.le.ps", "S,T",     0x4560003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.le.ps", "M,S,T",   0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
-{"c.le.qh", "Y,Q",     0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
-{"c.ngt.d", "S,T",     0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     SF      },
+{"c.le.qh", "Y,Q",     0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              0,      MX      },
+{"c.ngt.d", "S,T",     0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1,     0,      SF      },
 {"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
-{"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     EE      },
+{"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1,     0,      EE      },
 {"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
 {"c.ngt.ps","S,T",     0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
 {"c.ngt.ps","S,T",     0x4560003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.ngt.ps","M,S,T",   0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
-{"cabs.eq.d",  "M,S,T",        0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.eq.ps", "M,S,T",        0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.eq.s",  "M,S,T",        0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
-{"cabs.f.d",   "M,S,T",        0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.f.ps",  "M,S,T",        0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.f.s",   "M,S,T",        0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
-{"cabs.le.d",  "M,S,T",        0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.le.ps", "M,S,T",        0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.le.s",  "M,S,T",        0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
-{"cabs.lt.d",  "M,S,T",        0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.lt.ps", "M,S,T",        0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.lt.s",  "M,S,T",        0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
-{"cabs.nge.d", "M,S,T",        0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.nge.ps","M,S,T",        0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.nge.s", "M,S,T",        0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
-{"cabs.ngl.d", "M,S,T",        0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.ngl.ps","M,S,T",        0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.ngl.s", "M,S,T",        0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
-{"cabs.ngle.d","M,S,T",        0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.ngle.s","M,S,T",        0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
-{"cabs.ngt.d", "M,S,T",        0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.ngt.ps","M,S,T",        0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.ngt.s", "M,S,T",        0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
-{"cabs.ole.d", "M,S,T",        0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.ole.ps","M,S,T",        0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.ole.s", "M,S,T",        0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
-{"cabs.olt.d", "M,S,T",        0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.olt.ps","M,S,T",        0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.olt.s", "M,S,T",        0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
-{"cabs.seq.d", "M,S,T",        0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.seq.ps","M,S,T",        0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.seq.s", "M,S,T",        0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
-{"cabs.sf.d",  "M,S,T",        0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.sf.ps", "M,S,T",        0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.sf.s",  "M,S,T",        0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
-{"cabs.ueq.d", "M,S,T",        0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.ueq.ps","M,S,T",        0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.ueq.s", "M,S,T",        0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
-{"cabs.ule.d", "M,S,T",        0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.ule.ps","M,S,T",        0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.ule.s", "M,S,T",        0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
-{"cabs.ult.d", "M,S,T",        0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.ult.ps","M,S,T",        0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.ult.s", "M,S,T",        0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
-{"cabs.un.d",  "M,S,T",        0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.un.ps", "M,S,T",        0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
-{"cabs.un.s",  "M,S,T",        0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
+{"cabs.eq.d",  "M,S,T",        0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.eq.ps", "M,S,T",        0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.eq.s",  "M,S,T",        0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              0,      M3D     },
+{"cabs.f.d",   "M,S,T",        0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.f.ps",  "M,S,T",        0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.f.s",   "M,S,T",        0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              0,      M3D     },
+{"cabs.le.d",  "M,S,T",        0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.le.ps", "M,S,T",        0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.le.s",  "M,S,T",        0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              0,      M3D     },
+{"cabs.lt.d",  "M,S,T",        0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.lt.ps", "M,S,T",        0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.lt.s",  "M,S,T",        0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              0,      M3D     },
+{"cabs.nge.d", "M,S,T",        0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.nge.ps","M,S,T",        0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.nge.s", "M,S,T",        0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              0,      M3D     },
+{"cabs.ngl.d", "M,S,T",        0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.ngl.ps","M,S,T",        0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.ngl.s", "M,S,T",        0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              0,      M3D     },
+{"cabs.ngle.d","M,S,T",        0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.ngle.s","M,S,T",        0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              0,      M3D     },
+{"cabs.ngt.d", "M,S,T",        0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.ngt.ps","M,S,T",        0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.ngt.s", "M,S,T",        0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              0,      M3D     },
+{"cabs.ole.d", "M,S,T",        0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.ole.ps","M,S,T",        0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.ole.s", "M,S,T",        0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              0,      M3D     },
+{"cabs.olt.d", "M,S,T",        0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.olt.ps","M,S,T",        0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.olt.s", "M,S,T",        0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              0,      M3D     },
+{"cabs.seq.d", "M,S,T",        0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.seq.ps","M,S,T",        0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.seq.s", "M,S,T",        0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              0,      M3D     },
+{"cabs.sf.d",  "M,S,T",        0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.sf.ps", "M,S,T",        0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.sf.s",  "M,S,T",        0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              0,      M3D     },
+{"cabs.ueq.d", "M,S,T",        0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.ueq.ps","M,S,T",        0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.ueq.s", "M,S,T",        0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              0,      M3D     },
+{"cabs.ule.d", "M,S,T",        0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.ule.ps","M,S,T",        0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.ule.s", "M,S,T",        0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              0,      M3D     },
+{"cabs.ult.d", "M,S,T",        0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.ult.ps","M,S,T",        0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.ult.s", "M,S,T",        0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              0,      M3D     },
+{"cabs.un.d",  "M,S,T",        0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.un.ps", "M,S,T",        0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              0,      M3D     },
+{"cabs.un.s",  "M,S,T",        0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              0,      M3D     },
 /* CW4010 instructions which are aliases for the cache instruction.  */
 {"flushi",  "",                0xbc010000, 0xffffffff, 0,                      0,              L1      },
 {"flushd",  "",                0xbc020000, 0xffffffff, 0,                      0,              L1      },
@@ -609,44 +609,44 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cache",   "k,A(b)",  0,    (int) M_CACHE_AB, INSN_MACRO,             0,              I3_32|T3},
 {"ceil.l.d", "D,S",    0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3_33   },
 {"ceil.l.s", "D,S",    0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3_33   },
-{"ceil.w.d", "D,S",    0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2,     SF      },
-{"ceil.w.s", "D,S",    0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2,     EE      },
-{"cfc0",    "t,G",     0x40400000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1,             IOCT|IOCTP|IOCT2        },
+{"ceil.w.d", "D,S",    0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2,     0,      SF      },
+{"ceil.w.s", "D,S",    0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2,     0,      EE      },
+{"cfc0",    "t,G",     0x40400000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1,     0,      IOCT|IOCTP|IOCT2        },
 {"cfc1",    "t,G",     0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,              I1      },
 {"cfc1",    "t,S",     0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,              I1      },
 /* cfc2 is at the bottom of the table.  */
 /* cfc3 is at the bottom of the table.  */
-{"cftc1",   "d,E",     0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            MT32    },
-{"cftc1",   "d,T",     0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            MT32    },
-{"cftc2",   "d,E",     0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32,           IOCT|IOCTP|IOCT2        },
+{"cftc1",   "d,E",     0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            0,      MT32    },
+{"cftc1",   "d,T",     0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            0,      MT32    },
+{"cftc2",   "d,E",     0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              0,      MT32,   IOCT|IOCTP|IOCT2        },
 {"cins32",  "t,r,+p,+S",0x70000033, 0xfc00003f, WR_t|RD_s,             0,              IOCT    },
 {"cins",    "t,r,+P,+S",0x70000033, 0xfc00003f, WR_t|RD_s,             0,              IOCT    }, /* cins32 */
 {"cins",    "t,r,+p,+s",0x70000032, 0xfc00003f, WR_t|RD_s,             0,              IOCT    },
 {"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s,        0,              I32|N55 },
 {"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s,        0,              I32|N55 },
-{"ctc0",    "t,G",     0x40c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1,             IOCT|IOCTP|IOCT2        },
+{"ctc0",    "t,G",     0x40c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1,     0,      IOCT|IOCTP|IOCT2        },
 {"ctc1",    "t,G",     0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    0,              I1      },
 {"ctc1",    "t,S",     0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    0,              I1      },
 /* ctc2 is at the bottom of the table.  */
 /* ctc3 is at the bottom of the table.  */
-{"cttc1",   "t,g",     0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
-{"cttc1",   "t,S",     0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
-{"cttc2",   "t,g",     0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC,    0,              MT32,           IOCT|IOCTP|IOCT2        },
+{"cttc1",   "t,g",     0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            0,      MT32    },
+{"cttc1",   "t,S",     0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            0,      MT32    },
+{"cttc2",   "t,g",     0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC,    0,              0,      MT32,   IOCT|IOCTP|IOCT2        },
 {"cvt.d.l", "D,S",     0x46a00021, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3_33   },
-{"cvt.d.s", "D,S",     0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1,     SF      },
-{"cvt.d.w", "D,S",     0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1,     SF      },
+{"cvt.d.s", "D,S",     0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1,     0,      SF      },
+{"cvt.d.w", "D,S",     0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1,     0,      SF      },
 {"cvt.l.d", "D,S",     0x46200025, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3_33   },
 {"cvt.l.s", "D,S",     0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3_33   },
 {"cvt.s.l", "D,S",     0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3_33   },
-{"cvt.s.d", "D,S",     0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1,     SF      },
+{"cvt.s.d", "D,S",     0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1,     0,      SF      },
 {"cvt.s.w", "D,S",     0x46800020, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
 {"cvt.s.pl","D,S",     0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5_33   },
 {"cvt.s.pu","D,S",     0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5_33   },
-{"cvt.w.d", "D,S",     0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1,     SF      },
-{"cvt.w.s", "D,S",     0x46000024, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1,     EE      },
-{"cvt.ps.pw", "D,S",   0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              M3D     },
+{"cvt.w.d", "D,S",     0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1,     0,      SF      },
+{"cvt.w.s", "D,S",     0x46000024, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1,     0,      EE      },
+{"cvt.ps.pw", "D,S",   0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              0,      M3D     },
 {"cvt.ps.s","D,V,T",   0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0,            I5_33   },
-{"cvt.pw.ps", "D,S",   0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              M3D     },
+{"cvt.pw.ps", "D,S",   0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              0,      M3D     },
 {"dabs",    "d,v",     0,    (int) M_DABS,     INSN_MACRO,             0,              I3      },
 {"dadd",    "d,v,t",   0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
 {"dadd",    "t,r,I",   0,    (int) M_DADD_I,   INSN_MACRO,             0,              I3      },
@@ -669,13 +669,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dextm",   "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s,                    0,              I65     },
 {"dextu",   "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s,                    0,              I65     },
 /* For ddiv, see the comments about div.  */
-{"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3,     M32     },
-{"ddiv",    "d,v,t",   0,    (int) M_DDIV_3,   INSN_MACRO,             0,              I3,     M32     },
-{"ddiv",    "d,v,I",   0,    (int) M_DDIV_3I,  INSN_MACRO,             0,              I3,     M32     },
+{"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3,     0,      M32     },
+{"ddiv",    "d,v,t",   0,    (int) M_DDIV_3,   INSN_MACRO,             0,              I3,     0,      M32     },
+{"ddiv",    "d,v,I",   0,    (int) M_DDIV_3I,  INSN_MACRO,             0,              I3,     0,      M32     },
 /* For ddivu, see the comments about div.  */
-{"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3,     M32     },
-{"ddivu",   "d,v,t",   0,    (int) M_DDIVU_3,  INSN_MACRO,             0,              I3,     M32     },
-{"ddivu",   "d,v,I",   0,    (int) M_DDIVU_3I, INSN_MACRO,             0,              I3,     M32     },
+{"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3,     0,      M32     },
+{"ddivu",   "d,v,t",   0,    (int) M_DDIVU_3,  INSN_MACRO,             0,              I3,     0,      M32     },
+{"ddivu",   "d,v,I",   0,    (int) M_DDIVU_3I, INSN_MACRO,             0,              I3,     0,      M32     },
 {"di",      "",                0x42000039, 0xffffffff, WR_C0,                  0,              EE      },
 {"di",      "",                0x41606000, 0xffffffff, WR_t|WR_C0,             0,              I33     },
 {"di",      "t",       0x41606000, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
@@ -693,7 +693,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"div",     "d,v,I",   0,    (int) M_DIV_3I,   INSN_MACRO,             0,              I1      },
 {"div1",    "z,s,t",    0x7000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             EE      },
 {"div1",    "z,t",      0x7000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,             EE      },
-{"div.d",   "D,V,T",   0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1,     SF      },
+{"div.d",   "D,V,T",   0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1,     0,      SF      },
 {"div.s",   "D,V,T",   0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
 {"div.ps",  "D,V,T",   0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
 /* For divu, see the comments about div.  */
@@ -717,46 +717,46 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dmaccu",  "d,s,t",   0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
 {"dmaccus", "d,s,t",   0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
 {"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       0,             N411    },
-{"dmfc0",   "t,G",     0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I3,     EE      },
+{"dmfc0",   "t,G",     0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I3,     0,      EE      },
 {"dmfc0",   "t,+D",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I64     },
 {"dmfc0",   "t,G,H",   0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I64     },
-{"dmfgc0",   "t,G",    0x40600100, 0xffe007ff, LCD|WR_t|RD_C0,         0,              IVIRT64 },
-{"dmfgc0",   "t,+D",   0x40600100, 0xffe007f8, LCD|WR_t|RD_C0,         0,              IVIRT64 },
-{"dmfgc0",   "t,G,H",  0x40600100, 0xffe007f8, LCD|WR_t|RD_C0,         0,              IVIRT64 },
-{"dmt",     "",                0x41600bc1, 0xffffffff, TRAP,                   0,              MT32    },
-{"dmt",     "t",       0x41600bc1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
-{"dmtc0",   "t,G",     0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I3,     EE      },
+{"dmfgc0",   "t,G",    0x40600100, 0xffe007ff, LCD|WR_t|RD_C0,         0,              0,      IVIRT64 },
+{"dmfgc0",   "t,+D",   0x40600100, 0xffe007f8, LCD|WR_t|RD_C0,         0,              0,      IVIRT64 },
+{"dmfgc0",   "t,G,H",  0x40600100, 0xffe007f8, LCD|WR_t|RD_C0,         0,              0,      IVIRT64 },
+{"dmt",     "",                0x41600bc1, 0xffffffff, TRAP,                   0,              0,      MT32    },
+{"dmt",     "t",       0x41600bc1, 0xffe0ffff, TRAP|WR_t,              0,              0,      MT32    },
+{"dmtc0",   "t,G",     0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I3,     0,      EE      },
 {"dmtc0",   "t,+D",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I64     },
 {"dmtc0",   "t,G,H",   0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I64     },
-{"dmtgc0",  "t,G",     0x40600300, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              IVIRT64 },
-{"dmtgc0",  "t,+D",     0x40600300, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             IVIRT64 },
-{"dmtgc0",  "t,G,H",    0x40600300, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             IVIRT64 },
-{"dmfc1",   "t,S",     0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I3,     SF      },
-{"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,             I3,     SF      },
-{"dmtc1",   "t,S",     0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I3,     SF      },
-{"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,             I3,     SF      },
+{"dmtgc0",  "t,G",     0x40600300, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              0,      IVIRT64 },
+{"dmtgc0",  "t,+D",     0x40600300, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             0,      IVIRT64 },
+{"dmtgc0",  "t,G,H",    0x40600300, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             0,      IVIRT64 },
+{"dmfc1",   "t,S",     0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I3,     0,      SF      },
+{"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,             I3,     0,      SF      },
+{"dmtc1",   "t,S",     0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I3,     0,      SF      },
+{"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,             I3,     0,      SF      },
 /* dmfc2 is at the bottom of the table.  */
 /* dmtc2 is at the bottom of the table.  */
 /* dmfc3 is at the bottom of the table.  */
 /* dmtc3 is at the bottom of the table.  */
 {"dmul",    "d,v,t",   0x70000003, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              IOCT    },
-{"dmul",    "d,v,t",   0,    (int) M_DMUL,     INSN_MACRO,             0,              I3,     M32     },
-{"dmul",    "d,v,I",   0,    (int) M_DMUL_I,   INSN_MACRO,             0,              I3,     M32     },
-{"dmulo",   "d,v,t",   0,    (int) M_DMULO,    INSN_MACRO,             0,              I3,     M32     },
-{"dmulo",   "d,v,I",   0,    (int) M_DMULO_I,  INSN_MACRO,             0,              I3,     M32     },
-{"dmulou",  "d,v,t",   0,    (int) M_DMULOU,   INSN_MACRO,             0,              I3,     M32     },
-{"dmulou",  "d,v,I",   0,    (int) M_DMULOU_I, INSN_MACRO,             0,              I3,     M32     },
-{"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3,     M32     },
-{"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3,     M32     },
+{"dmul",    "d,v,t",   0,    (int) M_DMUL,     INSN_MACRO,             0,              I3,     0,      M32     },
+{"dmul",    "d,v,I",   0,    (int) M_DMUL_I,   INSN_MACRO,             0,              I3,     0,      M32     },
+{"dmulo",   "d,v,t",   0,    (int) M_DMULO,    INSN_MACRO,             0,              I3,     0,      M32     },
+{"dmulo",   "d,v,I",   0,    (int) M_DMULO_I,  INSN_MACRO,             0,              I3,     0,      M32     },
+{"dmulou",  "d,v,t",   0,    (int) M_DMULOU,   INSN_MACRO,             0,              I3,     0,      M32     },
+{"dmulou",  "d,v,I",   0,    (int) M_DMULOU_I, INSN_MACRO,             0,              I3,     0,      M32     },
+{"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3,     0,      M32     },
+{"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3,     0,      M32     },
 {"dneg",    "d,w",     0x0000002e, 0xffe007ff, WR_d|RD_t,              0,              I3      }, /* dsub 0 */
 {"dnegu",   "d,w",     0x0000002f, 0xffe007ff, WR_d|RD_t,              0,              I3      }, /* dsubu 0*/
 {"dpop",    "d,v",     0x7000002d, 0xfc1f07ff, WR_d|RD_s,              0,              IOCT    },
-{"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3,     M32     },
-{"drem",    "d,v,t",   0,    (int) M_DREM_3,   INSN_MACRO,             0,              I3,     M32     },
-{"drem",    "d,v,I",   0,    (int) M_DREM_3I,  INSN_MACRO,             0,              I3,     M32     },
-{"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3,     M32     },
-{"dremu",   "d,v,t",   0,    (int) M_DREMU_3,  INSN_MACRO,             0,              I3,     M32     },
-{"dremu",   "d,v,I",   0,    (int) M_DREMU_3I, INSN_MACRO,             0,              I3,     M32     },
+{"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3,     0,      M32     },
+{"drem",    "d,v,t",   0,    (int) M_DREM_3,   INSN_MACRO,             0,              I3,     0,      M32     },
+{"drem",    "d,v,I",   0,    (int) M_DREM_3I,  INSN_MACRO,             0,              I3,     0,      M32     },
+{"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3,     0,      M32     },
+{"dremu",   "d,v,t",   0,    (int) M_DREMU_3,  INSN_MACRO,             0,              I3,     0,      M32     },
+{"dremu",   "d,v,I",   0,    (int) M_DREMU_3I, INSN_MACRO,             0,              I3,     0,      M32     },
 {"dret",    "",                0x7000003e, 0xffffffff, 0,                      0,              N5      },
 {"drol",    "d,v,t",   0,    (int) M_DROL,     INSN_MACRO,             0,              I3      },
 {"drol",    "d,v,I",   0,    (int) M_DROL_I,   INSN_MACRO,             0,              I3      },
@@ -800,29 +800,29 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsub",       "D,S,T",        0x4b60000d,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"dsubu",   "d,v,t",   0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
 {"dsubu",   "d,v,I",   0,    (int) M_DSUBU_I,  INSN_MACRO,             0,              I3      },
-{"dvpe",    "",                0x41600001, 0xffffffff, TRAP,                   0,              MT32    },
-{"dvpe",    "t",       0x41600001, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
+{"dvpe",    "",                0x41600001, 0xffffffff, TRAP,                   0,              0,      MT32    },
+{"dvpe",    "t",       0x41600001, 0xffe0ffff, TRAP|WR_t,              0,              0,      MT32    },
 {"ei",      "",                0x42000038, 0xffffffff, WR_C0,                  0,              EE      },
 {"ei",      "",                0x41606020, 0xffffffff, WR_t|WR_C0,             0,              I33     },
 {"ei",      "t",       0x41606020, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
-{"emt",     "",                0x41600be1, 0xffffffff, TRAP,                   0,              MT32    },
-{"emt",     "t",       0x41600be1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
+{"emt",     "",                0x41600be1, 0xffffffff, TRAP,                   0,              0,      MT32    },
+{"emt",     "t",       0x41600be1, 0xffe0ffff, TRAP|WR_t,              0,              0,      MT32    },
 {"eret",    "",         0x42000018, 0xffffffff, NODS,                  0,              I3_32   },
-{"evpe",    "",                0x41600021, 0xffffffff, TRAP,                   0,              MT32    },
-{"evpe",    "t",       0x41600021, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
+{"evpe",    "",                0x41600021, 0xffffffff, TRAP,                   0,              0,      MT32    },
+{"evpe",    "t",       0x41600021, 0xffe0ffff, TRAP|WR_t,              0,              0,      MT32    },
 {"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,                    0,              I33     },
 {"exts32",  "t,r,+p,+S",0x7000003b, 0xfc00003f, WR_t|RD_s,             0,              IOCT    },
 {"exts",    "t,r,+P,+S",0x7000003b, 0xfc00003f, WR_t|RD_s,             0,              IOCT    }, /* exts32 */
 {"exts",    "t,r,+p,+s",0x7000003a, 0xfc00003f, WR_t|RD_s,             0,              IOCT    },
 {"floor.l.d", "D,S",   0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3_33   },
 {"floor.l.s", "D,S",   0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3_33   },
-{"floor.w.d", "D,S",   0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2,     SF      },
+{"floor.w.d", "D,S",   0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2,     0,      SF      },
 {"floor.w.s", "D,S",   0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
 {"hibernate","",        0x42000023, 0xffffffff,        0,                      0,              V1      },
-{"hypcall", "",                0x42000028, 0xffffffff, TRAP,                   0,              IVIRT   },
-{"hypcall", "+J",      0x42000028, 0xffe007ff, TRAP,                   0,              IVIRT   },
+{"hypcall", "",                0x42000028, 0xffffffff, TRAP,                   0,              0,      IVIRT   },
+{"hypcall", "+J",      0x42000028, 0xffe007ff, TRAP,                   0,              0,      IVIRT   },
 {"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,                    0,              I33     },
-{"iret",    "",                0x42000038, 0xffffffff, NODS,                   0,              MC      },
+{"iret",    "",                0x42000038, 0xffffffff, NODS,                   0,              0,      MC      },
 {"jr",      "s",       0x00000008, 0xfc1fffff, UBD|RD_s,               0,              I1      },
 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
    the same hazard barrier effect.  */
@@ -869,11 +869,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lbu",     "t,o(b)",  0x90000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
 {"lbu",     "t,A(b)",  0,    (int) M_LBU_AB,   INSN_MACRO,             0,              I1      },
 {"lbx",     "d,t(b)",  0x7c00058a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              IOCT2   },
-{"lbux",    "d,t(b)",  0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32|IOCT2},
-{"ldx",     "d,t(b)",  0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D64|IOCT2},
-{"lhx",     "d,t(b)",  0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32|IOCT2},
+{"lbux",    "d,t(b)",  0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              IOCT2,  D32},
+{"ldx",     "d,t(b)",  0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              IOCT2,  D64},
+{"lhx",     "d,t(b)",  0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              IOCT2,  D32},
 {"lhux",    "d,t(b)",  0x7c00050a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              IOCT2   },
-{"lwx",     "d,t(b)",  0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32|IOCT2},
+{"lwx",     "d,t(b)",  0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              IOCT2,  D32},
 {"lwux",    "d,t(b)",  0x7c00040a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              IOCT2   },
 {"lca",     "t,A(b)",  0,    (int) M_LCA_AB,   INSN_MACRO,             0,              I1      },
 /* The macro has to be first to handle o32 correctly.  */
@@ -883,17 +883,17 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ldaddw",  "t,b",     0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,              XLR     },
 {"ldaddwu", "t,b",     0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,              XLR     },
 {"ldaddd",  "t,b",     0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,              XLR     },
-{"ldc1",    "T,o(b)",  0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2,     SF      },
-{"ldc1",    "E,o(b)",  0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2,     SF      },
-{"ldc1",    "T,A(b)",  0,    (int) M_LDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2,     SF      },
-{"ldc1",    "E,A(b)",  0,    (int) M_LDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2,     SF      },
-{"l.d",     "T,o(b)",  0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2,     SF      }, /* ldc1 */
+{"ldc1",    "T,o(b)",  0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2,     0,      SF      },
+{"ldc1",    "E,o(b)",  0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2,     0,      SF      },
+{"ldc1",    "T,A(b)",  0,    (int) M_LDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2,     0,      SF      },
+{"ldc1",    "E,A(b)",  0,    (int) M_LDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2,     0,      SF      },
+{"l.d",     "T,o(b)",  0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2,     0,      SF      }, /* ldc1 */
 {"l.d",     "T,o(b)",  0,    (int) M_L_DOB,    INSN_MACRO,             INSN2_M_FP_D,   I1      },
 {"l.d",     "T,A(b)",  0,    (int) M_L_DAB,    INSN_MACRO,             INSN2_M_FP_D,   I1      },
-{"ldc2",    "E,o(b)",  0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2,             IOCT|IOCTP|IOCT2|EE     },
-{"ldc2",    "E,A(b)",  0,    (int) M_LDC2_AB,  INSN_MACRO,             0,              I2,             IOCT|IOCTP|IOCT2|EE     },
-{"ldc3",    "E,o(b)",  0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2,             IOCT|IOCTP|IOCT2|EE     },
-{"ldc3",    "E,A(b)",  0,    (int) M_LDC3_AB,  INSN_MACRO,             0,              I2,             IOCT|IOCTP|IOCT2|EE     },
+{"ldc2",    "E,o(b)",  0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"ldc2",    "E,A(b)",  0,    (int) M_LDC2_AB,  INSN_MACRO,             0,              I2,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"ldc3",    "E,o(b)",  0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"ldc3",    "E,A(b)",  0,    (int) M_LDC3_AB,  INSN_MACRO,             0,              I2,     0,      IOCT|IOCTP|IOCT2|EE     },
 {"ldl",            "t,o(b)",   0x68000000, 0xfc000000, LDD|WR_t|RD_b,          0,              I3      },
 {"ldl",            "t,A(b)",   0,    (int) M_LDL_AB,   INSN_MACRO,             0,              I3      },
 {"ldr",            "t,o(b)",   0x6c000000, 0xfc000000, LDD|WR_t|RD_b,          0,              I3      },
@@ -904,14 +904,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lhu",     "t,o(b)",  0x94000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
 {"lhu",     "t,A(b)",  0,    (int) M_LHU_AB,   INSN_MACRO,             0,              I1      },
 /* li is at the start of the table.  */
-{"li.d",    "t,F",     0,    (int) M_LI_D,     INSN_MACRO,             INSN2_M_FP_D,   I1,     SF      },
-{"li.d",    "T,L",     0,    (int) M_LI_DD,    INSN_MACRO,             INSN2_M_FP_D,   I1,     SF      },
+{"li.d",    "t,F",     0,    (int) M_LI_D,     INSN_MACRO,             INSN2_M_FP_D,   I1,     0,      SF      },
+{"li.d",    "T,L",     0,    (int) M_LI_DD,    INSN_MACRO,             INSN2_M_FP_D,   I1,     0,      SF      },
 {"li.s",    "t,f",     0,    (int) M_LI_S,     INSN_MACRO,             INSN2_M_FP_S,   I1      },
 {"li.s",    "T,l",     0,    (int) M_LI_SS,    INSN_MACRO,             INSN2_M_FP_S,   I1      },
-{"ll",     "t,o(b)",   0xc0000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2,     EE      },
-{"ll",     "t,A(b)",   0,    (int) M_LL_AB,    INSN_MACRO,             0,              I2,     EE      },
-{"lld",            "t,o(b)",   0xd0000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I3,     EE      },
-{"lld",     "t,A(b)",  0,    (int) M_LLD_AB,   INSN_MACRO,             0,              I3,     EE      },
+{"ll",     "t,o(b)",   0xc0000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2,     0,      EE      },
+{"ll",     "t,A(b)",   0,    (int) M_LL_AB,    INSN_MACRO,             0,              I2,     0,      EE      },
+{"lld",            "t,o(b)",   0xd0000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I3,     0,      EE      },
+{"lld",     "t,A(b)",  0,    (int) M_LLD_AB,   INSN_MACRO,             0,              I3,     0,      EE      },
 {"lq",      "t,o(b)",  0x78000000, 0xfc000000, WR_t|RD_b,              0,              MMI     },
 {"lq",      "t,A(b)",  0,    (int) M_LQ_AB,    INSN_MACRO,             0,              MMI     },
 {"lqc2",    "E,o(b)",  0xd8000000, 0xfc000000, RD_b|WR_C2,             0,              EE      },
@@ -920,18 +920,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"luxc1",   "D,t(b)",  0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I5_33|N55},
 {"lw",      "t,o(b)",  0x8c000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
 {"lw",      "t,A(b)",  0,    (int) M_LW_AB,    INSN_MACRO,             0,              I1      },
-{"lwc0",    "E,o(b)",  0xc0000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1,             IOCT|IOCTP|IOCT2        },
-{"lwc0",    "E,A(b)",  0,    (int) M_LWC0_AB,  INSN_MACRO,             0,              I1,             IOCT|IOCTP|IOCT2        },
+{"lwc0",    "E,o(b)",  0xc0000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1,     0,      IOCT|IOCTP|IOCT2        },
+{"lwc0",    "E,A(b)",  0,    (int) M_LWC0_AB,  INSN_MACRO,             0,              I1,     0,      IOCT|IOCTP|IOCT2        },
 {"lwc1",    "T,o(b)",  0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      },
 {"lwc1",    "E,o(b)",  0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      },
 {"lwc1",    "T,A(b)",  0,    (int) M_LWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
 {"lwc1",    "E,A(b)",  0,    (int) M_LWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
 {"l.s",     "T,o(b)",  0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      }, /* lwc1 */
 {"l.s",     "T,A(b)",  0,    (int) M_LWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
-{"lwc2",    "E,o(b)",  0xc8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1,             IOCT|IOCTP|IOCT2|EE     },
-{"lwc2",    "E,A(b)",  0,    (int) M_LWC2_AB,  INSN_MACRO,             0,              I1,             IOCT|IOCTP|IOCT2|EE     },
-{"lwc3",    "E,o(b)",  0xcc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1,             IOCT|IOCTP|IOCT2|EE     },
-{"lwc3",    "E,A(b)",  0,    (int) M_LWC3_AB,  INSN_MACRO,             0,              I1,             IOCT|IOCTP|IOCT2|EE     },
+{"lwc2",    "E,o(b)",  0xc8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"lwc2",    "E,A(b)",  0,    (int) M_LWC2_AB,  INSN_MACRO,             0,              I1,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"lwc3",    "E,o(b)",  0xcc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"lwc3",    "E,A(b)",  0,    (int) M_LWC3_AB,  INSN_MACRO,             0,              I1,     0,      IOCT|IOCTP|IOCT2|EE     },
 {"lwl",     "t,o(b)",  0x88000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
 {"lwl",     "t,A(b)",  0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I1      },
 {"lcache",  "t,o(b)",  0x88000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      }, /* same */
@@ -940,11 +940,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lwr",     "t,A(b)",  0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I1      },
 {"flush",   "t,o(b)",  0x98000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      }, /* same */
 {"flush",   "t,A(b)",  0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I2      }, /* as lwr */
-{"fork",    "d,s,t",   0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t,    0,              MT32    },
+{"fork",    "d,s,t",   0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t,    0,              0,      MT32    },
 {"lwu",     "t,o(b)",  0x9c000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I3      },
 {"lwu",     "t,A(b)",  0,    (int) M_LWU_AB,   INSN_MACRO,             0,              I3      },
 {"lwxc1",   "D,t(b)",  0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_S, 0,             I4_33   },
-{"lwxs",    "d,t(b)",  0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d,     0,              SMT     },
+{"lwxs",    "d,t(b)",  0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d,     0,              0,      SMT     },
 {"macc",    "d,s,t",   0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
 {"macc",    "d,s,t",   0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
 {"maccs",   "d,s,t",   0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
@@ -972,25 +972,25 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,                L1      },
 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,                I32|N55 },
 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,                G1      },
-{"madd",    "7,s,t",   0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D32     },
+{"madd",    "7,s,t",   0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         0,      D32     },
 {"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,                G1      },
 {"madd1",   "s,t",      0x70000020, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,                EE      },
 {"madd1",   "d,s,t",    0x70000020, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,                EE      },
 {"madda.s", "S,T",     0x4600001e, 0xffe007ff, RD_S|RD_T|FP_S,              0,         EE      },
-{"maddp",   "s,t",      0x70000441, 0xfc00ffff,        RD_s|RD_t|MOD_HILO,          0,         SMT     },
+{"maddp",   "s,t",      0x70000441, 0xfc00ffff,        RD_s|RD_t|MOD_HILO,          0,         0,      SMT     },
 {"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,                L1      },
 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,                I32|N55 },
 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,                G1      },
-{"maddu",   "7,s,t",   0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D32     },
+{"maddu",   "7,s,t",   0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         0,      D32     },
 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,                G1      },
 {"maddu1",  "s,t",      0x70000021, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,                EE      },
 {"maddu1",  "d,s,t",    0x70000021, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,                EE      },
 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,    0,              N411    },
-{"max.ob",  "X,Y,Q",   0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
+{"max.ob",  "X,Y,Q",   0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1,    MX      },
 {"max.ob",  "D,S,T",   0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"max.ob",  "D,S,T[e]",        0x48000007, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"max.ob",  "D,S,k",   0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
-{"max.qh",  "X,Y,Q",   0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
+{"max.qh",  "X,Y,Q",   0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      MX      },
 {"max.s",   "D,S,T",   0x46000028, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,    0,              EE      },
 {"mfbpc",   "t",       0x4000c000, 0xffe0ffff, LCD|WR_t|RD_C0,         0,              EE      },
 {"mfdab",   "t",       0x4000c004, 0xffe0ffff, LCD|WR_t|RD_C0,         0,              EE      },
@@ -1001,30 +1001,30 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mfiabm",  "t",       0x4000c003, 0xffe0ffff, LCD|WR_t|RD_C0,         0,              EE      },
 {"mfpc",    "t,P",     0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0,         0,              M1|N5|EE        },
 {"mfps",    "t,P",     0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0,         0,              M1|N5|EE        },
-{"mftacx",  "d",       0x41020021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
-{"mftacx",  "d,*",     0x41020021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
-{"mftc0",   "d,+t",    0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
-{"mftc0",   "d,+T",    0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
-{"mftc0",   "d,E,H",   0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
-{"mftc1",   "d,T",     0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,             MT32    },
-{"mftc1",   "d,E",     0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,             MT32    },
-{"mftc2",   "d,E",     0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32,           IOCT|IOCTP|IOCT2        },
-{"mftdsp",  "d",       0x41100021, 0xffff07ff, TRAP|WR_d,              0,              MT32    },
-{"mftgpr",  "d,t",     0x41000020, 0xffe007ff, TRAP|WR_d|RD_t,         0,              MT32    },
-{"mfthc1",  "d,T",     0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,             MT32    },
-{"mfthc1",  "d,E",     0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,             MT32    },
-{"mfthc2",  "d,E",     0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32,           IOCT|IOCTP|IOCT2        },
-{"mfthi",   "d",       0x41010021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
-{"mfthi",   "d,*",     0x41010021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
-{"mftlo",   "d",       0x41000021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
-{"mftlo",   "d,*",     0x41000021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
-{"mftr",    "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d,            0,              MT32    },
+{"mftacx",  "d",       0x41020021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              0,      MT32    },
+{"mftacx",  "d,*",     0x41020021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              0,      MT32    },
+{"mftc0",   "d,+t",    0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0,    0,              0,      MT32    },
+{"mftc0",   "d,+T",    0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,              0,      MT32    },
+{"mftc0",   "d,E,H",   0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,              0,      MT32    },
+{"mftc1",   "d,T",     0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,             0,      MT32    },
+{"mftc1",   "d,E",     0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,             0,      MT32    },
+{"mftc2",   "d,E",     0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              0,      MT32,           IOCT|IOCTP|IOCT2        },
+{"mftdsp",  "d",       0x41100021, 0xffff07ff, TRAP|WR_d,              0,              0,      MT32    },
+{"mftgpr",  "d,t",     0x41000020, 0xffe007ff, TRAP|WR_d|RD_t,         0,              0,      MT32    },
+{"mfthc1",  "d,T",     0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,             0,      MT32    },
+{"mfthc1",  "d,E",     0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,             0,      MT32    },
+{"mfthc2",  "d,E",     0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              0,      MT32,           IOCT|IOCTP|IOCT2        },
+{"mfthi",   "d",       0x41010021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              0,      MT32    },
+{"mfthi",   "d,*",     0x41010021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              0,      MT32    },
+{"mftlo",   "d",       0x41000021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              0,      MT32    },
+{"mftlo",   "d,*",     0x41000021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              0,      MT32    },
+{"mftr",    "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d,            0,              0,      MT32    },
 {"mfc0",    "t,G",     0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
 {"mfc0",    "t,+D",0x40000000, 0xffe007f8,     LCD|WR_t|RD_C0,         0,              I32     },
 {"mfc0",    "t,G,H",   0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I32     },
-{"mfgc0",    "t,G",    0x40600000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              IVIRT   },
-{"mfgc0",    "t,+D",   0x40600000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              IVIRT   },
-{"mfgc0",    "t,G,H",  0x40600000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              IVIRT   },
+{"mfgc0",    "t,G",    0x40600000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              0,      IVIRT   },
+{"mfgc0",    "t,+D",   0x40600000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              0,      IVIRT   },
+{"mfgc0",    "t,G,H",  0x40600000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              0,      IVIRT   },
 {"mfc1",    "t,S",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
 {"mfc1",    "t,G",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
 {"mfhc1",   "t,S",     0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I33     },
@@ -1034,49 +1034,49 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* mfc3 is at the bottom of the table.  */
 {"mfdr",    "t,G",     0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0,         0,              N5      },
 {"mfhi",    "d",       0x00000010, 0xffff07ff, WR_d|RD_HI,             0,              I1      },
-{"mfhi",    "d,9",     0x00000010, 0xff9f07ff, WR_d|RD_HI,             0,              D32     },
+{"mfhi",    "d,9",     0x00000010, 0xff9f07ff, WR_d|RD_HI,             0,              0,      D32     },
 {"mfhi1",   "d",       0x70000010, 0xffff07ff, WR_d|RD_HI,             0,              EE      },
 {"mflo",    "d",       0x00000012, 0xffff07ff, WR_d|RD_LO,             0,              I1      },
-{"mflo",    "d,9",     0x00000012, 0xff9f07ff, WR_d|RD_LO,             0,              D32     },
+{"mflo",    "d,9",     0x00000012, 0xff9f07ff, WR_d|RD_LO,             0,              0,      D32     },
 {"mflo1",   "d",       0x70000012, 0xffff07ff, WR_d|RD_LO,             0,              EE      },
-{"mflhxu",  "d",       0x00000052, 0xffff07ff, WR_d|MOD_HILO,          0,              SMT     },
+{"mflhxu",  "d",       0x00000052, 0xffff07ff, WR_d|MOD_HILO,          0,              0,      SMT     },
 {"mfcr",    "t,s",     0x70000018, 0xfc00ffff, WR_t,                   0,              XLR     },
 {"mfsa",    "d",       0x00000028, 0xffff07ff, WR_d,                   0,              EE      },
-{"min.ob",  "X,Y,Q",   0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
+{"min.ob",  "X,Y,Q",   0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1,    MX      },
 {"min.ob",  "D,S,T",   0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"min.ob",  "D,S,T[e]",        0x48000006, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"min.ob",  "D,S,k",   0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
-{"min.qh",  "X,Y,Q",   0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
+{"min.qh",  "X,Y,Q",   0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      MX      },
 {"min.s",   "D,S,T",   0x46000029, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,    0,              EE      },
-{"mov.d",   "D,S",     0x46200006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1,     SF      },
+{"mov.d",   "D,S",     0x46200006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1,     0,      SF      },
 {"mov.s",   "D,S",     0x46000006, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
 {"mov.ps",  "D,S",     0x46c00006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5_33|IL2F      },
 {"mov.ps",  "D,S",     0x45600006, 0xffff003f, WR_D|RD_S|FP_D,         0,              IL2E    },
 {"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,          I4_32  },
 {"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,             I4_32   },
-{"movf.l",  "D,S,N",   0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
-{"movf.l",  "X,Y,N",   0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
+{"movf.l",  "D,S,N",   0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              SB1,    MX      },
+{"movf.l",  "X,Y,N",   0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              SB1,    MX      },
 {"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,             I4_32   },
 {"movf.ps", "D,S,N",   0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5_33   },
 {"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              I4_32|IL2E|IL2F|EE      },
 {"movnz",   "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              IL2E|IL2F|IL3A  },
 {"ffc",     "d,v",     0x0000000b, 0xfc1f07ff, WR_d|RD_s,              0,              L1      },
 {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             I4_32   },
-{"movn.l",  "D,S,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             MX|SB1  },
-{"movn.l",  "X,Y,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             MX|SB1  },
+{"movn.l",  "D,S,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             SB1,    MX      },
+{"movn.l",  "X,Y,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             SB1,    MX      },
 {"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,             I4_32   },
 {"movn.ps", "D,S,t",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             I5_33   },
 {"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,          I4_32   },
 {"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,             I4_32   },
-{"movt.l",  "D,S,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,             MX|SB1  },
-{"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,             MX|SB1  },
+{"movt.l",  "D,S,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,             SB1,    MX      },
+{"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,             SB1,    MX      },
 {"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,             I4_32   },
 {"movt.ps", "D,S,N",   0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5_33   },
 {"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              I4_32|IL2E|IL2F|EE      },
 {"ffs",     "d,v",     0x0000000a, 0xfc1f07ff, WR_d|RD_s,              0,              L1      },
 {"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             I4_32   },
-{"movz.l",  "D,S,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             MX|SB1  },
-{"movz.l",  "X,Y,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             MX|SB1  },
+{"movz.l",  "D,S,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             SB1,    MX      },
+{"movz.l",  "X,Y,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             SB1,    MX      },
 {"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,             I4_32   },
 {"movz.ps", "D,S,t",    0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             I5_33   },
 {"msac",    "d,s,t",   0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
@@ -1084,7 +1084,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msachi",  "d,s,t",   0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
 {"msachiu", "d,s,t",   0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
 /* move is at the top of the table.  */
-{"msgn.qh", "X,Y,Q",   0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
+{"msgn.qh", "X,Y,Q",   0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      MX      },
 {"msgsnd",  "t",       0,    (int) M_MSGSND,   INSN_MACRO,             0,             XLR      },
 {"msgld",   "",        0,    (int) M_MSGLD,    INSN_MACRO,             0,             XLR      },
 {"msgld",   "t",       0,    (int) M_MSGLD_T,  INSN_MACRO,             0,             XLR      },
@@ -1102,11 +1102,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msub.ps",    "D,S,T",        0x71600019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,     0,              L1      },
 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,             I32|N55 },
-{"msub",    "7,s,t",   0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
+{"msub",    "7,s,t",   0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D32     },
 {"msuba.s", "S,T",     0x4600001f, 0xffe007ff, RD_S|RD_T|FP_S,         0,              EE      },
 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,     0,              L1      },
 {"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,             I32|N55 },
-{"msubu",   "7,s,t",   0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
+{"msubu",   "7,s,t",   0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D32     },
 {"mtbpc",   "t",       0x4080c000, 0xffe0ffff, COD|RD_t|WR_C0,         0,              EE      },
 {"mtdab",   "t",       0x4080c004, 0xffe0ffff, COD|RD_t|WR_C0,         0,              EE      },
 {"mtdabm",  "t",       0x4080c005, 0xffe0ffff, COD|RD_t|WR_C0,         0,              EE      },
@@ -1119,9 +1119,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtc0",    "t,G",     0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I1      },
 {"mtc0",    "t,+D",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I32     },
 {"mtc0",    "t,G,H",   0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I32     },
-{"mtgc0",   "t,G",     0x40600200, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              IVIRT   },
-{"mtgc0",   "t,+D",    0x40600200, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              IVIRT   },
-{"mtgc0",   "t,G,H",   0x40600200, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              IVIRT   },
+{"mtgc0",   "t,G",     0x40600200, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              0,      IVIRT   },
+{"mtgc0",   "t,+D",    0x40600200, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              0,      IVIRT   },
+{"mtgc0",   "t,G,H",   0x40600200, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              0,      IVIRT   },
 {"mtc1",    "t,S",     0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
 {"mtc1",    "t,G",     0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
 {"mthc1",   "t,S",     0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I33     },
@@ -1131,12 +1131,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* mtc3 is at the bottom of the table.  */
 {"mtdr",    "t,G",     0x7080003d, 0xffe007ff, COD|RD_t|WR_C0,         0,              N5      },
 {"mthi",    "s",       0x00000011, 0xfc1fffff, RD_s|WR_HI,             0,              I1      },
-{"mthi",    "s,7",     0x00000011, 0xfc1fe7ff, RD_s|WR_HI,             0,              D32     },
+{"mthi",    "s,7",     0x00000011, 0xfc1fe7ff, RD_s|WR_HI,             0,              0,      D32     },
 {"mthi1",   "s",       0x70000011, 0xfc1fffff, RD_s|WR_HI,             0,              EE      },
 {"mtlo",    "s",       0x00000013, 0xfc1fffff, RD_s|WR_LO,             0,              I1      },
-{"mtlo",    "s,7",     0x00000013, 0xfc1fe7ff, RD_s|WR_LO,             0,              D32     },
+{"mtlo",    "s,7",     0x00000013, 0xfc1fe7ff, RD_s|WR_LO,             0,              0,      D32     },
 {"mtlo1",   "s",       0x70000013, 0xfc1fffff, RD_s|WR_LO,             0,              EE      },
-{"mtlhx",   "s",       0x00000053, 0xfc1fffff, RD_s|MOD_HILO,          0,              SMT     },
+{"mtlhx",   "s",       0x00000053, 0xfc1fffff, RD_s|MOD_HILO,          0,              0,      SMT     },
 {"mtcr",    "t,s",      0x70000019, 0xfc00ffff, RD_t,                  0,              XLR     },
 {"mtm0",    "s",       0x70000008, 0xfc1fffff, RD_s,                   0,              IOCT    },
 {"mtm1",    "s",       0x7000000c, 0xfc1fffff, RD_s,                   0,              IOCT    },
@@ -1147,84 +1147,84 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtsa",    "s",       0x00000029, 0xfc1fffff, RD_s,                   0,              EE      },
 {"mtsab",   "s,j",     0x04180000, 0xfc1f0000, RD_s,                   0,              EE      },
 {"mtsah",   "s,j",     0x04190000, 0xfc1f0000, RD_s,                   0,              EE      },
-{"mttc0",   "t,G",     0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
-{"mttc0",   "t,+D",    0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
-{"mttc0",   "t,G,H",   0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
-{"mttc1",   "t,S",     0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,             MT32    },
-{"mttc1",   "t,G",     0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,             MT32    },
-{"mttc2",   "t,g",     0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           MT32,           IOCT|IOCTP|IOCT2        },
-{"mttacx",  "t",       0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
-{"mttacx",  "t,&",     0x41801021, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
-{"mttdsp",  "t",       0x41808021, 0xffe0ffff, TRAP|RD_t,              0,              MT32    },
-{"mttgpr",  "t,d",     0x41800020, 0xffe007ff, TRAP|WR_d|RD_t,         0,              MT32    },
-{"mtthc1",  "t,S",     0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,             MT32    },
-{"mtthc1",  "t,G",     0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,             MT32    },
-{"mtthc2",  "t,g",     0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           MT32,           IOCT|IOCTP|IOCT2        },
-{"mtthi",   "t",       0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
-{"mtthi",   "t,&",     0x41800821, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
-{"mttlo",   "t",       0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
-{"mttlo",   "t,&",     0x41800021, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
-{"mttr",    "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t,            0,              MT32    },
-{"mul.d",   "D,V,T",   0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1,     SF      },
+{"mttc0",   "t,G",     0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           0,      MT32    },
+{"mttc0",   "t,+D",    0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           0,      MT32    },
+{"mttc0",   "t,G,H",   0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           0,      MT32    },
+{"mttc1",   "t,S",     0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,             0,      MT32    },
+{"mttc1",   "t,G",     0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,             0,      MT32    },
+{"mttc2",   "t,g",     0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           0,      MT32,   IOCT|IOCTP|IOCT2        },
+{"mttacx",  "t",       0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              0,      MT32    },
+{"mttacx",  "t,&",     0x41801021, 0xffe09fff, TRAP|WR_a|RD_t,         0,              0,      MT32    },
+{"mttdsp",  "t",       0x41808021, 0xffe0ffff, TRAP|RD_t,              0,              0,      MT32    },
+{"mttgpr",  "t,d",     0x41800020, 0xffe007ff, TRAP|WR_d|RD_t,         0,              0,      MT32    },
+{"mtthc1",  "t,S",     0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,             0,      MT32    },
+{"mtthc1",  "t,G",     0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,             0,      MT32    },
+{"mtthc2",  "t,g",     0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           0,      MT32,   IOCT|IOCTP|IOCT2        },
+{"mtthi",   "t",       0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              0,      MT32    },
+{"mtthi",   "t,&",     0x41800821, 0xffe09fff, TRAP|WR_a|RD_t,         0,              0,      MT32    },
+{"mttlo",   "t",       0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              0,      MT32    },
+{"mttlo",   "t,&",     0x41800021, 0xffe09fff, TRAP|WR_a|RD_t,         0,              0,      MT32    },
+{"mttr",    "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t,            0,              0,      MT32    },
+{"mul.d",   "D,V,T",   0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1,     0,      SF      },
 {"mul.s",   "D,V,T",   0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
-{"mul.ob",  "X,Y,Q",   0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
+{"mul.ob",  "X,Y,Q",   0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1,    MX      },
 {"mul.ob",  "D,S,T",   0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"mul.ob",  "D,S,T[e]",        0x48000030, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"mul.ob",  "D,S,k",   0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"mul.ps",  "D,V,T",   0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33|IL2F      },
 {"mul.ps",  "D,V,T",   0x45600002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              IL2E    },
-{"mul.qh",  "X,Y,Q",   0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
+{"mul.qh",  "X,Y,Q",   0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      MX      },
 {"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,             I32|P3|N55},
 {"mul",     "d,s,t",   0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N54     },
 {"mul",     "d,v,t",   0,    (int) M_MUL,      INSN_MACRO,             0,              I1      },
 {"mul",     "d,v,I",   0,    (int) M_MUL_I,    INSN_MACRO,             0,              I1      },
-{"mula.ob", "Y,Q",     0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
+{"mula.ob", "Y,Q",     0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        SB1,    MX      },
 {"mula.ob", "S,T",     0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"mula.ob", "S,T[e]",  0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"mula.ob", "S,k",     0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
-{"mula.qh", "Y,Q",     0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
+{"mula.qh", "Y,Q",     0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        0,      MX      },
 {"mula.s",  "V,T",     0x4600001a, 0xffe007ff, RD_S|RD_T|FP_S,         0,              EE      },
 {"mulhi",   "d,s,t",   0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
 {"mulhiu",  "d,s,t",   0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
-{"mull.ob", "Y,Q",     0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
+{"mull.ob", "Y,Q",     0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        SB1,    MX      },
 {"mull.ob", "S,T",     0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"mull.ob", "S,T[e]",  0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"mull.ob", "S,k",     0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
-{"mull.qh", "Y,Q",     0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
+{"mull.qh", "Y,Q",     0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        0,      MX      },
 {"mulo",    "d,v,t",   0,    (int) M_MULO,     INSN_MACRO,             0,              I1      },
 {"mulo",    "d,v,I",   0,    (int) M_MULO_I,   INSN_MACRO,             0,              I1      },
 {"mulou",   "d,v,t",   0,    (int) M_MULOU,    INSN_MACRO,             0,              I1      },
 {"mulou",   "d,v,I",   0,    (int) M_MULOU_I,  INSN_MACRO,             0,              I1      },
-{"mulr.ps", "D,S,T",   0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
+{"mulr.ps", "D,S,T",   0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      M3D     },
 {"muls",    "d,s,t",   0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
 {"mulsu",   "d,s,t",   0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
 {"mulshi",  "d,s,t",   0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
 {"mulshiu", "d,s,t",   0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
-{"muls.ob", "Y,Q",     0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
+{"muls.ob", "Y,Q",     0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        SB1,    MX      },
 {"muls.ob", "S,T",     0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"muls.ob", "S,T[e]",  0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"muls.ob", "S,k",     0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
-{"muls.qh", "Y,Q",     0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
-{"mulsl.ob", "Y,Q",    0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
+{"muls.qh", "Y,Q",     0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        0,      MX      },
+{"mulsl.ob", "Y,Q",    0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        SB1,    MX      },
 {"mulsl.ob", "S,T",    0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"mulsl.ob", "S,k",    0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
-{"mulsl.qh", "Y,Q",    0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
+{"mulsl.qh", "Y,Q",    0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        0,      MX      },
 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,             I1      },
-{"mult",    "7,s,t",   0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D32     },
+{"mult",    "7,s,t",   0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              0,      D32     },
 {"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,                G1      },
 {"mult1",   "s,t",      0x70000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,             EE      },
 {"mult1",   "d,s,t",    0x70000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,                EE      },
-{"multp",   "s,t",     0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              SMT     },
+{"multp",   "s,t",     0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              0,      SMT     },
 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,             I1      },
-{"multu",   "7,s,t",   0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D32     },
+{"multu",   "7,s,t",   0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              0,      D32     },
 {"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,                G1      },
 {"multu1",  "s,t",      0x70000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,             EE      },
 {"multu1",  "d,s,t",    0x70000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,                EE      },
 {"mulu",    "d,s,t",   0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
 {"neg",     "d,w",     0x00000022, 0xffe007ff, WR_d|RD_t,              0,              I1      }, /* sub 0 */
 {"negu",    "d,w",     0x00000023, 0xffe007ff, WR_d|RD_t,              0,              I1      }, /* subu 0 */
-{"neg.d",   "D,V",     0x46200007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1,     SF      },
+{"neg.d",   "D,V",     0x46200007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1,     0,      SF      },
 {"neg.s",   "D,V",     0x46000007, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
 {"neg.ps",  "D,V",     0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5_33|IL2F      },
 {"neg.ps",  "D,V",     0x45600007, 0xffff003f, WR_D|RD_S|FP_D,         0,              IL2E    },
@@ -1251,21 +1251,21 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"nor",     "t,r,I",   0,    (int) M_NOR_I,    INSN_MACRO,             0,              I1      },
 {"nor",        "D,S,T",        0x47a00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
 {"nor",        "D,S,T",        0x4ba00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
-{"nor.ob",  "X,Y,Q",   0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
+{"nor.ob",  "X,Y,Q",   0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1,    MX      },
 {"nor.ob",  "D,S,T",   0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"nor.ob",  "D,S,T[e]",        0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"nor.ob",  "D,S,k",   0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
-{"nor.qh",  "X,Y,Q",   0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
+{"nor.qh",  "X,Y,Q",   0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      MX      },
 {"not",     "d,v",     0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t,         0,              I1      },/*nor d,s,0*/
 {"or",      "d,v,t",   0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"or",      "t,r,I",   0,    (int) M_OR_I,     INSN_MACRO,             0,              I1      },
 {"or", "D,S,T",        0x45a00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
 {"or", "D,S,T",        0x4b20000c,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
-{"or.ob",   "X,Y,Q",   0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
+{"or.ob",   "X,Y,Q",   0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1,    MX      },
 {"or.ob",   "D,S,T",   0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"or.ob",   "D,S,T[e]",        0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"or.ob",   "D,S,k",   0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
-{"or.qh",   "X,Y,Q",   0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
+{"or.qh",   "X,Y,Q",   0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      MX      },
 {"ori",     "t,r,i",   0x34000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
 {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
 {"pabsdiffc.ob", "Y,Q",        0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        SB1     },
@@ -1304,16 +1304,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"pextuw",  "d,s,t",   0x700004a8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              MMI     },
 {"phmadh",  "d,s,t",   0x70000449, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              MMI     },
 {"phmsbh",  "d,s,t",   0x70000549, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              MMI     },
-{"pickf.ob", "X,Y,Q",  0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
+{"pickf.ob", "X,Y,Q",  0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1,    MX      },
 {"pickf.ob", "D,S,T",  0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f,        WR_D|RD_S|RD_T,         0,              N54     },
 {"pickf.ob", "D,S,k",  0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
-{"pickf.qh", "X,Y,Q",  0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
-{"pickt.ob", "X,Y,Q",  0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
+{"pickf.qh", "X,Y,Q",  0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      MX      },
+{"pickt.ob", "X,Y,Q",  0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1,    MX      },
 {"pickt.ob", "D,S,T",  0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f,        WR_D|RD_S|RD_T,         0,              N54     },
 {"pickt.ob", "D,S,k",  0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
-{"pickt.qh", "X,Y,Q",  0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
+{"pickt.qh", "X,Y,Q",  0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      MX      },
 {"pinteh",  "d,s,t",   0x700002a9, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              MMI     },
 {"pinth",   "d,s,t",   0x70000289, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              MMI     },
 {"pll.ps",  "D,V,T",   0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33   },
@@ -1361,7 +1361,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
   /* pref and prefx are at the start of the table.  */
 {"pul.ps",  "D,V,T",   0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33   },
 {"puu.ps",  "D,V,T",   0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33   },
-{"pperm",   "s,t",     0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t,     0,              SMT     },
+{"pperm",   "s,t",     0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t,     0,              0,      SMT     },
 {"qfsrv",   "d,s,t",   0x700006e8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              MMI     },
 {"qmac.00", "s,t",     0x70000412, 0xfc00ffff, MOD_HILO|RD_s|RD_t,     0,              IOCT2   },
 {"qmac.01", "s,t",     0x70000452, 0xfc00ffff, MOD_HILO|RD_s|RD_t,     0,              IOCT2   },
@@ -1371,24 +1371,24 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"qmacs.01", "s,t",    0x70000052, 0xfc00ffff, MOD_HILO|RD_s|RD_t,     0,              IOCT2   },
 {"qmacs.02", "s,t",    0x70000092, 0xfc00ffff, MOD_HILO|RD_s|RD_t,     0,              IOCT2   },
 {"qmacs.03", "s,t",    0x700000d2, 0xfc00ffff, MOD_HILO|RD_s|RD_t,     0,              IOCT2   },
-{"rach.ob", "X",       0x7a00003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
+{"rach.ob", "X",       0x7a00003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        SB1,    MX      },
 {"rach.ob", "D",       0x4a00003f, 0xfffff83f, WR_D,                   0,              N54     },
-{"rach.qh", "X",       0x7a20003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
-{"racl.ob", "X",       0x7800003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
+{"rach.qh", "X",       0x7a20003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        0,      MX      },
+{"racl.ob", "X",       0x7800003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        SB1,    MX      },
 {"racl.ob", "D",       0x4800003f, 0xfffff83f, WR_D,                   0,              N54     },
-{"racl.qh", "X",       0x7820003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
-{"racm.ob", "X",       0x7900003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
+{"racl.qh", "X",       0x7820003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        0,      MX      },
+{"racm.ob", "X",       0x7900003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        SB1,    MX      },
 {"racm.ob", "D",       0x4900003f, 0xfffff83f, WR_D,                   0,              N54     },
-{"racm.qh", "X",       0x7920003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
+{"racm.qh", "X",       0x7920003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        0,      MX      },
 {"recip.d", "D,S",     0x46200015, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4_33   },
 {"recip.ps","D,S",     0x46c00015, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
 {"recip.s", "D,S",     0x46000015, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4_33   },
-{"recip1.d",  "D,S",   0x4620001d, 0xffff003f, WR_D|RD_S|FP_D,         0,              M3D     },
-{"recip1.ps", "D,S",   0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
-{"recip1.s",  "D,S",   0x4600001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
-{"recip2.d",  "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
-{"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
-{"recip2.s",  "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
+{"recip1.d",  "D,S",   0x4620001d, 0xffff003f, WR_D|RD_S|FP_D,         0,              0,      M3D     },
+{"recip1.ps", "D,S",   0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              0,      M3D     },
+{"recip1.s",  "D,S",   0x4600001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              0,      M3D     },
+{"recip2.d",  "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      M3D     },
+{"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              0,      M3D     },
+{"recip2.s",  "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              0,      M3D     },
 {"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I1      },
 {"rem",     "d,v,t",   0,    (int) M_REM_3,    INSN_MACRO,             0,              I1      },
 {"rem",     "d,v,I",   0,    (int) M_REM_3I,   INSN_MACRO,             0,              I1      },
@@ -1398,41 +1398,41 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"rdhwr",   "t,K",     0x7c00003b, 0xffe007ff, WR_t,                   0,              I33     },
 {"rdpgpr",  "d,w",     0x41400000, 0xffe007ff, WR_d,                   0,              I33     },
 /* rfe is moved below as it now conflicts with tlbgp */
-{"rnas.qh", "X,Q",     0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
-{"rnau.ob", "X,Q",     0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
-{"rnau.qh", "X,Q",     0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
-{"rnes.qh", "X,Q",     0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
-{"rneu.ob", "X,Q",     0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
-{"rneu.qh", "X,Q",     0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
+{"rnas.qh", "X,Q",     0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        0,      MX      },
+{"rnau.ob", "X,Q",     0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        SB1,    MX      },
+{"rnau.qh", "X,Q",     0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        0,      MX      },
+{"rnes.qh", "X,Q",     0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        0,      MX      },
+{"rneu.ob", "X,Q",     0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        SB1,    MX      },
+{"rneu.qh", "X,Q",     0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        0,      MX      },
 {"rol",     "d,v,t",   0,    (int) M_ROL,      INSN_MACRO,             0,              I1      },
 {"rol",     "d,v,I",   0,    (int) M_ROL_I,    INSN_MACRO,             0,              I1      },
 {"ror",     "d,v,t",   0,    (int) M_ROR,      INSN_MACRO,             0,              I1      },
 {"ror",     "d,v,I",   0,    (int) M_ROR_I,    INSN_MACRO,             0,              I1      },
-{"ror",            "d,w,<",    0x00200002, 0xffe0003f, WR_d|RD_t,              0,              N5|I33|SMT },
-{"rorv",    "d,t,s",   0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              N5|I33|SMT },
-{"rotl",    "d,v,t",   0,    (int) M_ROL,      INSN_MACRO,             0,              I33|SMT },
-{"rotl",    "d,v,I",   0,    (int) M_ROL_I,    INSN_MACRO,             0,              I33|SMT },
-{"rotr",    "d,v,t",   0,    (int) M_ROR,      INSN_MACRO,             0,              I33|SMT },
-{"rotr",    "d,v,I",   0,    (int) M_ROR_I,    INSN_MACRO,             0,              I33|SMT },
-{"rotrv",   "d,t,s",   0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              I33|SMT },
+{"ror",            "d,w,<",    0x00200002, 0xffe0003f, WR_d|RD_t,              0,              N5|I33, SMT },
+{"rorv",    "d,t,s",   0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              N5|I33, SMT },
+{"rotl",    "d,v,t",   0,    (int) M_ROL,      INSN_MACRO,             0,              I33,    SMT     },
+{"rotl",    "d,v,I",   0,    (int) M_ROL_I,    INSN_MACRO,             0,              I33,    SMT     },
+{"rotr",    "d,v,t",   0,    (int) M_ROR,      INSN_MACRO,             0,              I33,    SMT     },
+{"rotr",    "d,v,I",   0,    (int) M_ROR_I,    INSN_MACRO,             0,              I33,    SMT     },
+{"rotrv",   "d,t,s",   0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              I33,    SMT     },
 {"round.l.d", "D,S",   0x46200008, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3_33   },
 {"round.l.s", "D,S",   0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3_33   },
-{"round.w.d", "D,S",   0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2,     SF      },
+{"round.w.d", "D,S",   0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2,     0,      SF      },
 {"round.w.s", "D,S",   0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
 {"rsqrt.d", "D,S",     0x46200016, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4_33   },
 {"rsqrt.ps","D,S",     0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
 {"rsqrt.s", "D,S",     0x46000016, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4_33   },
 {"rsqrt.s", "D,S,T",   0x46000016, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              EE      },
-{"rsqrt1.d",  "D,S",   0x4620001e, 0xffff003f, WR_D|RD_S|FP_D,         0,              M3D     },
-{"rsqrt1.ps", "D,S",   0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
-{"rsqrt1.s",  "D,S",   0x4600001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
-{"rsqrt2.d",  "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
-{"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
-{"rsqrt2.s",  "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
-{"rzs.qh",  "X,Q",     0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
-{"rzu.ob",  "X,Q",     0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
+{"rsqrt1.d",  "D,S",   0x4620001e, 0xffff003f, WR_D|RD_S|FP_D,         0,              0,      M3D     },
+{"rsqrt1.ps", "D,S",   0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              0,      M3D     },
+{"rsqrt1.s",  "D,S",   0x4600001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              0,      M3D     },
+{"rsqrt2.d",  "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      M3D     },
+{"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              0,      M3D     },
+{"rsqrt2.s",  "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              0,      M3D     },
+{"rzs.qh",  "X,Q",     0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        0,      MX      },
+{"rzu.ob",  "X,Q",     0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        SB1,    MX      },
 {"rzu.ob",  "D,k",     0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T,         0,              N54     },
-{"rzu.qh",  "X,Q",     0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
+{"rzu.qh",  "X,Q",     0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        0,      MX      },
 {"saa",            "t,o(b)",   0,    (int) M_SAA_OB,   INSN_MACRO,             0,              IOCTP   },
 {"saa",            "t,A(b)",   0,    (int) M_SAA_AB,   INSN_MACRO,             0,              IOCTP   },
 {"saa",            "t,(b)",    0x70000018, 0xfc00ffff, SM|RD_t|RD_b,           0,              IOCTP   },
@@ -1441,10 +1441,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"saad",    "t,(b)",   0x70000019, 0xfc00ffff, SM|RD_t|RD_b,           0,              IOCTP   },
 {"sb",      "t,o(b)",  0xa0000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
 {"sb",      "t,A(b)",  0,    (int) M_SB_AB,    INSN_MACRO,             0,              I1      },
-{"sc",     "t,o(b)",   0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      0,              I2,     EE      },
-{"sc",     "t,A(b)",   0,    (int) M_SC_AB,    INSN_MACRO,             0,              I2,     EE      },
-{"scd",            "t,o(b)",   0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      0,              I3,     EE      },
-{"scd",            "t,A(b)",   0,    (int) M_SCD_AB,   INSN_MACRO,             0,              I3,     EE      },
+{"sc",     "t,o(b)",   0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      0,              I2,     0,      EE      },
+{"sc",     "t,A(b)",   0,    (int) M_SC_AB,    INSN_MACRO,             0,              I2,     0,      EE      },
+{"scd",            "t,o(b)",   0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      0,              I3,     0,      EE      },
+{"scd",            "t,A(b)",   0,    (int) M_SCD_AB,   INSN_MACRO,             0,              I3,     0,      EE      },
 /* The macro has to be first to handle o32 correctly.  */
 {"sd",      "t,o(b)",  0,    (int) M_SD_OB,    INSN_MACRO,             0,              I1      },
 {"sd",      "t,o(b)",  0xfc000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
@@ -1454,15 +1454,15 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sdbbp",   "c,q",     0x0000000e, 0xfc00003f, TRAP,                   0,              G2      },
 {"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,                  0,              I32     },
 {"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,                  0,              I32     },
-{"sdc1",    "T,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2,     SF      },
-{"sdc1",    "E,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2,     SF      },
-{"sdc1",    "T,A(b)",  0,    (int) M_SDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2,     SF      },
-{"sdc1",    "E,A(b)",  0,    (int) M_SDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2,     SF      },
-{"sdc2",    "E,o(b)",  0xf8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I2,             IOCT|IOCTP|IOCT2|EE     },
-{"sdc2",    "E,A(b)",  0,    (int) M_SDC2_AB,  INSN_MACRO,             0,              I2,             IOCT|IOCTP|IOCT2|EE     },
-{"sdc3",    "E,o(b)",  0xfc000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I2,             IOCT|IOCTP|IOCT2|EE     },
-{"sdc3",    "E,A(b)",  0,    (int) M_SDC3_AB,  INSN_MACRO,             0,              I2,             IOCT|IOCTP|IOCT2|EE     },
-{"s.d",     "T,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2,     SF      },
+{"sdc1",    "T,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2,     0,      SF      },
+{"sdc1",    "E,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2,     0,      SF      },
+{"sdc1",    "T,A(b)",  0,    (int) M_SDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2,     0,      SF      },
+{"sdc1",    "E,A(b)",  0,    (int) M_SDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2,     0,      SF      },
+{"sdc2",    "E,o(b)",  0xf8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I2,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"sdc2",    "E,A(b)",  0,    (int) M_SDC2_AB,  INSN_MACRO,             0,              I2,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"sdc3",    "E,o(b)",  0xfc000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I2,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"sdc3",    "E,A(b)",  0,    (int) M_SDC3_AB,  INSN_MACRO,             0,              I2,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"s.d",     "T,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2,     0,      SF      },
 {"s.d",     "T,o(b)",  0,    (int) M_S_DOB,    INSN_MACRO,             INSN2_M_FP_D,   I1      },
 {"s.d",     "T,A(b)",  0,    (int) M_S_DAB,    INSN_MACRO,             INSN2_M_FP_D,   I1      },
 {"sdl",     "t,o(b)",  0xb0000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
@@ -1490,20 +1490,20 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sgtu",    "d,v,I",   0,    (int) M_SGTU_I,   INSN_MACRO,             0,              I1      },
 {"sh",      "t,o(b)",  0xa4000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
 {"sh",      "t,A(b)",  0,    (int) M_SH_AB,    INSN_MACRO,             0,              I1      },
-{"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              MX      },
-{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              MX|SB1  },
+{"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              0,      MX      },
+{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              SB1,    MX      },
 {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T,      0,              N54     },
-{"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              MX      },
-{"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              MX|SB1  },
+{"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              0,      MX      },
+{"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              SB1,    MX      },
 {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T,      0,              N54     },
-{"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              MX      },
-{"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              MX|SB1  },
+{"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              0,      MX      },
+{"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              SB1,    MX      },
 {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T,      0,              N54     },
-{"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              MX      },
+{"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              0,      MX      },
 {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T,      0,              N54     },
-{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              MX      },
-{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              MX      },
-{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              MX|SB1  },
+{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              0,      MX      },
+{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              0,      MX      },
+{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              SB1,    MX      },
 {"sle",     "d,v,t",   0,    (int) M_SLE,      INSN_MACRO,             0,              I1      },
 {"sle",     "d,v,I",   0,    (int) M_SLE_I,    INSN_MACRO,             0,              I1      },
 {"sle",        "S,T",          0x46a0003e,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2E    },
@@ -1517,10 +1517,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sll",     "d,w,<",   0x00000000, 0xffe0003f, WR_d|RD_t,              0,              I1      },
 {"sll",        "D,S,T",        0x45800002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
 {"sll",        "D,S,T",        0x4b00000e,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
-{"sll.ob",  "X,Y,Q",   0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
+{"sll.ob",  "X,Y,Q",   0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1,    MX      },
 {"sll.ob",  "D,S,T[e]",        0x48000010, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"sll.ob",  "D,S,k",   0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
-{"sll.qh",  "X,Y,Q",   0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
+{"sll.qh",  "X,Y,Q",   0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      MX      },
 {"slt",     "d,v,t",   0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"slt",     "d,v,I",   0,    (int) M_SLT_I,    INSN_MACRO,             0,              I1      },
 {"slt",        "S,T",          0x46a0003c,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2E    },
@@ -1539,7 +1539,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sq",      "t,A(b)",  0,    (int) M_SQ_AB,    INSN_MACRO,             0,              MMI     },
 {"sqc2",    "E,o(b)",  0xf8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              EE      },
 {"sqc2",    "E,A(b)",  0,    (int) M_SQC2_AB,  INSN_MACRO,             0,              EE      },
-{"sqrt.d",  "D,S",     0x46200004, 0xffff003f, WR_D|RD_S|FP_D,         0,              I2,     SF      },
+{"sqrt.d",  "D,S",     0x46200004, 0xffff003f, WR_D|RD_S|FP_D,         0,              I2,     0,      SF      },
 {"sqrt.s",  "D,S",     0x46000004, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
 {"sqrt.ps", "D,S",     0x46c00004, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
 {"srav",    "d,t,s",   0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
@@ -1547,35 +1547,35 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sra",     "d,w,<",   0x00000003, 0xffe0003f, WR_d|RD_t,              0,              I1      },
 {"sra",        "D,S,T",        0x45c00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
 {"sra",        "D,S,T",        0x4b40000f,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
-{"sra.qh",  "X,Y,Q",   0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
+{"sra.qh",  "X,Y,Q",   0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      MX      },
 {"srlv",    "d,t,s",   0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
 {"srl",     "d,w,s",   0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* srlv */
 {"srl",     "d,w,<",   0x00000002, 0xffe0003f, WR_d|RD_t,              0,              I1      },
 {"srl",        "D,S,T",        0x45800003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
 {"srl",        "D,S,T",        0x4b00000f,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
-{"srl.ob",  "X,Y,Q",   0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
+{"srl.ob",  "X,Y,Q",   0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1,    MX      },
 {"srl.ob",  "D,S,T[e]",        0x48000012, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"srl.ob",  "D,S,k",   0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
-{"srl.qh",  "X,Y,Q",   0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
+{"srl.qh",  "X,Y,Q",   0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      MX      },
 /* ssnop is at the start of the table.  */
 {"standby", "",         0x42000021, 0xffffffff,        0,                      0,              V1      },
 {"sub",     "d,v,t",   0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"sub",     "d,v,I",   0,    (int) M_SUB_I,    INSN_MACRO,             0,              I1      },
 {"sub",        "D,S,T",        0x45c00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
 {"sub",        "D,S,T",        0x4b40000d,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F|IL3A       },
-{"sub.d",   "D,V,T",   0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1,     SF      },
+{"sub.d",   "D,V,T",   0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1,     0,      SF      },
 {"sub.s",   "D,V,T",   0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
-{"sub.ob",  "X,Y,Q",   0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
+{"sub.ob",  "X,Y,Q",   0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1,    MX      },
 {"sub.ob",  "D,S,T",   0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"sub.ob",  "D,S,T[e]",        0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"sub.ob",  "D,S,k",   0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"sub.ps",  "D,V,T",   0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33|IL2F      },
 {"sub.ps",  "D,V,T",   0x45600001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              IL2E    },
-{"sub.qh",  "X,Y,Q",   0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
-{"suba.ob", "Y,Q",     0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
-{"suba.qh", "Y,Q",     0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
-{"subl.ob", "Y,Q",     0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
-{"subl.qh", "Y,Q",     0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
+{"sub.qh",  "X,Y,Q",   0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      MX      },
+{"suba.ob", "Y,Q",     0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        SB1,    MX      },
+{"suba.qh", "Y,Q",     0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        0,      MX      },
+{"subl.ob", "Y,Q",     0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        SB1,    MX      },
+{"subl.qh", "Y,Q",     0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        0,      MX      },
 {"suba.s",  "V,T",     0x46000019, 0xffe007ff, RD_S|RD_T|FP_S,         0,              EE      },
 {"subu",    "d,v,t",   0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"subu",    "d,v,I",   0,    (int) M_SUBU_I,   INSN_MACRO,             0,              I1      },
@@ -1588,18 +1588,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"swapw",   "t,b",     0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,              XLR     },
 {"swapwu",  "t,b",     0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,              XLR     },
 {"swapd",   "t,b",     0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,              XLR     },
-{"swc0",    "E,o(b)",  0xe0000000, 0xfc000000, SM|RD_C0|RD_b,          0,              I1,             IOCT|IOCTP|IOCT2        },
-{"swc0",    "E,A(b)",  0,    (int) M_SWC0_AB,  INSN_MACRO,             0,              I1,             IOCT|IOCTP|IOCT2        },
+{"swc0",    "E,o(b)",  0xe0000000, 0xfc000000, SM|RD_C0|RD_b,          0,              I1,     0,      IOCT|IOCTP|IOCT2        },
+{"swc0",    "E,A(b)",  0,    (int) M_SWC0_AB,  INSN_MACRO,             0,              I1,     0,      IOCT|IOCTP|IOCT2        },
 {"swc1",    "T,o(b)",  0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      },
 {"swc1",    "E,o(b)",  0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      },
 {"swc1",    "T,A(b)",  0,    (int) M_SWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
 {"swc1",    "E,A(b)",  0,    (int) M_SWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
 {"s.s",     "T,o(b)",  0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      }, /* swc1 */
 {"s.s",     "T,A(b)",  0,    (int) M_SWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
-{"swc2",    "E,o(b)",  0xe8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I1,             IOCT|IOCTP|IOCT2|EE     },
-{"swc2",    "E,A(b)",  0,    (int) M_SWC2_AB,  INSN_MACRO,             0,              I1,             IOCT|IOCTP|IOCT2|EE     },
-{"swc3",    "E,o(b)",  0xec000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I1,             IOCT|IOCTP|IOCT2|EE     },
-{"swc3",    "E,A(b)",  0,    (int) M_SWC3_AB,  INSN_MACRO,             0,              I1,             IOCT|IOCTP|IOCT2|EE     },
+{"swc2",    "E,o(b)",  0xe8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I1,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"swc2",    "E,A(b)",  0,    (int) M_SWC2_AB,  INSN_MACRO,             0,              I1,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"swc3",    "E,o(b)",  0xec000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I1,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"swc3",    "E,A(b)",  0,    (int) M_SWC3_AB,  INSN_MACRO,             0,              I1,     0,      IOCT|IOCTP|IOCT2|EE     },
 {"swl",     "t,o(b)",  0xa8000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
 {"swl",     "t,A(b)",  0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I1      },
 {"scache",  "t,o(b)",  0xa8000000, 0xfc000000, RD_t|RD_b,              0,              I2      }, /* same */
@@ -1644,12 +1644,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,              0,              I1      },
 {"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,              0,              I1      },
 {"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,              0,              I1      },
-{"tlbgr",   "",         0x42000009, 0xffffffff, INSN_TLB,              0,              IVIRT   },
-{"tlbgwi",  "",         0x4200000a, 0xffffffff, INSN_TLB,              0,              IVIRT   },
-{"tlbginv", "",         0x4200000b, 0xffffffff, INSN_TLB,              0,              IVIRT   },
-{"tlbginvf","",         0x4200000c, 0xffffffff, INSN_TLB,              0,              IVIRT   },
-{"tlbgwr",  "",         0x4200000e, 0xffffffff, INSN_TLB,              0,              IVIRT   },
-{"tlbgp",   "",         0x42000010, 0xffffffff, INSN_TLB,              0,              IVIRT   },
+{"tlbgr",   "",         0x42000009, 0xffffffff, INSN_TLB,              0,              0,      IVIRT   },
+{"tlbgwi",  "",         0x4200000a, 0xffffffff, INSN_TLB,              0,              0,      IVIRT   },
+{"tlbginv", "",         0x4200000b, 0xffffffff, INSN_TLB,              0,              0,      IVIRT   },
+{"tlbginvf","",         0x4200000c, 0xffffffff, INSN_TLB,              0,              0,      IVIRT   },
+{"tlbgwr",  "",         0x4200000e, 0xffffffff, INSN_TLB,              0,              0,      IVIRT   },
+{"tlbgp",   "",         0x42000010, 0xffffffff, INSN_TLB,              0,              0,      IVIRT   },
 {"tlti",    "s,j",     0x040a0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
 {"tlt",     "s,t",     0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
 {"tlt",     "s,t,q",   0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
@@ -1667,13 +1667,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"tne",     "s,I",     0,    (int) M_TNE_I,    INSN_MACRO,             0,              I2      },
 {"trunc.l.d", "D,S",   0x46200009, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3_33   },
 {"trunc.l.s", "D,S",   0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3_33   },
-{"trunc.w.d", "D,S",   0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2,     SF      },
-{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2,     SF      },
-{"trunc.w.d", "D,S,t", 0,    (int) M_TRUNCWD,  INSN_MACRO,             INSN2_M_FP_S|INSN2_M_FP_D, I1,  SF      },
+{"trunc.w.d", "D,S",   0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2,     0,      SF      },
+{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2,     0,      SF      },
+{"trunc.w.d", "D,S,t", 0,    (int) M_TRUNCWD,  INSN_MACRO,             INSN2_M_FP_S|INSN2_M_FP_D, I1,  0,      SF      },
 {"trunc.w.s", "D,S",   0x46000024, 0xffff003f, WR_D|RD_S|FP_S,         0,              EE      },
-{"trunc.w.s", "D,S",   0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2,     EE      },
-{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2,     EE      },
-{"trunc.w.s", "D,S,t", 0,    (int) M_TRUNCWS,  INSN_MACRO,             INSN2_M_FP_S,   I1,     EE      },
+{"trunc.w.s", "D,S",   0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2,     0,      EE      },
+{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2,     0,      EE      },
+{"trunc.w.s", "D,S,t", 0,    (int) M_TRUNCWS,  INSN_MACRO,             INSN2_M_FP_S,   I1,     0,      EE      },
 {"uld",     "t,o(b)",  0,    (int) M_ULD,      INSN_MACRO,             0,              I3      },
 {"uld",     "t,A(b)",  0,    (int) M_ULD_A,    INSN_MACRO,             0,              I3      },
 {"ulh",     "t,o(b)",  0,    (int) M_ULH,      INSN_MACRO,             0,              I1      },
@@ -1691,12 +1691,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"v3mulu",  "d,v,t",   0x70000011, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              IOCT    },
 {"vmm0",    "d,v,t",   0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              IOCT    },
 {"vmulu",   "d,v,t",   0x7000000f, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              IOCT    },
-{"wach.ob", "Y",       0x7a00003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        MX|SB1  },
+{"wach.ob", "Y",       0x7a00003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        SB1,    MX      },
 {"wach.ob", "S",       0x4a00003e, 0xffff07ff, RD_S,                   0,              N54     },
-{"wach.qh", "Y",       0x7a20003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        MX      },
-{"wacl.ob", "Y,Z",     0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
+{"wach.qh", "Y",       0x7a20003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        0,      MX      },
+{"wacl.ob", "Y,Z",     0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        SB1,    MX      },
 {"wacl.ob", "S,T",     0x4800003e, 0xffe007ff, RD_S|RD_T,              0,              N54     },
-{"wacl.qh", "Y,Z",     0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
+{"wacl.qh", "Y,Z",     0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        0,      MX      },
 {"wait",    "",         0x42000020, 0xffffffff, NODS,                  0,              I3_32   },
 {"wait",    "J",        0x42000020, 0xfe00003f, NODS,                  0,              I32|N55 },
 {"waiti",   "",                0x42000020, 0xffffffff, NODS,                   0,              L1      },
@@ -1706,14 +1706,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"xor",     "t,r,I",   0,    (int) M_XOR_I,    INSN_MACRO,             0,              I1      },
 {"xor",        "D,S,T",        0x47800002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
 {"xor",        "D,S,T",        0x4b800002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
-{"xor.ob",  "X,Y,Q",   0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
+{"xor.ob",  "X,Y,Q",   0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1,    MX      },
 {"xor.ob",  "D,S,T",   0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"xor.ob",  "D,S,T[e]",        0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"xor.ob",  "D,S,k",   0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
-{"xor.qh",  "X,Y,Q",   0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
+{"xor.qh",  "X,Y,Q",   0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              0,      MX      },
 {"xori",    "t,r,i",   0x38000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
-{"yield",   "s",       0x7c000009, 0xfc1fffff, NODS|RD_s,              0,              MT32    },
-{"yield",   "d,s",     0x7c000009, 0xfc1f07ff, NODS|WR_d|RD_s,         0,              MT32    },
+{"yield",   "s",       0x7c000009, 0xfc1fffff, NODS|RD_s,              0,              0,      MT32    },
+{"yield",   "d,s",     0x7c000009, 0xfc1f07ff, NODS|WR_d|RD_s,         0,              0,      MT32    },
 {"zcb",     "(b)",     0x7000071f, 0xfc1fffff, SM|RD_b,                0,              IOCT2   },
 {"zcbt",    "(b)",     0x7000075f, 0xfc1fffff, SM|RD_b,                0,              IOCT2   },
 
@@ -1785,36 +1785,36 @@ const struct mips_opcode mips_builtin_opcodes[] =
 
 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
    instructions so they are here for the latters to take precedence.  */
-{"bc2f",    "p",       0x49000000, 0xffff0000, CBD|RD_CC,              0,              I1,             IOCT|IOCTP|IOCT2        },
-{"bc2f",    "N,p",     0x49000000, 0xffe30000, CBD|RD_CC,              0,              I32,            IOCT|IOCTP|IOCT2        },
-{"bc2fl",   "p",       0x49020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3,          IOCT|IOCTP|IOCT2        },
-{"bc2fl",   "N,p",     0x49020000, 0xffe30000, CBL|RD_CC,              0,              I32,            IOCT|IOCTP|IOCT2        },
-{"bc2t",    "p",       0x49010000, 0xffff0000, CBD|RD_CC,              0,              I1,             IOCT|IOCTP|IOCT2        },
-{"bc2t",    "N,p",     0x49010000, 0xffe30000, CBD|RD_CC,              0,              I32,            IOCT|IOCTP|IOCT2        },
-{"bc2tl",   "p",       0x49030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3,          IOCT|IOCTP|IOCT2        },
-{"bc2tl",   "N,p",     0x49030000, 0xffe30000, CBL|RD_CC,              0,              I32,            IOCT|IOCTP|IOCT2        },
-{"cfc2",    "t,G",     0x48400000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1,             IOCT|IOCTP|IOCT2        },
+{"bc2f",    "p",       0x49000000, 0xffff0000, CBD|RD_CC,              0,              I1,     0,      IOCT|IOCTP|IOCT2        },
+{"bc2f",    "N,p",     0x49000000, 0xffe30000, CBD|RD_CC,              0,              I32,    0,      IOCT|IOCTP|IOCT2        },
+{"bc2fl",   "p",       0x49020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3,  0,      IOCT|IOCTP|IOCT2        },
+{"bc2fl",   "N,p",     0x49020000, 0xffe30000, CBL|RD_CC,              0,              I32,    0,      IOCT|IOCTP|IOCT2        },
+{"bc2t",    "p",       0x49010000, 0xffff0000, CBD|RD_CC,              0,              I1,     0,      IOCT|IOCTP|IOCT2        },
+{"bc2t",    "N,p",     0x49010000, 0xffe30000, CBD|RD_CC,              0,              I32,    0,      IOCT|IOCTP|IOCT2        },
+{"bc2tl",   "p",       0x49030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3,  0,      IOCT|IOCTP|IOCT2        },
+{"bc2tl",   "N,p",     0x49030000, 0xffe30000, CBL|RD_CC,              0,              I32,    0,      IOCT|IOCTP|IOCT2        },
+{"cfc2",    "t,G",     0x48400000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1,     0,      IOCT|IOCTP|IOCT2        },
 {"cfc2.i",  "t,G",     0x48400001, 0xffe007ff, LCD|WR_t|RD_C2,         0,              EE      },
 {"cfc2.ni", "t,G",     0x48400000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              EE      },
-{"ctc2",    "t,G",     0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1,             IOCT|IOCTP|IOCT2        },
+{"ctc2",    "t,G",     0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1,     0,      IOCT|IOCTP|IOCT2        },
 {"ctc2.i",  "t,G",     0x48c00001, 0xffe007ff, COD|RD_t|WR_CC,         0,              EE      },
 {"ctc2.ni", "t,G",     0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              EE      },
 {"dmfc2",   "t,i",     0x48200000, 0xffe00000, LCD|WR_t|RD_C2,         0,              IOCT    },
-{"dmfc2",   "t,G",     0x48200000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I3,             IOCT|IOCTP|IOCT2|EE     },
-{"dmfc2",   "t,G,H",   0x48200000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I64,            IOCT|IOCTP|IOCT2        },
+{"dmfc2",   "t,G",     0x48200000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I3,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"dmfc2",   "t,G,H",   0x48200000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I64,    0,      IOCT|IOCTP|IOCT2        },
 {"dmtc2",   "t,i",     0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,              IOCT    },
-{"dmtc2",   "t,G",     0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I3,             IOCT|IOCTP|IOCT2|EE     },
-{"dmtc2",   "t,G,H",   0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I64,            IOCT|IOCTP|IOCT2        },
-{"mfc2",    "t,G",     0x48000000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1,             IOCT|IOCTP|IOCT2|EE     },
-{"mfc2",    "t,G,H",   0x48000000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I32,            IOCT|IOCTP|IOCT2        },
-{"mfhc2",   "t,G",     0x48600000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I33,            IOCT|IOCTP|IOCT2        },
-{"mfhc2",   "t,G,H",   0x48600000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I33,            IOCT|IOCTP|IOCT2        },
-{"mfhc2",   "t,i",     0x48600000, 0xffe00000, LCD|WR_t|RD_C2,         0,              I33,            IOCT|IOCTP|IOCT2        },
-{"mtc2",    "t,G",     0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I1,             IOCT|IOCTP|IOCT2|EE     },
-{"mtc2",    "t,G,H",   0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I32,            IOCT|IOCTP|IOCT2        },
-{"mthc2",   "t,G",     0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I33,            IOCT|IOCTP|IOCT2        },
-{"mthc2",   "t,G,H",   0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I33,            IOCT|IOCTP|IOCT2        },
-{"mthc2",   "t,i",     0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,              I33,            IOCT|IOCTP|IOCT2        },
+{"dmtc2",   "t,G",     0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I3,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"dmtc2",   "t,G,H",   0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I64,    0,      IOCT|IOCTP|IOCT2        },
+{"mfc2",    "t,G",     0x48000000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"mfc2",    "t,G,H",   0x48000000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I32,    0,      IOCT|IOCTP|IOCT2        },
+{"mfhc2",   "t,G",     0x48600000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I33,    0,      IOCT|IOCTP|IOCT2        },
+{"mfhc2",   "t,G,H",   0x48600000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I33,    0,      IOCT|IOCTP|IOCT2        },
+{"mfhc2",   "t,i",     0x48600000, 0xffe00000, LCD|WR_t|RD_C2,         0,              I33,    0,      IOCT|IOCTP|IOCT2        },
+{"mtc2",    "t,G",     0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I1,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"mtc2",    "t,G,H",   0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I32,    0,      IOCT|IOCTP|IOCT2        },
+{"mthc2",   "t,G",     0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I33,    0,      IOCT|IOCTP|IOCT2        },
+{"mthc2",   "t,G,H",   0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I33,    0,      IOCT|IOCTP|IOCT2        },
+{"mthc2",   "t,i",     0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,              I33,    0,      IOCT|IOCTP|IOCT2        },
 {"qmfc2",   "t,G",     0x48200000, 0xffe007ff, WR_t|RD_C2,             0,              EE      },
 {"qmfc2.i", "t,G",     0x48200001, 0xffe007ff, WR_t|RD_C2,             0,              EE      },
 {"qmfc2.ni","t,G",     0x48200000, 0xffe007ff, WR_t|RD_C2,             0,              EE      },
@@ -1823,308 +1823,308 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"qmtc2.ni","t,G",     0x48a00000, 0xffe007ff, RD_t|WR_C2,             0,              EE      },
 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X 
    instructions, so they are here for the latters to take precedence.  */
-{"bc3f",    "p",       0x4d000000, 0xffff0000, CBD|RD_CC,              0,              I1,             IOCT|IOCTP|IOCT2|EE     },
-{"bc3fl",   "p",       0x4d020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3,          IOCT|IOCTP|IOCT2|EE     },
-{"bc3t",    "p",       0x4d010000, 0xffff0000, CBD|RD_CC,              0,              I1,             IOCT|IOCTP|IOCT2|EE     },
-{"bc3tl",   "p",       0x4d030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3,          IOCT|IOCTP|IOCT2|EE     },
-{"cfc3",    "t,G",     0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1,             IOCT|IOCTP|IOCT2|EE     },
-{"ctc3",    "t,G",     0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1,             IOCT|IOCTP|IOCT2|EE     },
-{"dmfc3",   "t,G",     0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I3,             IOCT|IOCTP|IOCT2|EE     },
-{"dmtc3",   "t,G",     0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I3,             IOCT|IOCTP|IOCT2|EE     },
-{"mfc3",    "t,G",     0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1,             IOCT|IOCTP|IOCT2|EE     },
-{"mfc3",    "t,G,H",   0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3,         0,              I32,            IOCT|IOCTP|IOCT2|EE     },
-{"mtc3",    "t,G",     0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I1,             IOCT|IOCTP|IOCT2|EE     },
-{"mtc3",    "t,G,H",   0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,              I32,            IOCT|IOCTP|IOCT2|EE     },
+{"bc3f",    "p",       0x4d000000, 0xffff0000, CBD|RD_CC,              0,              I1,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"bc3fl",   "p",       0x4d020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3,  0,      IOCT|IOCTP|IOCT2|EE     },
+{"bc3t",    "p",       0x4d010000, 0xffff0000, CBD|RD_CC,              0,              I1,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"bc3tl",   "p",       0x4d030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3,  0,      IOCT|IOCTP|IOCT2|EE     },
+{"cfc3",    "t,G",     0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"ctc3",    "t,G",     0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"dmfc3",   "t,G",     0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I3,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"dmtc3",   "t,G",     0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I3,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"mfc3",    "t,G",     0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"mfc3",    "t,G,H",   0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3,         0,              I32,    0,      IOCT|IOCTP|IOCT2|EE     },
+{"mtc3",    "t,G",     0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I1,     0,      IOCT|IOCTP|IOCT2|EE     },
+{"mtc3",    "t,G,H",   0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,              I32,    0,      IOCT|IOCTP|IOCT2|EE     },
 
   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
      4010 any more, so move this insn out of the way.  If the object
      format gave us more info, we could do this right.  */
 {"addciu",  "t,r,j",   0x70000000, 0xfc000000, WR_t|RD_s,              0,              L1      },
 /* MIPS DSP ASE */
-{"absq_s.ph", "d,t",   0x7c000252, 0xffe007ff, WR_d|RD_t,              0,              D32     },
-{"absq_s.pw", "d,t",   0x7c000456, 0xffe007ff, WR_d|RD_t,              0,              D64     },
-{"absq_s.qh", "d,t",   0x7c000256, 0xffe007ff, WR_d|RD_t,              0,              D64     },
-{"absq_s.w", "d,t",    0x7c000452, 0xffe007ff, WR_d|RD_t,              0,              D32     },
-{"addq.ph", "d,s,t",   0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"addq.pw", "d,s,t",   0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"addq.qh", "d,s,t",   0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"addq_s.w", "d,s,t",  0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"addsc",   "d,s,t",   0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"addu.ob", "d,s,t",   0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"addu.qb", "d,s,t",   0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"addwc",   "d,s,t",   0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"bitrev",  "d,t",     0x7c0006d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
-{"bposge32", "p",      0x041c0000, 0xffff0000, CBD,                    0,              D32     },
-{"bposge64", "p",      0x041d0000, 0xffff0000, CBD,                    0,              D64     },
-{"cmp.eq.ph", "s,t",   0x7c000211, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
-{"cmp.eq.pw", "s,t",   0x7c000415, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
-{"cmp.eq.qh", "s,t",   0x7c000215, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
-{"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D64     },
-{"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D32     },
-{"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D64     },
-{"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D32     },
-{"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D64     },
-{"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D32     },
-{"cmp.le.ph", "s,t",   0x7c000291, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
-{"cmp.le.pw", "s,t",   0x7c000495, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
-{"cmp.le.qh", "s,t",   0x7c000295, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
-{"cmp.lt.ph", "s,t",   0x7c000251, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
-{"cmp.lt.pw", "s,t",   0x7c000455, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
-{"cmp.lt.qh", "s,t",   0x7c000255, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
-{"cmpu.eq.ob", "s,t",  0x7c000015, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
-{"cmpu.eq.qb", "s,t",  0x7c000011, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
-{"cmpu.le.ob", "s,t",  0x7c000095, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
-{"cmpu.le.qb", "s,t",  0x7c000091, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
-{"cmpu.lt.ob", "s,t",  0x7c000055, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
-{"cmpu.lt.qb", "s,t",  0x7c000051, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
-{"dextpdp", "t,7,6",   0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,     0,              D64     },
-{"dextpdpv", "t,7,s",  0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,             D64     },
-{"dextp",   "t,7,6",   0x7c0000bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
-{"dextpv",  "t,7,s",   0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
-{"dextr.l", "t,7,6",   0x7c00043c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
-{"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
-{"dextr_rs.l", "t,7,6",        0x7c0005bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
-{"dextr_rs.w", "t,7,6",        0x7c0001bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
-{"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
-{"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
-{"dextrv.l", "t,7,s",  0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
-{"dextrv_r.l", "t,7,s",        0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
-{"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s,       0,              D64     },
-{"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s,       0,              D64     },
-{"dextrv_r.w", "t,7,s",        0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
-{"dextrv_s.h", "t,7,s",        0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
-{"dextrv.w", "t,7,s",  0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
-{"dextr.w", "t,7,6",   0x7c00003c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
-{"dinsv",   "t,s",     0x7c00000d, 0xfc00ffff, WR_t|RD_s,              0,              D64     },
-{"dmadd",   "7,s,t",   0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
-{"dmaddu",  "7,s,t",   0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
-{"dmsub",   "7,s,t",   0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
-{"dmsubu",  "7,s,t",   0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
-{"dmthlip", "s,7",     0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,    0,              D64     },
-{"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
-{"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D32     },
-{"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D32     },
-{"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
-{"dpau.h.obl", "7,s,t",        0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
-{"dpau.h.obr", "7,s,t",        0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
-{"dpau.h.qbl", "7,s,t",        0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
-{"dpau.h.qbr", "7,s,t",        0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
-{"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
-{"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D32     },
-{"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D32     },
-{"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
-{"dpsu.h.obl", "7,s,t",        0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
-{"dpsu.h.obr", "7,s,t",        0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
-{"dpsu.h.qbl", "7,s,t",        0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
-{"dpsu.h.qbr", "7,s,t",        0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
-{"dshilo",  "7,:",     0x7c0006bc, 0xfc07e7ff, MOD_a,                  0,              D64     },
-{"dshilov", "7,s",     0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s,             0,              D64     },
-{"extpdp",  "t,7,6",   0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,     0,              D32     },
-{"extpdpv", "t,7,s",   0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,             D32     },
-{"extp",    "t,7,6",   0x7c0000b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
-{"extpv",   "t,7,s",   0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
-{"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
-{"extr_r.w", "t,7,6",  0x7c000138, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
-{"extr_s.h", "t,7,6",  0x7c0003b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
-{"extrv_rs.w", "t,7,s",        0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
-{"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
-{"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
-{"extrv.w", "t,7,s",   0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
-{"extr.w",  "t,7,6",   0x7c000038, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
-{"insv",    "t,s",     0x7c00000c, 0xfc00ffff, WR_t|RD_s,              0,              D32     },
+{"absq_s.ph", "d,t",   0x7c000252, 0xffe007ff, WR_d|RD_t,              0,              0,      D32     },
+{"absq_s.pw", "d,t",   0x7c000456, 0xffe007ff, WR_d|RD_t,              0,              0,      D64     },
+{"absq_s.qh", "d,t",   0x7c000256, 0xffe007ff, WR_d|RD_t,              0,              0,      D64     },
+{"absq_s.w", "d,t",    0x7c000452, 0xffe007ff, WR_d|RD_t,              0,              0,      D32     },
+{"addq.ph", "d,s,t",   0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"addq.pw", "d,s,t",   0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"addq.qh", "d,s,t",   0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"addq_s.w", "d,s,t",  0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"addsc",   "d,s,t",   0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"addu.ob", "d,s,t",   0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"addu.qb", "d,s,t",   0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"addwc",   "d,s,t",   0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"bitrev",  "d,t",     0x7c0006d2, 0xffe007ff, WR_d|RD_t,              0,              0,      D32     },
+{"bposge32", "p",      0x041c0000, 0xffff0000, CBD,                    0,              0,      D32     },
+{"bposge64", "p",      0x041d0000, 0xffff0000, CBD,                    0,              0,      D64     },
+{"cmp.eq.ph", "s,t",   0x7c000211, 0xfc00ffff, RD_s|RD_t,              0,              0,      D32     },
+{"cmp.eq.pw", "s,t",   0x7c000415, 0xfc00ffff, RD_s|RD_t,              0,              0,      D64     },
+{"cmp.eq.qh", "s,t",   0x7c000215, 0xfc00ffff, RD_s|RD_t,              0,              0,      D64     },
+{"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              0,      D64     },
+{"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              0,      D32     },
+{"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              0,      D64     },
+{"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              0,      D32     },
+{"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              0,      D64     },
+{"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              0,      D32     },
+{"cmp.le.ph", "s,t",   0x7c000291, 0xfc00ffff, RD_s|RD_t,              0,              0,      D32     },
+{"cmp.le.pw", "s,t",   0x7c000495, 0xfc00ffff, RD_s|RD_t,              0,              0,      D64     },
+{"cmp.le.qh", "s,t",   0x7c000295, 0xfc00ffff, RD_s|RD_t,              0,              0,      D64     },
+{"cmp.lt.ph", "s,t",   0x7c000251, 0xfc00ffff, RD_s|RD_t,              0,              0,      D32     },
+{"cmp.lt.pw", "s,t",   0x7c000455, 0xfc00ffff, RD_s|RD_t,              0,              0,      D64     },
+{"cmp.lt.qh", "s,t",   0x7c000255, 0xfc00ffff, RD_s|RD_t,              0,              0,      D64     },
+{"cmpu.eq.ob", "s,t",  0x7c000015, 0xfc00ffff, RD_s|RD_t,              0,              0,      D64     },
+{"cmpu.eq.qb", "s,t",  0x7c000011, 0xfc00ffff, RD_s|RD_t,              0,              0,      D32     },
+{"cmpu.le.ob", "s,t",  0x7c000095, 0xfc00ffff, RD_s|RD_t,              0,              0,      D64     },
+{"cmpu.le.qb", "s,t",  0x7c000091, 0xfc00ffff, RD_s|RD_t,              0,              0,      D32     },
+{"cmpu.lt.ob", "s,t",  0x7c000055, 0xfc00ffff, RD_s|RD_t,              0,              0,      D64     },
+{"cmpu.lt.qb", "s,t",  0x7c000051, 0xfc00ffff, RD_s|RD_t,              0,              0,      D32     },
+{"dextpdp", "t,7,6",   0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,     0,              0,      D64     },
+{"dextpdpv", "t,7,s",  0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,             0,      D64     },
+{"dextp",   "t,7,6",   0x7c0000bc, 0xfc00e7ff, WR_t|RD_a,              0,              0,      D64     },
+{"dextpv",  "t,7,s",   0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              0,      D64     },
+{"dextr.l", "t,7,6",   0x7c00043c, 0xfc00e7ff, WR_t|RD_a,              0,              0,      D64     },
+{"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a,              0,              0,      D64     },
+{"dextr_rs.l", "t,7,6",        0x7c0005bc, 0xfc00e7ff, WR_t|RD_a,              0,              0,      D64     },
+{"dextr_rs.w", "t,7,6",        0x7c0001bc, 0xfc00e7ff, WR_t|RD_a,              0,              0,      D64     },
+{"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a,              0,              0,      D64     },
+{"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a,              0,              0,      D64     },
+{"dextrv.l", "t,7,s",  0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              0,      D64     },
+{"dextrv_r.l", "t,7,s",        0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              0,      D64     },
+{"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s,       0,              0,      D64     },
+{"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s,       0,              0,      D64     },
+{"dextrv_r.w", "t,7,s",        0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              0,      D64     },
+{"dextrv_s.h", "t,7,s",        0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              0,      D64     },
+{"dextrv.w", "t,7,s",  0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              0,      D64     },
+{"dextr.w", "t,7,6",   0x7c00003c, 0xfc00e7ff, WR_t|RD_a,              0,              0,      D64     },
+{"dinsv",   "t,s",     0x7c00000d, 0xfc00ffff, WR_t|RD_s,              0,              0,      D64     },
+{"dmadd",   "7,s,t",   0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D64     },
+{"dmaddu",  "7,s,t",   0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D64     },
+{"dmsub",   "7,s,t",   0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D64     },
+{"dmsubu",  "7,s,t",   0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D64     },
+{"dmthlip", "s,7",     0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,    0,              0,      D64     },
+{"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              0,      D64     },
+{"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              0,      D32     },
+{"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              0,      D32     },
+{"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              0,      D64     },
+{"dpau.h.obl", "7,s,t",        0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D64     },
+{"dpau.h.obr", "7,s,t",        0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D64     },
+{"dpau.h.qbl", "7,s,t",        0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D32     },
+{"dpau.h.qbr", "7,s,t",        0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D32     },
+{"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              0,      D64     },
+{"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              0,      D32     },
+{"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              0,      D32     },
+{"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              0,      D64     },
+{"dpsu.h.obl", "7,s,t",        0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D64     },
+{"dpsu.h.obr", "7,s,t",        0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D64     },
+{"dpsu.h.qbl", "7,s,t",        0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D32     },
+{"dpsu.h.qbr", "7,s,t",        0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D32     },
+{"dshilo",  "7,:",     0x7c0006bc, 0xfc07e7ff, MOD_a,                  0,              0,      D64     },
+{"dshilov", "7,s",     0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s,             0,              0,      D64     },
+{"extpdp",  "t,7,6",   0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,     0,              0,      D32     },
+{"extpdpv", "t,7,s",   0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,             0,      D32     },
+{"extp",    "t,7,6",   0x7c0000b8, 0xfc00e7ff, WR_t|RD_a,              0,              0,      D32     },
+{"extpv",   "t,7,s",   0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              0,      D32     },
+{"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_t|RD_a,              0,              0,      D32     },
+{"extr_r.w", "t,7,6",  0x7c000138, 0xfc00e7ff, WR_t|RD_a,              0,              0,      D32     },
+{"extr_s.h", "t,7,6",  0x7c0003b8, 0xfc00e7ff, WR_t|RD_a,              0,              0,      D32     },
+{"extrv_rs.w", "t,7,s",        0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              0,      D32     },
+{"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              0,      D32     },
+{"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              0,      D32     },
+{"extrv.w", "t,7,s",   0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              0,      D32     },
+{"extr.w",  "t,7,6",   0x7c000038, 0xfc00e7ff, WR_t|RD_a,              0,              0,      D32     },
+{"insv",    "t,s",     0x7c00000c, 0xfc00ffff, WR_t|RD_s,              0,              0,      D32     },
 /* lbux, ldx, lhx and lwx are the basic instruction section.  */
-{"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D32     },
-{"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D32     },
-{"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              D64     },
-{"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              D64     },
-{"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              D64     },
-{"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              D64     },
-{"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
-{"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
-{"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D32     },
-{"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D32     },
-{"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
-{"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
-{"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
-{"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
-{"modsub",  "d,s,t",   0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"mthlip",  "s,7",     0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,    0,              D32     },
-{"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,         D64     },
-{"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,         D64     },
-{"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D32     },
-{"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D32     },
-{"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,         D32     },
-{"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,         D32     },
-{"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,         D64     },
-{"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,         D64     },
-{"mulq_rs.ph", "d,s,t",        0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D32     },
-{"mulq_rs.qh", "d,s,t",        0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D64     },
-{"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              D64     },
-{"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              D32     },
-{"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              D64     },
-{"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"pick.ob", "d,s,t",   0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"pick.ph", "d,s,t",   0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"pick.pw", "d,s,t",   0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"pick.qb", "d,s,t",   0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"pick.qh", "d,s,t",   0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t,           0,              D64     },
-{"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t,            0,              D64     },
-{"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t,           0,              D64     },
-{"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t,            0,              D64     },
-{"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t,           0,              D64     },
-{"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t,           0,              D64     },
-{"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t,          0,              D32     },
-{"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t,           0,              D32     },
-{"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t,          0,              D32     },
-{"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t,           0,              D32     },
-{"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t,          0,              D64     },
-{"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t,           0,              D64     },
-{"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t,          0,              D64     },
-{"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t,           0,              D64     },
-{"preceq.w.phl", "d,t",        0x7c000312, 0xffe007ff, WR_d|RD_t,              0,              D32     },
-{"preceq.w.phr", "d,t",        0x7c000352, 0xffe007ff, WR_d|RD_t,              0,              D32     },
-{"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t,           0,              D32     },
-{"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t,            0,              D32     },
-{"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t,           0,              D32     },
-{"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t,            0,              D32     },
-{"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t,           0,              D64     },
-{"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t,            0,              D64     },
-{"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t,           0,              D64     },
-{"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t,            0,              D64     },
-{"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t,      0,              D64     },
-{"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D32     },
-{"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D64     },
-{"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t,      0,              D32     },
-{"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t,      0,              D64     },
-{"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D32     },
-{"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t,   0,              D64     },
-{"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t,   0,              D64     },
-{"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t,   0,              D32     },
-{"raddu.l.ob", "d,s",  0x7c000514, 0xfc1f07ff, WR_d|RD_s,              0,              D64     },
-{"raddu.w.qb", "d,s",  0x7c000510, 0xfc1f07ff, WR_d|RD_s,              0,              D32     },
-{"rddsp",   "d",       0x7fff04b8, 0xffff07ff, WR_d,                   0,              D32     },
-{"rddsp",   "d,'",     0x7c0004b8, 0xffc007ff, WR_d,                   0,              D32     },
-{"repl.ob", "d,5",     0x7c000096, 0xff0007ff, WR_d,                   0,              D64     },
-{"repl.ph", "d,@",     0x7c000292, 0xfc0007ff, WR_d,                   0,              D32     },
-{"repl.pw", "d,@",     0x7c000496, 0xfc0007ff, WR_d,                   0,              D64     },
-{"repl.qb", "d,5",     0x7c000092, 0xff0007ff, WR_d,                   0,              D32     },
-{"repl.qh", "d,@",     0x7c000296, 0xfc0007ff, WR_d,                   0,              D64     },
-{"replv.ob", "d,t",    0x7c0000d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
-{"replv.ph", "d,t",    0x7c0002d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
-{"replv.pw", "d,t",    0x7c0004d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
-{"replv.qb", "d,t",    0x7c0000d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
-{"replv.qh", "d,t",    0x7c0002d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
-{"shilo",   "7,0",     0x7c0006b8, 0xfc0fe7ff, MOD_a,                  0,              D32     },
-{"shilov",  "7,s",     0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s,             0,              D32     },
-{"shll.ob", "d,t,3",   0x7c000017, 0xff0007ff, WR_d|RD_t,              0,              D64     },
-{"shll.ph", "d,t,4",   0x7c000213, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
-{"shll.pw", "d,t,6",   0x7c000417, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
-{"shll.qb", "d,t,3",   0x7c000013, 0xff0007ff, WR_d|RD_t,              0,              D32     },
-{"shll.qh", "d,t,4",   0x7c000217, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
-{"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
-{"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
-{"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
-{"shll_s.w", "d,t,6",  0x7c000513, 0xfc0007ff, WR_d|RD_t,              0,              D32     },
-{"shllv.ob", "d,t,s",  0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"shllv.ph", "d,t,s",  0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"shllv.pw", "d,t,s",  0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"shllv.qb", "d,t,s",  0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"shllv.qh", "d,t,s",  0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"shllv_s.ph", "d,t,s",        0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"shllv_s.pw", "d,t,s",        0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"shllv_s.qh", "d,t,s",        0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"shra.ph", "d,t,4",   0x7c000253, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
-{"shra.pw", "d,t,6",   0x7c000457, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
-{"shra.qh", "d,t,4",   0x7c000257, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
-{"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
-{"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
-{"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
-{"shra_r.w", "d,t,6",  0x7c000553, 0xfc0007ff, WR_d|RD_t,              0,              D32     },
-{"shrav.ph", "d,t,s",  0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"shrav.pw", "d,t,s",  0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"shrav.qh", "d,t,s",  0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"shrav_r.ph", "d,t,s",        0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"shrav_r.pw", "d,t,s",        0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"shrav_r.qh", "d,t,s",        0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"shrl.ob", "d,t,3",   0x7c000057, 0xff0007ff, WR_d|RD_t,              0,              D64     },
-{"shrl.qb", "d,t,3",   0x7c000053, 0xff0007ff, WR_d|RD_t,              0,              D32     },
-{"shrlv.ob", "d,t,s",  0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"shrlv.qb", "d,t,s",  0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"subq.ph", "d,s,t",   0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"subq.pw", "d,s,t",   0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"subq.qh", "d,s,t",   0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"subq_s.w", "d,s,t",  0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"subu.ob", "d,s,t",   0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"subu.qb", "d,s,t",   0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
-{"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
-{"wrdsp",   "s",       0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA,          0,              D32     },
-{"wrdsp",   "s,8",     0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA,          0,              D32     },
+{"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              0,      D32     },
+{"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              0,      D32     },
+{"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              0,      D64     },
+{"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              0,      D64     },
+{"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              0,      D64     },
+{"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              0,      D64     },
+{"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              0,      D64     },
+{"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              0,      D64     },
+{"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              0,      D32     },
+{"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              0,      D32     },
+{"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              0,      D64     },
+{"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              0,      D64     },
+{"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              0,      D64     },
+{"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              0,      D64     },
+{"modsub",  "d,s,t",   0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"mthlip",  "s,7",     0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,    0,              0,      D32     },
+{"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,         0,      D64     },
+{"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,         0,      D64     },
+{"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          0,      D32     },
+{"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          0,      D32     },
+{"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,         0,      D32     },
+{"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,         0,      D32     },
+{"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,         0,      D64     },
+{"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,         0,      D64     },
+{"mulq_rs.ph", "d,s,t",        0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              0,      D32     },
+{"mulq_rs.qh", "d,s,t",        0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              0,      D64     },
+{"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              0,      D64     },
+{"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              0,      D32     },
+{"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              0,      D64     },
+{"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"pick.ob", "d,s,t",   0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"pick.ph", "d,s,t",   0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"pick.pw", "d,s,t",   0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"pick.qb", "d,s,t",   0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"pick.qh", "d,s,t",   0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t,           0,              0,      D64     },
+{"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t,            0,              0,      D64     },
+{"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t,           0,              0,      D64     },
+{"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t,            0,              0,      D64     },
+{"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t,           0,              0,      D64     },
+{"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t,           0,              0,      D64     },
+{"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t,          0,              0,      D32     },
+{"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t,           0,              0,      D32     },
+{"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t,          0,              0,      D32     },
+{"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t,           0,              0,      D32     },
+{"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t,          0,              0,      D64     },
+{"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t,           0,              0,      D64     },
+{"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t,          0,              0,      D64     },
+{"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t,           0,              0,      D64     },
+{"preceq.w.phl", "d,t",        0x7c000312, 0xffe007ff, WR_d|RD_t,              0,              0,      D32     },
+{"preceq.w.phr", "d,t",        0x7c000352, 0xffe007ff, WR_d|RD_t,              0,              0,      D32     },
+{"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t,           0,              0,      D32     },
+{"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t,            0,              0,      D32     },
+{"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t,           0,              0,      D32     },
+{"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t,            0,              0,      D32     },
+{"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t,           0,              0,      D64     },
+{"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t,            0,              0,      D64     },
+{"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t,           0,              0,      D64     },
+{"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t,            0,              0,      D64     },
+{"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t,      0,              0,      D64     },
+{"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              0,      D32     },
+{"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              0,      D64     },
+{"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t,      0,              0,      D32     },
+{"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t,      0,              0,      D64     },
+{"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              0,      D32     },
+{"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t,   0,              0,      D64     },
+{"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t,   0,              0,      D64     },
+{"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t,   0,              0,      D32     },
+{"raddu.l.ob", "d,s",  0x7c000514, 0xfc1f07ff, WR_d|RD_s,              0,              0,      D64     },
+{"raddu.w.qb", "d,s",  0x7c000510, 0xfc1f07ff, WR_d|RD_s,              0,              0,      D32     },
+{"rddsp",   "d",       0x7fff04b8, 0xffff07ff, WR_d,                   0,              0,      D32     },
+{"rddsp",   "d,'",     0x7c0004b8, 0xffc007ff, WR_d,                   0,              0,      D32     },
+{"repl.ob", "d,5",     0x7c000096, 0xff0007ff, WR_d,                   0,              0,      D64     },
+{"repl.ph", "d,@",     0x7c000292, 0xfc0007ff, WR_d,                   0,              0,      D32     },
+{"repl.pw", "d,@",     0x7c000496, 0xfc0007ff, WR_d,                   0,              0,      D64     },
+{"repl.qb", "d,5",     0x7c000092, 0xff0007ff, WR_d,                   0,              0,      D32     },
+{"repl.qh", "d,@",     0x7c000296, 0xfc0007ff, WR_d,                   0,              0,      D64     },
+{"replv.ob", "d,t",    0x7c0000d6, 0xffe007ff, WR_d|RD_t,              0,              0,      D64     },
+{"replv.ph", "d,t",    0x7c0002d2, 0xffe007ff, WR_d|RD_t,              0,              0,      D32     },
+{"replv.pw", "d,t",    0x7c0004d6, 0xffe007ff, WR_d|RD_t,              0,              0,      D64     },
+{"replv.qb", "d,t",    0x7c0000d2, 0xffe007ff, WR_d|RD_t,              0,              0,      D32     },
+{"replv.qh", "d,t",    0x7c0002d6, 0xffe007ff, WR_d|RD_t,              0,              0,      D64     },
+{"shilo",   "7,0",     0x7c0006b8, 0xfc0fe7ff, MOD_a,                  0,              0,      D32     },
+{"shilov",  "7,s",     0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s,             0,              0,      D32     },
+{"shll.ob", "d,t,3",   0x7c000017, 0xff0007ff, WR_d|RD_t,              0,              0,      D64     },
+{"shll.ph", "d,t,4",   0x7c000213, 0xfe0007ff, WR_d|RD_t,              0,              0,      D32     },
+{"shll.pw", "d,t,6",   0x7c000417, 0xfc0007ff, WR_d|RD_t,              0,              0,      D64     },
+{"shll.qb", "d,t,3",   0x7c000013, 0xff0007ff, WR_d|RD_t,              0,              0,      D32     },
+{"shll.qh", "d,t,4",   0x7c000217, 0xfe0007ff, WR_d|RD_t,              0,              0,      D64     },
+{"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t,              0,              0,      D32     },
+{"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t,              0,              0,      D64     },
+{"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t,              0,              0,      D64     },
+{"shll_s.w", "d,t,6",  0x7c000513, 0xfc0007ff, WR_d|RD_t,              0,              0,      D32     },
+{"shllv.ob", "d,t,s",  0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"shllv.ph", "d,t,s",  0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"shllv.pw", "d,t,s",  0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"shllv.qb", "d,t,s",  0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"shllv.qh", "d,t,s",  0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"shllv_s.ph", "d,t,s",        0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"shllv_s.pw", "d,t,s",        0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"shllv_s.qh", "d,t,s",        0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"shra.ph", "d,t,4",   0x7c000253, 0xfe0007ff, WR_d|RD_t,              0,              0,      D32     },
+{"shra.pw", "d,t,6",   0x7c000457, 0xfc0007ff, WR_d|RD_t,              0,              0,      D64     },
+{"shra.qh", "d,t,4",   0x7c000257, 0xfe0007ff, WR_d|RD_t,              0,              0,      D64     },
+{"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t,              0,              0,      D32     },
+{"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t,              0,              0,      D64     },
+{"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t,              0,              0,      D64     },
+{"shra_r.w", "d,t,6",  0x7c000553, 0xfc0007ff, WR_d|RD_t,              0,              0,      D32     },
+{"shrav.ph", "d,t,s",  0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"shrav.pw", "d,t,s",  0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"shrav.qh", "d,t,s",  0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"shrav_r.ph", "d,t,s",        0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"shrav_r.pw", "d,t,s",        0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"shrav_r.qh", "d,t,s",        0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"shrl.ob", "d,t,3",   0x7c000057, 0xff0007ff, WR_d|RD_t,              0,              0,      D64     },
+{"shrl.qb", "d,t,3",   0x7c000053, 0xff0007ff, WR_d|RD_t,              0,              0,      D32     },
+{"shrlv.ob", "d,t,s",  0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"shrlv.qb", "d,t,s",  0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"subq.ph", "d,s,t",   0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"subq.pw", "d,s,t",   0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"subq.qh", "d,s,t",   0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"subq_s.w", "d,s,t",  0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"subu.ob", "d,s,t",   0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"subu.qb", "d,s,t",   0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D64     },
+{"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D32     },
+{"wrdsp",   "s",       0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA,          0,              0,      D32     },
+{"wrdsp",   "s,8",     0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA,          0,              0,      D32     },
 /* MIPS DSP ASE Rev2 */
-{"absq_s.qb", "d,t",   0x7c000052, 0xffe007ff, WR_d|RD_t,              0,              D33     },
-{"addu.ph", "d,s,t",   0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"adduh.qb", "d,s,t",  0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"adduh_r.qb", "d,s,t",        0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"append",  "t,s,h",   0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33     },
-{"balign",  "t,s,I",   0,    (int) M_BALIGN,   INSN_MACRO,             0,              D33     },
-{"balign",  "t,s,2",   0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s,         0,              D33     },
-{"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33    },
-{"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33    },
-{"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33    },
-{"dpa.w.ph", "7,s,t",  0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
-{"dps.w.ph", "7,s,t",  0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
-{"mul.ph",  "d,s,t",   0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
-{"mul_s.ph", "d,s,t",  0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
-{"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
-{"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
-{"mulq_s.w", "d,s,t",  0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
-{"mulsa.w.ph", "7,s,t",        0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
-{"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D33    },
-{"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s,     0,              D33    },
-{"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s,   0,              D33    },
-{"prepend", "t,s,h",   0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33     },
-{"shra.qb", "d,t,3",   0x7c000113, 0xff0007ff, WR_d|RD_t,              0,              D33     },
-{"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t,              0,              D33     },
-{"shrav.qb", "d,t,s",  0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"shrav_r.qb", "d,t,s",        0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"shrl.ph", "d,t,4",   0x7c000653, 0xfe0007ff, WR_d|RD_t,              0,              D33     },
-{"shrlv.ph", "d,t,s",  0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"subu.ph", "d,s,t",   0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"subuh.qb", "d,s,t",  0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"subuh_r.qb", "d,s,t",        0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"addqh.ph", "d,s,t",  0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"addqh_r.ph", "d,s,t",        0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"addqh.w", "d,s,t",   0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"subqh.ph", "d,s,t",  0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"subqh_r.ph", "d,s,t",        0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"subqh.w", "d,s,t",   0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
-{"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
-{"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
-{"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D33     },
-{"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              D33     },
-{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D33     },
-{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              D33     },
+{"absq_s.qb", "d,t",   0x7c000052, 0xffe007ff, WR_d|RD_t,              0,              0,      D33     },
+{"addu.ph", "d,s,t",   0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"adduh.qb", "d,s,t",  0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"adduh_r.qb", "d,s,t",        0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"append",  "t,s,h",   0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              0,      D33     },
+{"balign",  "t,s,I",   0,    (int) M_BALIGN,   INSN_MACRO,             0,              0,      D33     },
+{"balign",  "t,s,2",   0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s,         0,              0,      D33     },
+{"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              0,     D33     },
+{"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              0,     D33     },
+{"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              0,     D33     },
+{"dpa.w.ph", "7,s,t",  0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D33     },
+{"dps.w.ph", "7,s,t",  0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D33     },
+{"mul.ph",  "d,s,t",   0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              0,      D33     },
+{"mul_s.ph", "d,s,t",  0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              0,      D33     },
+{"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              0,      D33     },
+{"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              0,      D33     },
+{"mulq_s.w", "d,s,t",  0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              0,      D33     },
+{"mulsa.w.ph", "7,s,t",        0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D33     },
+{"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              0,     D33     },
+{"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s,     0,              0,     D33     },
+{"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s,   0,              0,     D33     },
+{"prepend", "t,s,h",   0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              0,      D33     },
+{"shra.qb", "d,t,3",   0x7c000113, 0xff0007ff, WR_d|RD_t,              0,              0,      D33     },
+{"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t,              0,              0,      D33     },
+{"shrav.qb", "d,t,s",  0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"shrav_r.qb", "d,t,s",        0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"shrl.ph", "d,t,4",   0x7c000653, 0xfe0007ff, WR_d|RD_t,              0,              0,      D33     },
+{"shrlv.ph", "d,t,s",  0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"subu.ph", "d,s,t",   0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"subuh.qb", "d,s,t",  0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"subuh_r.qb", "d,s,t",        0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"addqh.ph", "d,s,t",  0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"addqh_r.ph", "d,s,t",        0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"addqh.w", "d,s,t",   0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"subqh.ph", "d,s,t",  0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"subqh_r.ph", "d,s,t",        0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"subqh.w", "d,s,t",   0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              0,      D33     },
+{"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D33     },
+{"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              0,      D33     },
+{"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              0,      D33     },
+{"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              0,      D33     },
+{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              0,      D33     },
+{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              0,      D33     },
 /* Move bc0* after mftr and mttr to avoid opcode collision.  */
-{"bc0f",    "p",       0x41000000, 0xffff0000, CBD|RD_CC,              0,              I1,             IOCT|IOCTP|IOCT2        },
-{"bc0fl",   "p",       0x41020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3,          IOCT|IOCTP|IOCT2        },
-{"bc0t",    "p",       0x41010000, 0xffff0000, CBD|RD_CC,              0,              I1,             IOCT|IOCTP|IOCT2        },
-{"bc0tl",   "p",       0x41030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3,          IOCT|IOCTP|IOCT2        },
+{"bc0f",    "p",       0x41000000, 0xffff0000, CBD|RD_CC,              0,              I1,     0,      IOCT|IOCTP|IOCT2        },
+{"bc0fl",   "p",       0x41020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3,  0,      IOCT|IOCTP|IOCT2        },
+{"bc0t",    "p",       0x41010000, 0xffff0000, CBD|RD_CC,              0,              I1,     0,      IOCT|IOCTP|IOCT2        },
+{"bc0tl",   "p",       0x41030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3,  0,      IOCT|IOCTP|IOCT2        },
 /* ST Microelectronics Loongson-2E and -2F.  */
 {"mult.g",     "d,s,t",        0x7c000018,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
 {"mult.g",     "d,s,t",        0x70000010,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
@@ -2300,14 +2300,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the
    disassembler recognizes more specific versions first.  */
-{"c0",      "C",       0x42000000, 0xfe000000, CP,                     0,              I1,             IOCT|IOCTP|IOCT2        },
+{"c0",      "C",       0x42000000, 0xfe000000, CP,                     0,              I1,     0,      IOCT|IOCTP|IOCT2        },
 {"c1",      "C",       0x46000000, 0xfe000000, FP_S,                   0,              I1      },
-{"c2",      "C",       0x4a000000, 0xfe000000, CP,                     0,              I1,             IOCT|IOCTP|IOCT2        },
-{"c3",      "C",       0x4e000000, 0xfe000000, CP,                     0,              I1,             IOCT|IOCTP|IOCT2        },
-{"cop0",     "C",      0,    (int) M_COP0,     INSN_MACRO,             0,              I1,             IOCT|IOCTP|IOCT2        },
+{"c2",      "C",       0x4a000000, 0xfe000000, CP,                     0,              I1,     0,      IOCT|IOCTP|IOCT2        },
+{"c3",      "C",       0x4e000000, 0xfe000000, CP,                     0,              I1,     0,      IOCT|IOCTP|IOCT2        },
+{"cop0",     "C",      0,    (int) M_COP0,     INSN_MACRO,             0,              I1,     0,      IOCT|IOCTP|IOCT2        },
 {"cop1",     "C",      0,    (int) M_COP1,     INSN_MACRO,             INSN2_M_FP_S,   I1      },
-{"cop2",     "C",      0,    (int) M_COP2,     INSN_MACRO,             0,              I1,             IOCT|IOCTP|IOCT2        },
-{"cop3",     "C",      0,    (int) M_COP3,     INSN_MACRO,             0,              I1,             IOCT|IOCTP|IOCT2        },
+{"cop2",     "C",      0,    (int) M_COP2,     INSN_MACRO,             0,              I1,     0,      IOCT|IOCTP|IOCT2        },
+{"cop3",     "C",      0,    (int) M_COP3,     INSN_MACRO,             0,              I1,     0,      IOCT|IOCTP|IOCT2        },
 /* RFE conflicts with the new Virt spec instruction tlbgp. */
 {"rfe",     "",                0x42000010, 0xffffffff, 0,                      0,              I1|T3   },
 };