None of the supported SH4 family SoCs features a second DMAC module. As
this definition negatively impacts DMA channel calculation for the above
targets, remove it from the code.
Signed-off-by: Artur Rojek <contact@artur-rojek.eu>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Link: https://lore.kernel.org/r/20230527164452.64797-3-contact@artur-rojek.eu
Signed-off-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
#define DMAE0_IRQ evt2irq(0x6c0)
#define SH_DMAC_BASE0 0xffa00000
-#define SH_DMAC_BASE1 0xffa00070
#endif /* __ASM_CPU_SH4_DMA_H */