[RegisterCoalescer] fix dst subreg replacement during remat copy trick

Instructions might use definition register as its "undef" operand. It
happens on architectures with predicated executon:

```
%0:subreg = instruction op_1, ..., op_N, undef %0:subreg, op_N+2, ...
```

RegisterCoalescer should take into account all remat instruction
operands during destination subregister fixup.

```
; remat result before fix:
%1 = instruction op_1, ..., op_N, undef %1:subreg, op_N+2, ...

; remat result after fix (correct):
%1 = instruction op_1, ..., op_N, undef %1, op_N+2, ...
```

Differential Revision: https://reviews.llvm.org/D125657

diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index f8c6a39..8865bcf 100644 (file)
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -1376,8 +1376,18 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
         TRI->getCommonSubClass(DefRC, DstRC);
       if (CommonRC != nullptr) {
         NewRC = CommonRC;
+
+        // Instruction might contain "undef %0:subreg" as use operand:
+        //   %0:subreg = instr op_1, ..., op_N, undef %0:subreg, op_N+2, ...
+        //
+        // Need to check all operands.
+        for (MachineOperand &MO : NewMI.operands()) {
+          if (MO.isReg() && MO.getReg() == DstReg && MO.getSubReg() == DstIdx) {
+            MO.setSubReg(0);
+          }
+        }
+
         DstIdx = 0;
-        DefMO.setSubReg(0);
         DefMO.setIsUndef(false); // Only subregs can have def+undef.
       }
     }