powerpc/32: Use SPRN_SPRG_SCRATCH2 in exception prologs

Use SPRN_SPRG_SCRATCH2 as a third scratch register in
exception prologs in order to simplify them and avoid
data going back and forth from/to CR.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/6f5c8a7faa8cc54acb89c55c20aa579a2f30a4e9.1606285014.git.christophe.leroy@csgroup.eu

diff --git a/arch/powerpc/kernel/head_32.h b/arch/powerpc/kernel/head_32.h
index 30f0b16..541664d 100644 (file)
--- a/arch/powerpc/kernel/head_32.h
+++ b/arch/powerpc/kernel/head_32.h
@@ -40,7 +40,7 @@
 
 .macro EXCEPTION_PROLOG_1 for_rtas=0
 #ifdef CONFIG_VMAP_STACK
-       mr      r11, r1
+       mtspr   SPRN_SPRG_SCRATCH2,r1
        subi    r1, r1, INT_FRAME_SIZE          /* use r1 if kernel */
        beq     1f
        mfspr   r1,SPRN_SPRG_THREAD
@@ -61,15 +61,10 @@
 
 .macro EXCEPTION_PROLOG_2 handle_dar_dsisr=0
 #ifdef CONFIG_VMAP_STACK
-       mtcr    r10
-       li      r10, MSR_KERNEL & ~(MSR_IR | MSR_RI) /* can take DTLB miss */
-       mtmsr   r10
+       li      r11, MSR_KERNEL & ~(MSR_IR | MSR_RI) /* can take DTLB miss */
+       mtmsr   r11
        isync
-#else
-       stw     r10,_CCR(r11)           /* save registers */
-#endif
-       mfspr   r10, SPRN_SPRG_SCRATCH0
-#ifdef CONFIG_VMAP_STACK
+       mfspr   r11, SPRN_SPRG_SCRATCH2
        stw     r11,GPR1(r1)
        stw     r11,0(r1)
        mr      r11, r1
@@ -78,14 +73,12 @@
        stw     r1,0(r11)
        tovirt(r1, r11)         /* set new kernel sp */
 #endif
+       stw     r10,_CCR(r11)           /* save registers */
        stw     r12,GPR12(r11)
        stw     r9,GPR9(r11)
-       stw     r10,GPR10(r11)
-#ifdef CONFIG_VMAP_STACK
-       mfcr    r10
-       stw     r10, _CCR(r11)
-#endif
+       mfspr   r10,SPRN_SPRG_SCRATCH0
        mfspr   r12,SPRN_SPRG_SCRATCH1
+       stw     r10,GPR10(r11)
        stw     r12,GPR11(r11)
        mflr    r10
        stw     r10,_LINK(r11)
@@ -99,7 +92,6 @@
        stw     r10, _DSISR(r11)
        .endif
        lwz     r9, SRR1(r12)
-       andi.   r10, r9, MSR_PR
        lwz     r12, SRR0(r12)
 #else
        mfspr   r12,SPRN_SRR0