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ARM: dts: aspeed: rainier: Add eMMC clock phase compensation
authorAndrew Jeffery <andrew@aj.id.au>
Tue, 8 Dec 2020 01:26:15 +0000 (11:56 +1030)
committerJoel Stanley <joel@jms.id.au>
Tue, 9 Feb 2021 11:57:19 +0000 (22:27 +1030)
Determined by scope measurements at speed.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20201208012615.2717412-7-andrew@aj.id.au
Signed-off-by: Joel Stanley <joel@jms.id.au>
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts patch | blob | history

diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
index a4b77ae..72de21f 100644 (file)
--- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
@@ -195,6 +195,7 @@
 
 &emmc {
        status = "okay";
+       clk-phase-mmc-hs200 = <180>, <180>;
 };
 
 &fsim0 {
Domain: System / Kernel;