;; multiple instructions, patterns which emit 0 instructions, and patterns
;; which emit instruction that can go in any slot (e.g. nop).
-(define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop_b,nop_f,nop_i,nop_m,nop_x,lfetch"
- (const_string "unknown"))
+(define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,
+ fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,
+ chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,
+ syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop_b,nop_f,
+ nop_i,nop_m,nop_x,lfetch"
+ (const_string "unknown"))
;; chk_s has an I and an M form; use type A for convenience.
(define_attr "type" "unknown,A,I,M,F,B,L,X,S"
[(set (match_operand:QI 0 "general_operand" "")
(match_operand:QI 1 "general_operand" ""))]
""
- "
{
if (! reload_in_progress && ! reload_completed
&& ! ia64_move_ok (operands[0], operands[1]))
operands[1] = force_reg (QImode, operands[1]);
-}")
+})
(define_insn "*movqi_internal"
[(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
[(set (match_operand:HI 0 "general_operand" "")
(match_operand:HI 1 "general_operand" ""))]
""
- "
{
if (! reload_in_progress && ! reload_completed
&& ! ia64_move_ok (operands[0], operands[1]))
operands[1] = force_reg (HImode, operands[1]);
-}")
+})
(define_insn "*movhi_internal"
[(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
[(set (match_operand:SI 0 "general_operand" "")
(match_operand:SI 1 "general_operand" ""))]
""
- "
{
if (! reload_in_progress && ! reload_completed
&& ! ia64_move_ok (operands[0], operands[1]))
operands[1] = force_reg (SImode, operands[1]);
-}")
+})
(define_insn "*movsi_internal"
[(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
mov %0 = %1
mov %0 = %1
mov %0 = %r1"
-;; frar_m, toar_m ??? why not frar_i and toar_i
+ ;; frar_m, toar_m ??? why not frar_i and toar_i
[(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")])
(define_expand "movdi"
[(set (match_operand:DI 0 "general_operand" "")
(match_operand:DI 1 "general_operand" ""))]
""
- "
{
if (! reload_in_progress && ! reload_completed
&& ! ia64_move_ok (operands[0], operands[1]))
if (rtx_equal_function_value_matters
&& ! (GET_CODE (operands[1]) == SYMBOL_REF
&& SYMBOL_REF_FLAG (operands[1])))
- emit_insn (gen_movdi_symbolic (operands[0], operands[1], gen_reg_rtx (DImode)));
+ emit_insn (gen_movdi_symbolic (operands[0], operands[1],
+ gen_reg_rtx (DImode)));
else
ia64_expand_load_address (operands[0], operands[1], NULL_RTX);
DONE;
}
-}")
+})
;; This is used during early compilation to delay the decision on
;; how to refer to a variable as long as possible. This is especially
"* abort ();"
""
[(const_int 0)]
- "ia64_expand_load_address (operands[0], operands[1], operands[2]); DONE;")
+ { ia64_expand_load_address (operands[0], operands[1], operands[2]); DONE; })
(define_insn "*movdi_internal"
[(set (match_operand:DI 0 "destination_operand"
(match_operand:DI 1 "move_operand"
"rO,J,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
"ia64_move_ok (operands[0], operands[1])"
- "*
{
static const char * const alt[] = {
- \"%,mov %0 = %r1\",
- \"%,addl %0 = %1, r0\",
- \"%,movl %0 = %1\",
- \"%,ld8%O1 %0 = %1%P1\",
- \"%,st8%Q0 %0 = %r1%P0\",
- \"%,getf.sig %0 = %1\",
- \"%,setf.sig %0 = %r1\",
- \"%,mov %0 = %1\",
- \"%,ldf8 %0 = %1%P1\",
- \"%,stf8 %0 = %1%P0\",
- \"%,mov %0 = %1\",
- \"%,mov %0 = %r1\",
- \"%,mov %0 = %1\",
- \"%,mov %0 = %1\",
- \"%,mov %0 = %1\",
- \"%,mov %0 = %1\",
- \"mov %0 = pr\",
- \"mov pr = %1, -1\"
+ "%,mov %0 = %r1",
+ "%,addl %0 = %1, r0",
+ "%,movl %0 = %1",
+ "%,ld8%O1 %0 = %1%P1",
+ "%,st8%Q0 %0 = %r1%P0",
+ "%,getf.sig %0 = %1",
+ "%,setf.sig %0 = %r1",
+ "%,mov %0 = %1",
+ "%,ldf8 %0 = %1%P1",
+ "%,stf8 %0 = %1%P0",
+ "%,mov %0 = %1",
+ "%,mov %0 = %r1",
+ "%,mov %0 = %1",
+ "%,mov %0 = %1",
+ "%,mov %0 = %1",
+ "%,mov %0 = %1",
+ "mov %0 = pr",
+ "mov pr = %1, -1"
};
if (which_alternative == 2 && ! TARGET_NO_PIC
abort ();
return alt[which_alternative];
-}"
+}
[(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
(define_split
(match_operand:DI 1 "symbolic_operand" ""))]
"reload_completed && ! TARGET_NO_PIC"
[(const_int 0)]
- "
{
ia64_expand_load_address (operands[0], operands[1], NULL_RTX);
DONE;
-}")
+})
(define_expand "load_fptr"
[(set (match_dup 2)
(plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" "")))
(set (match_operand:DI 0 "register_operand" "") (match_dup 3))]
""
- "
{
operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
operands[3] = gen_rtx_MEM (DImode, operands[2]);
RTX_UNCHANGING_P (operands[3]) = 1;
-}")
+})
(define_insn "*load_fptr_internal1"
[(set (match_operand:DI 0 "register_operand" "=r")
(set (match_operand:DI 0 "register_operand" "")
(plus:DI (match_dup 3) (match_dup 2)))]
""
- "
{
operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
operands[3] = pic_offset_table_rtx;
-}")
+})
(define_expand "load_symptr"
[(set (match_operand:DI 2 "register_operand" "")
(plus:DI (match_dup 4) (match_operand:DI 1 "got_symbolic_operand" "")))
(set (match_operand:DI 0 "register_operand" "") (match_dup 3))]
""
- "
{
operands[3] = gen_rtx_MEM (DImode, operands[2]);
operands[4] = pic_offset_table_rtx;
RTX_UNCHANGING_P (operands[3]) = 1;
-}")
+})
(define_insn "*load_symptr_internal1"
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:TI 1 "general_operand" ""))
(clobber (match_scratch:DI 2 ""))])]
""
- "
{
if (! reload_in_progress && ! reload_completed
&& ! ia64_move_ok (operands[0], operands[1]))
operands[1] = force_reg (TImode, operands[1]);
-}")
+})
(define_insn_and_split "*movti_internal"
[(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
"#"
"reload_completed"
[(const_int 0)]
- "
{
rtx adj1, adj2, in[2], out[2], insn;
int first;
XEXP (XEXP (out[!first], 0), 0),
REG_NOTES (insn));
DONE;
-}"
+}
[(set_attr "itanium_class" "unknown")
(set_attr "predicable" "no")])
"#"
"reload_completed"
[(const_int 0)]
- "
{
rtx in[2], out[2];
int first;
emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first]));
emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first]));
DONE;
-}"
+}
[(set_attr "itanium_class" "unknown")
(set_attr "predicable" "no")])
(match_operand:TI 1 "" "m"))
(clobber (match_operand:TI 2 "register_operand" "=&r"))])]
""
- "
{
unsigned int s_regno = REGNO (operands[2]);
if (s_regno == REGNO (operands[0]))
s_regno += 1;
operands[2] = gen_rtx_REG (DImode, s_regno);
-}")
+})
(define_expand "reload_outti"
[(parallel [(set (match_operand:TI 0 "" "=m")
(match_operand:TI 1 "register_operand" "r"))
(clobber (match_operand:TI 2 "register_operand" "=&r"))])]
""
- "
{
unsigned int s_regno = REGNO (operands[2]);
if (s_regno == REGNO (operands[1]))
s_regno += 1;
operands[2] = gen_rtx_REG (DImode, s_regno);
-}")
+})
;; Floating Point Moves
;;
[(set (match_operand:SF 0 "general_operand" "")
(match_operand:SF 1 "general_operand" ""))]
""
- "
{
if (! reload_in_progress && ! reload_completed
&& ! ia64_move_ok (operands[0], operands[1]))
operands[1] = force_reg (SFmode, operands[1]);
-}")
+})
(define_insn "*movsf_internal"
[(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
(match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
"ia64_move_ok (operands[0], operands[1])"
"@
- mov %0 = %F1
- ldfs %0 = %1%P1
- stfs %0 = %F1%P0
- getf.s %0 = %F1
- setf.s %0 = %1
- mov %0 = %1
- ld4%O1 %0 = %1%P1
- st4%Q0 %0 = %1%P0"
+ mov %0 = %F1
+ ldfs %0 = %1%P1
+ stfs %0 = %F1%P0
+ getf.s %0 = %F1
+ setf.s %0 = %1
+ mov %0 = %1
+ ld4%O1 %0 = %1%P1
+ st4%Q0 %0 = %1%P0"
[(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
(define_expand "movdf"
[(set (match_operand:DF 0 "general_operand" "")
(match_operand:DF 1 "general_operand" ""))]
""
- "
{
if (! reload_in_progress && ! reload_completed
&& ! ia64_move_ok (operands[0], operands[1]))
operands[1] = force_reg (DFmode, operands[1]);
-}")
+})
(define_insn "*movdf_internal"
[(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
(match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
"ia64_move_ok (operands[0], operands[1])"
"@
- mov %0 = %F1
- ldfd %0 = %1%P1
- stfd %0 = %F1%P0
- getf.d %0 = %F1
- setf.d %0 = %1
- mov %0 = %1
- ld8%O1 %0 = %1%P1
- st8%Q0 %0 = %1%P0"
+ mov %0 = %F1
+ ldfd %0 = %1%P1
+ stfd %0 = %F1%P0
+ getf.d %0 = %F1
+ setf.d %0 = %1
+ mov %0 = %1
+ ld8%O1 %0 = %1%P1
+ st8%Q0 %0 = %1%P0"
[(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
;; With no offsettable memory references, we've got to have a scratch
[(set (match_operand:TF 0 "general_operand" "")
(match_operand:TF 1 "general_operand" ""))]
"INTEL_EXTENDED_IEEE_FORMAT"
- "
{
/* We must support TFmode loads into general registers for stdarg/vararg
and unprototyped calls. We split them into DImode loads for convenience.
if (! ia64_move_ok (operands[0], operands[1]))
operands[1] = force_reg (TFmode, operands[1]);
}
-}")
+})
;; ??? There's no easy way to mind volatile acquire/release semantics.
(match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))]
"INTEL_EXTENDED_IEEE_FORMAT && ia64_move_ok (operands[0], operands[1])"
"@
- mov %0 = %F1
- ldfe %0 = %1%P1
- stfe %0 = %F1%P0"
+ mov %0 = %F1
+ ldfe %0 = %1%P1
+ stfe %0 = %F1%P0"
[(set_attr "itanium_class" "fmisc,fld,stf")])
\f
;; ::::::::::::::::::::
(match_operand:DI 2 "const_int_operand" ""))
(match_operand:DI 3 "nonmemory_operand" ""))]
""
- "
{
int width = INTVAL (operands[1]);
int shift = INTVAL (operands[2]);
operands[2] = GEN_INT (shift);
#endif
}
-}")
+})
(define_insn "*insv_internal"
[(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
(match_operand:DI 3 "const_int_operand" "n")))]
"CONST_OK_FOR_M (INTVAL (operands[2]))
&& ia64_depz_field_mask (operands[3], operands[2]) > 0"
- "*
{
operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2]));
- return \"%,dep.z %0 = %1, %2, %3\";
-}"
+ return "%,dep.z %0 = %1, %2, %3";
+}
[(set_attr "itanium_class" "ishf")])
(define_insn "shift_mix4left"
(match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
""
"@
- add %0 = %1, %2
- adds %0 = %2, %1
- addl %0 = %2, %1"
+ add %0 = %1, %2
+ adds %0 = %2, %1
+ addl %0 = %2, %1"
[(set_attr "itanium_class" "ialu")])
(define_insn "*addsi3_plus1"
(neg:SI (match_dup 1))
(match_dup 1)))]
""
- "
-{
- operands[2] = gen_reg_rtx (BImode);
-}")
+ { operands[2] = gen_reg_rtx (BImode); })
(define_expand "sminsi3"
[(set (match_dup 3)
(if_then_else:SI (ne (match_dup 3) (const_int 0))
(match_dup 2) (match_dup 1)))]
""
- "
-{
- operands[3] = gen_reg_rtx (BImode);
-}")
+ { operands[3] = gen_reg_rtx (BImode); })
(define_expand "smaxsi3"
[(set (match_dup 3)
(if_then_else:SI (ne (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))]
""
- "
-{
- operands[3] = gen_reg_rtx (BImode);
-}")
+ { operands[3] = gen_reg_rtx (BImode); })
(define_expand "uminsi3"
[(set (match_dup 3)
(if_then_else:SI (ne (match_dup 3) (const_int 0))
(match_dup 2) (match_dup 1)))]
""
- "
-{
- operands[3] = gen_reg_rtx (BImode);
-}")
+ { operands[3] = gen_reg_rtx (BImode); })
(define_expand "umaxsi3"
[(set (match_dup 3)
(if_then_else:SI (ne (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))]
""
- "
-{
- operands[3] = gen_reg_rtx (BImode);
-}")
+ { operands[3] = gen_reg_rtx (BImode); })
(define_expand "divsi3"
[(set (match_operand:SI 0 "register_operand" "")
(div:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
- "
{
rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
emit_insn (gen_fix_trunctfdi2_alts (op0_di, op0_tf, const1_rtx));
emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
DONE;
-}")
+})
(define_expand "modsi3"
[(set (match_operand:SI 0 "register_operand" "")
(mod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
- "
{
rtx op2_neg, op1_di, div;
emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
gen_lowpart (SImode, op1_di)));
DONE;
-}")
+})
(define_expand "udivsi3"
[(set (match_operand:SI 0 "register_operand" "")
(udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
- "
{
rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
emit_insn (gen_fixuns_trunctfdi2_alts (op0_di, op0_tf, const1_rtx));
emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
DONE;
-}")
+})
(define_expand "umodsi3"
[(set (match_operand:SI 0 "register_operand" "")
(umod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
- "
{
rtx op2_neg, op1_di, div;
emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
gen_lowpart (SImode, op1_di)));
DONE;
-}")
+})
(define_insn_and_split "divsi3_internal"
[(set (match_operand:TF 0 "fr_register_operand" "=&f")
(match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
""
"@
- add %0 = %1, %2
- adds %0 = %2, %1
- addl %0 = %2, %1"
+ add %0 = %1, %2
+ adds %0 = %2, %1
+ addl %0 = %2, %1"
[(set_attr "itanium_class" "ialu")])
(define_insn "*adddi3_plus1"
(neg:DI (match_dup 1))
(match_dup 1)))]
""
- "
-{
- operands[2] = gen_reg_rtx (BImode);
-}")
+ { operands[2] = gen_reg_rtx (BImode); })
(define_expand "smindi3"
[(set (match_dup 3)
(if_then_else:DI (ne (match_dup 3) (const_int 0))
(match_dup 2) (match_dup 1)))]
""
- "
-{
- operands[3] = gen_reg_rtx (BImode);
-}")
+ { operands[3] = gen_reg_rtx (BImode); })
(define_expand "smaxdi3"
[(set (match_dup 3)
(if_then_else:DI (ne (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))]
""
- "
-{
- operands[3] = gen_reg_rtx (BImode);
-}")
+ { operands[3] = gen_reg_rtx (BImode); })
(define_expand "umindi3"
[(set (match_dup 3)
(if_then_else:DI (ne (match_dup 3) (const_int 0))
(match_dup 2) (match_dup 1)))]
""
- "
-{
- operands[3] = gen_reg_rtx (BImode);
-}")
+ { operands[3] = gen_reg_rtx (BImode); })
(define_expand "umaxdi3"
[(set (match_dup 3)
(if_then_else:DI (ne (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))]
""
- "
-{
- operands[3] = gen_reg_rtx (BImode);
-}")
+ { operands[3] = gen_reg_rtx (BImode); })
(define_expand "ffsdi2"
[(set (match_dup 6)
(if_then_else:DI (ne (match_dup 6) (const_int 0))
(match_dup 5) (match_dup 4)))]
""
- "
{
operands[2] = gen_reg_rtx (DImode);
operands[3] = gen_reg_rtx (DImode);
operands[4] = gen_reg_rtx (DImode);
operands[5] = gen_reg_rtx (DImode);
operands[6] = gen_reg_rtx (BImode);
-}")
+})
(define_insn "*popcnt"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(div:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
- "
{
rtx op1_tf, op2_tf, op0_tf;
emit_insn (gen_fix_trunctfdi2_alts (operands[0], op0_tf, const1_rtx));
DONE;
-}")
+})
(define_expand "moddi3"
[(set (match_operand:DI 0 "register_operand" "")
(mod:SI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
- "
{
rtx op2_neg, div;
emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
DONE;
-}")
+})
(define_expand "udivdi3"
[(set (match_operand:DI 0 "register_operand" "")
(udiv:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
- "
{
rtx op1_tf, op2_tf, op0_tf;
emit_insn (gen_fixuns_trunctfdi2_alts (operands[0], op0_tf, const1_rtx));
DONE;
-}")
+})
(define_expand "umoddi3"
[(set (match_operand:DI 0 "register_operand" "")
(umod:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
- "
{
rtx op2_neg, div;
emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
DONE;
-}")
+})
(define_insn_and_split "divdi3_internal_lat"
[(set (match_operand:TF 0 "fr_register_operand" "=&f")
(div:SF (match_operand:SF 1 "fr_register_operand" "")
(match_operand:SF 2 "fr_register_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
- "
{
rtx insn;
if (TARGET_INLINE_DIV_LAT)
insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]);
emit_insn (insn);
DONE;
-}")
+})
(define_insn_and_split "divsf3_internal_lat"
[(set (match_operand:SF 0 "fr_register_operand" "=&f")
(set (match_dup 0)
(float_truncate:SF (match_dup 6))))
]
- "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
- operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
- operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
- operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0]));
- operands[10] = CONST1_RTX (TFmode);"
+{
+ operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
+ operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
+ operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
+ operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0]));
+ operands[10] = CONST1_RTX (TFmode);
+}
[(set_attr "predicable" "no")])
(define_insn_and_split "divsf3_internal_thr"
(plus:TF (mult:TF (match_dup 4) (match_dup 6))
(match_dup 3)))))
]
- "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
- operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
- operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
- operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3]));
- operands[10] = CONST1_RTX (TFmode);"
+{
+ operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
+ operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
+ operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
+ operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3]));
+ operands[10] = CONST1_RTX (TFmode);
+}
[(set_attr "predicable" "no")])
\f
;; ::::::::::::::::::::
(div:DF (match_operand:DF 1 "fr_register_operand" "")
(match_operand:DF 2 "fr_register_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
- "
{
rtx insn;
if (TARGET_INLINE_DIV_LAT)
insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]);
emit_insn (insn);
DONE;
-}")
+})
(define_insn_and_split "divdf3_internal_lat"
[(set (match_operand:DF 0 "fr_register_operand" "=&f")
(float_truncate:DF (plus:TF (mult:TF (match_dup 5) (match_dup 7))
(match_dup 3)))))
]
- "operands[7] = gen_rtx_REG (TFmode, REGNO (operands[0]));
- operands[8] = gen_rtx_REG (TFmode, REGNO (operands[1]));
- operands[9] = gen_rtx_REG (TFmode, REGNO (operands[2]));
- operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3]));
- operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5]));
- operands[12] = CONST1_RTX (TFmode);"
+{
+ operands[7] = gen_rtx_REG (TFmode, REGNO (operands[0]));
+ operands[8] = gen_rtx_REG (TFmode, REGNO (operands[1]));
+ operands[9] = gen_rtx_REG (TFmode, REGNO (operands[2]));
+ operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3]));
+ operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5]));
+ operands[12] = CONST1_RTX (TFmode);
+}
[(set_attr "predicable" "no")])
(define_insn_and_split "divdf3_internal_thr"
(plus:DF (mult:DF (match_dup 4) (match_dup 0))
(match_dup 9))))
]
- "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
- operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
- operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
- operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3]));
- operands[10] = CONST1_RTX (TFmode);"
+{
+ operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
+ operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
+ operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
+ operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3]));
+ operands[10] = CONST1_RTX (TFmode);
+}
[(set_attr "predicable" "no")])
\f
;; ::::::::::::::::::::
(div:TF (match_operand:TF 1 "fr_register_operand" "")
(match_operand:TF 2 "fr_register_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
- "
{
rtx insn;
if (TARGET_INLINE_DIV_LAT)
insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]);
emit_insn (insn);
DONE;
-}")
+})
(define_insn_and_split "divtf3_internal_lat"
[(set (match_operand:TF 0 "fr_register_operand" "=&f")
(ashift:SI (match_operand:SI 1 "gr_register_operand" "")
(match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
""
- "
{
if (GET_CODE (operands[2]) != CONST_INT)
{
emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
operands[2] = subshift;
}
-}")
+})
(define_insn "*ashlsi3_internal"
[(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
(ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
(match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
""
- "
{
rtx subtarget = gen_reg_rtx (DImode);
if (GET_CODE (operands[2]) == CONST_INT)
}
emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
DONE;
-}")
+})
(define_expand "lshrsi3"
[(set (match_operand:SI 0 "gr_register_operand" "")
(lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
(match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
""
- "
{
rtx subtarget = gen_reg_rtx (DImode);
if (GET_CODE (operands[2]) == CONST_INT)
}
emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
DONE;
-}")
+})
;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result
;; here, instead of 64 like the patterns above. Keep the pattern together
(rotatert:SI (match_operand:SI 1 "gr_register_operand" "")
(match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
""
- "
{
if (GET_MODE (operands[2]) != VOIDmode)
{
emit_insn (gen_zero_extendsidi2 (tmp, operands[2]));
operands[2] = tmp;
}
-}")
+})
(define_insn_and_split "*rotrsi3_internal"
[(set (match_operand:SI 0 "gr_register_operand" "=&r")
(rotate:SI (match_operand:SI 1 "gr_register_operand" "")
(match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
""
- "
{
if (! shift_32bit_count_operand (operands[2], SImode))
{
emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp));
DONE;
}
-}")
+})
(define_insn_and_split "*rotlsi3_internal"
[(set (match_operand:SI 0 "gr_register_operand" "=r")
(ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
(set (match_dup 3)
(lshiftrt:DI (match_dup 3) (match_dup 2)))]
- "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));
- operands[2] = GEN_INT (32 - INTVAL (operands[2]));")
+{
+ operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));
+ operands[2] = GEN_INT (32 - INTVAL (operands[2]));
+})
\f
;; ::::::::::::::::::::
;; ::
(rotatert:DI (match_operand:DI 1 "gr_register_operand" "")
(match_operand:DI 2 "nonmemory_operand" "")))]
""
- "
{
if (! shift_count_operand (operands[2], DImode))
FAIL;
-}")
+})
(define_insn "*rotrdi3_internal"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(rotate:DI (match_operand:DI 1 "gr_register_operand" "")
(match_operand:DI 2 "nonmemory_operand" "")))]
""
- "
{
if (! shift_count_operand (operands[2], DImode))
FAIL;
-}")
+})
(define_insn "*rotldi3_internal"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(compare (match_operand:BI 0 "register_operand" "")
(match_operand:BI 1 "const_int_operand" "")))]
""
- "
{
ia64_compare_op0 = operands[0];
ia64_compare_op1 = operands[1];
DONE;
-}")
+})
(define_expand "cmpsi"
[(set (cc0)
(compare (match_operand:SI 0 "gr_register_operand" "")
(match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
""
- "
{
ia64_compare_op0 = operands[0];
ia64_compare_op1 = operands[1];
DONE;
-}")
+})
(define_expand "cmpdi"
[(set (cc0)
(compare (match_operand:DI 0 "gr_register_operand" "")
(match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
""
- "
{
ia64_compare_op0 = operands[0];
ia64_compare_op1 = operands[1];
DONE;
-}")
+})
(define_expand "cmpsf"
[(set (cc0)
(compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "")
(match_operand:SF 1 "fr_reg_or_fp01_operand" "")))]
""
- "
{
ia64_compare_op0 = operands[0];
ia64_compare_op1 = operands[1];
DONE;
-}")
+})
(define_expand "cmpdf"
[(set (cc0)
(compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "")
(match_operand:DF 1 "fr_reg_or_fp01_operand" "")))]
""
- "
{
ia64_compare_op0 = operands[0];
ia64_compare_op1 = operands[1];
DONE;
-}")
+})
(define_expand "cmptf"
[(set (cc0)
(compare (match_operand:TF 0 "tfreg_or_fp01_operand" "")
(match_operand:TF 1 "tfreg_or_fp01_operand" "")))]
"INTEL_EXTENDED_IEEE_FORMAT"
- "
{
ia64_compare_op0 = operands[0];
ia64_compare_op1 = operands[1];
DONE;
-}")
+})
(define_insn "*cmpsi_normal"
[(set (match_operand:BI 0 "register_operand" "=c")
(use (match_operand 3 "" "")) ; loop level
(use (match_operand 4 "" ""))] ; label
""
- "
{
/* Only use cloop on innermost loops. */
if (INTVAL (operands[3]) > 1)
emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM),
operands[4]));
DONE;
-}")
+})
(define_insn "doloop_end_internal"
[(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "")
"rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))]
"ia64_move_ok (operands[0], operands[2])
&& ia64_move_ok (operands[0], operands[3])"
- "* abort ();"
+ { abort (); }
[(set_attr "predicable" "no")])
(define_split
(match_operand 3 "move_operand" "")))]
"reload_completed"
[(const_int 0)]
- "
{
rtx tmp;
if (! rtx_equal_p (operands[0], operands[2]))
emit_insn (tmp);
}
DONE;
-}")
+})
;; Absolute value pattern.
(cond_exec
(match_dup 5)
(set (match_dup 0) (match_dup 3)))]
- "
{
operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
VOIDmode, operands[1], const0_rtx);
-}")
+})
;;
;; SImode if_then_else patterns.
"rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
"ia64_move_ok (operands[0], operands[2])
&& ia64_move_ok (operands[0], operands[3])"
- "* abort ();"
+ { abort (); }
[(set_attr "predicable" "no")])
(define_insn "*abssi2_internal"
(cond_exec
(match_dup 5)
(set (match_dup 0) (match_dup 3)))]
- "
{
operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
VOIDmode, operands[1], const0_rtx);
-}")
+})
(define_insn_and_split "*cond_opsi2_internal"
[(set (match_operand:SI 0 "gr_register_operand" "=r")
(cond_exec
(match_dup 7)
(set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))]
- "
{
operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
VOIDmode, operands[1], const0_rtx);
-}"
+}
[(set_attr "itanium_class" "ialu")
(set_attr "predicable" "no")])
(cond_exec
(match_dup 7)
(set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))]
- "
{
operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
VOIDmode, operands[1], const0_rtx);
-}"
+}
[(set_attr "itanium_class" "ialu")
(set_attr "predicable" "no")])
(use (match_operand 2 "" ""))
(use (match_operand 3 "" ""))]
""
- "
{
ia64_expand_call (NULL_RTX, operands[0], operands[2], 0);
DONE;
-}")
+})
(define_expand "sibcall"
[(use (match_operand:DI 0 "" ""))
(use (match_operand 2 "" ""))
(use (match_operand 3 "" ""))]
""
- "
{
ia64_expand_call (NULL_RTX, operands[0], operands[2], 1);
DONE;
-}")
+})
;; Subroutine call instruction returning a value. Operand 0 is the hard
;; register in which the value is returned. There are three more operands,
(use (match_operand 3 "" ""))
(use (match_operand 4 "" ""))]
""
- "
{
ia64_expand_call (operands[0], operands[1], operands[3], 0);
DONE;
-}")
+})
(define_expand "sibcall_value"
[(use (match_operand 0 "" ""))
(use (match_operand 3 "" ""))
(use (match_operand 4 "" ""))]
""
- "
{
ia64_expand_call (operands[0], operands[1], operands[3], 1);
DONE;
-}")
+})
;; Call subroutine returning any type.
(match_operand 1 "" "")
(match_operand 2 "" "")])]
""
- "
{
int i;
emit_insn (gen_blockage ());
DONE;
-}")
+})
(define_insn "call_nopic"
[(call (mem:DI (match_operand:DI 0 "call_operand" "b,i"))
(define_expand "prologue"
[(const_int 1)]
""
- "
{
ia64_expand_prologue ();
DONE;
-}")
+})
(define_expand "epilogue"
[(return)]
""
- "
{
ia64_expand_epilogue (0);
DONE;
-}")
+})
(define_expand "sibcall_epilogue"
[(return)]
""
- "
{
ia64_expand_epilogue (1);
DONE;
-}")
+})
;; This prevents the scheduler from moving the SP decrement past FP-relative
;; stack accesses. This is the same as adddi3 plus the extra set.
(match_dup 3))]
""
"@
- add %0 = %1, %2
- adds %0 = %2, %1
- addl %0 = %2, %1"
+ add %0 = %1, %2
+ adds %0 = %2, %1
+ addl %0 = %2, %1"
[(set_attr "itanium_class" "ialu")])
;; This prevents the scheduler from moving the SP restore past FP-relative
"mov %0 = %1"
[(set_attr "itanium_class" "ialu")])
+;; As USE insns aren't meaningful after reload, this is used instead
+;; to prevent deleting instructions setting registers for EH handling
+(define_insn "prologue_use"
+ [(unspec:DI [(match_operand:DI 0 "register_operand" "")]
+ UNSPEC_PROLOGUE_USE)]
+ ""
+ ""
+ [(set_attr "itanium_class" "ignore")
+ (set_attr "predicable" "no")])
+
;; Allocate a new register frame.
(define_insn "alloc"
UNSPEC_GR_SPILL))
(clobber (match_operand:DI 3 "register_operand" ""))]
""
- "*
{
- return \".mem.offset %2, 0\;%,st8.spill %0 = %1%P0\";
-}"
+ /* Note that we use a C output pattern here to avoid the predicate
+ being automatically added before the .mem.offset directive. */
+ return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0";
+}
[(set_attr "itanium_class" "st")])
;; Reads ar.unat
UNSPEC_GR_RESTORE))
(use (match_operand:DI 3 "register_operand" ""))]
""
- "*
-{
- return \".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1\";
-}"
+ { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; }
[(set_attr "itanium_class" "ld")])
(define_insn "fr_spill"
[(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
UNSPECV_SET_BSP)]
""
- "flushrs\;mov r19=ar.rsc\;;;\;and r19=0x1c,r19\;;;\;mov ar.rsc=r19\;;;\;mov ar.bspstore=%0\;;;\;or r19=0x3,r19\;;;\;loadrs\;invala\;;;\;mov ar.rsc=r19"
+ "flushrs
+ mov r19=ar.rsc
+ ;;
+ and r19=0x1c,r19
+ ;;
+ mov ar.rsc=r19
+ ;;
+ mov ar.bspstore=%0
+ ;;
+ or r19=0x3,r19
+ ;;
+ loadrs
+ invala
+ ;;
+ mov ar.rsc=r19"
[(set_attr "itanium_class" "unknown")
(set_attr "predicable" "no")])
(define_insn "bundle_selector"
[(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)]
""
- "*
-{
- return get_bundle_name (INTVAL (operands[0]));
-}"
+ { return get_bundle_name (INTVAL (operands[0])); }
[(set_attr "itanium_class" "ignore")
(set_attr "predicable" "no")])
[(use (match_operand:OI 0 "memory_operand" ""))
(use (match_operand:DI 1 "register_operand" ""))]
""
- "
{
emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
\"__ia64_save_stack_nonlocal\"),
0, VOIDmode, 2, XEXP (operands[0], 0), Pmode,
operands[1], Pmode);
DONE;
-}")
+})
(define_expand "nonlocal_goto"
[(use (match_operand 0 "general_operand" ""))
(use (match_operand 2 "general_operand" ""))
(use (match_operand 3 "general_operand" ""))]
""
- "
{
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"),
LCT_NORETURN, VOIDmode, 3,
operands[3], Pmode);
emit_barrier ();
DONE;
-}")
+})
;; The rest of the setjmp processing happens with the nonlocal_goto expander.
;; ??? This is not tested.
(define_expand "builtin_setjmp_setup"
[(use (match_operand:DI 0 "" ""))]
""
- "
{
emit_move_insn (ia64_gp_save_reg (0), gen_rtx_REG (DImode, GR_REG (1)));
DONE;
-}")
+})
(define_expand "builtin_setjmp_receiver"
[(use (match_operand:DI 0 "" ""))]
""
- "
{
emit_move_insn (gen_rtx_REG (DImode, GR_REG (1)), ia64_gp_save_reg (0));
DONE;
-}")
+})
(define_expand "eh_epilogue"
[(use (match_operand:DI 0 "register_operand" "r"))
(use (match_operand:DI 1 "register_operand" "r"))
(use (match_operand:DI 2 "register_operand" "r"))]
""
- "
{
rtx bsp = gen_rtx_REG (Pmode, 10);
rtx sp = gen_rtx_REG (Pmode, 9);
cfun->machine->ia64_eh_epilogue_sp = sp;
cfun->machine->ia64_eh_epilogue_bsp = bsp;
-}")
+})
\f
;; Builtin apply support.
[(use (match_operand:DI 0 "register_operand" ""))
(use (match_operand:OI 1 "memory_operand" ""))]
""
- "
{
emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
- \"__ia64_restore_stack_nonlocal\"),
+ "__ia64_restore_stack_nonlocal"),
0, VOIDmode, 1,
copy_to_reg (XEXP (operands[1], 0)), Pmode);
DONE;
-}")
+})
\f
;;; Intrinsics support.
[(set (mem:BLK (match_dup 0))
(unspec:BLK [(mem:BLK (match_dup 0))] UNSPEC_MF))]
""
- "
{
operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
MEM_VOLATILE_P (operands[0]) = 1;
-}")
+})
(define_insn "*mf_internal"
[(set (match_operand:BLK 0 "" "")
(define_insn "safe_across_calls_normal"
[(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)]
""
- "*
{
emit_safe_across_calls (asm_out_file);
- return \"\";
-}"
+ return "";
+}
[(set_attr "itanium_class" "ignore")
(set_attr "predicable" "no")])
""
"addp4 %0 = %1, %2"
[(set_attr "itanium_class" "ialu")])
-
-;; As USE insns aren't meaningful after reload, this is used instead
-;; to prevent deleting instructions setting registers for EH handling
-(define_insn "prologue_use"
- [(unspec:DI [(match_operand:DI 0 "register_operand" "")]
- UNSPEC_PROLOGUE_USE)]
- ""
- "// %0 needed for EH"
- [(set_attr "itanium_class" "ignore")
- (set_attr "predicable" "no")])
projects / platform / upstream / linaro-gcc.git / commitdiff