SegmentCache idt; /* only base and limit are used */
target_ulong cr[5]; /* NOTE: cr1 is unused */
- uint64_t a20_mask;
+ int32_t a20_mask;
/* FPU state */
unsigned int fpstt; /* top of stack index */
eflags & CC_C ? 'C' : '-',
env->hflags & HF_CPL_MASK,
(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
- (int)(env->a20_mask >> 20) & 1,
+ (env->a20_mask >> 20) & 1,
(env->hflags >> HF_SMM_SHIFT) & 1,
env->halted);
} else
eflags & CC_C ? 'C' : '-',
env->hflags & HF_CPL_MASK,
(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
- (int)(env->a20_mask >> 20) & 1,
+ (env->a20_mask >> 20) & 1,
(env->hflags >> HF_SMM_SHIFT) & 1,
env->halted);
}
/* when a20 is changed, all the MMU mappings are invalid, so
we must flush everything */
tlb_flush(env, 1);
- env->a20_mask = (~0x100000) | (a20_state << 20);
+ env->a20_mask = ~(1 << 20) | (a20_state << 20);
}
}
{
CPUState *env = opaque;
uint16_t fptag, fpus, fpuc, fpregs_format;
- int32_t a20_mask;
int32_t pending_irq;
int i, bit;
qemu_put_betls(f, &env->dr[i]);
/* MMU */
- a20_mask = (int32_t) env->a20_mask;
- qemu_put_sbe32s(f, &a20_mask);
+ qemu_put_sbe32s(f, &env->a20_mask);
/* XMM */
qemu_put_be32s(f, &env->mxcsr);
CPUState *env = opaque;
int i, guess_mmx;
uint16_t fpus, fpuc, fptag, fpregs_format;
- int32_t a20_mask;
int32_t pending_irq;
cpu_synchronize_state(env);
for (i = 0; i < 4; i++)
hw_breakpoint_insert(env, i);
- /* MMU */
- qemu_get_sbe32s(f, &a20_mask);
- env->a20_mask = a20_mask;
+ qemu_get_sbe32s(f, &env->a20_mask);
qemu_get_be32s(f, &env->mxcsr);
for(i = 0; i < CPU_NB_REGS; i++) {