; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: not a3, a3
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w a1, a1, (a2)
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aq a1, a1, (a2)
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.rl a1, a1, (a2)
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoor.w.aqrl a1, a1, (a2)
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w a1, a1, (a2)
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aq a1, a1, (a2)
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.rl a1, a1, (a2)
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: amoxor.w.aqrl a1, a1, (a2)
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB35_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB35_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB36_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB36_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB37_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB37_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB38_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB38_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB39_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB39_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB40_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB40_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB40_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB41_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB41_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB41_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB42_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB42_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB42_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB43_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB43_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB43_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: addi a3, zero, 255
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: addi a4, zero, 255
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 56
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 56
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB44_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB44_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB44_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: addi a3, zero, 255
; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: and a1, a1, a3
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB90_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB90_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB90_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB90_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB91_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB91_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB91_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB91_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB92_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB92_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB92_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB92_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB93_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB93_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB93_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB93_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB94_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a3, a1, .LBB94_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a4, a1, .LBB94_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB94_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB95_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB95_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB95_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB96_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB96_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB96_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB97_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB97_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB97_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB98_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB98_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB98_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addiw a3, a3, -1
-; RV64IA-NEXT: sllw a7, a3, a0
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addiw a4, a4, -1
+; RV64IA-NEXT: sllw a7, a4, a0
; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: addi a4, zero, 48
-; RV64IA-NEXT: sub a4, a4, a0
+; RV64IA-NEXT: addi a5, zero, 48
+; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a5, (a6)
-; RV64IA-NEXT: and a3, a5, a7
+; RV64IA-NEXT: and a4, a5, a7
; RV64IA-NEXT: mv a2, a5
-; RV64IA-NEXT: sll a3, a3, a4
-; RV64IA-NEXT: sra a3, a3, a4
-; RV64IA-NEXT: bge a1, a3, .LBB99_3
+; RV64IA-NEXT: sll a4, a4, a3
+; RV64IA-NEXT: sra a4, a4, a3
+; RV64IA-NEXT: bge a1, a4, .LBB99_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB99_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1
; RV64IA-NEXT: and a2, a2, a7
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0