Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
fadd-op ::= ssa-id `=` `spv.FAdd` ssa-use, ssa-use
`:` float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.FAdd %0, %1 : f32
%5 = spv.FAdd %2, %3 : vector<4xf32>
```
Results are computed per component. The resulting value is undefined
if Operand 2 is 0.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
`:` float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.FDiv %0, %1 : f32
%5 = spv.FDiv %2, %3 : vector<4xf32>
```
1 divided by Operand 2 where if r ≠ 0, the sign of r is the same as the
sign of Operand 2.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
fmod-op ::= ssa-id `=` `spv.FMod` ssa-use, ssa-use
`:` float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.FMod %0, %1 : f32
%5 = spv.FMod %2, %3 : vector<4xf32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`:` float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.FMul %0, %1 : f32
%5 = spv.FMul %2, %3 : vector<4xf32>
```
// -----
def SPV_FNegateOp : SPV_ArithmeticUnaryOp<"FNegate", SPV_Float, []> {
- let summary = "Floating-point subtract of Operand from zero.";
+ let summary = [{
+ Inverts the sign bit of Operand. (Note, however, that OpFNegate is still
+ considered a floating-point instruction, and so is subject to the
+ general floating-point rules regarding, for example, subnormals and NaN
+ propagation).
+ }];
let description = [{
Result Type must be a scalar or vector of floating-point type.
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
fmul-op ::= `spv.FNegate` ssa-use `:` float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%1 = spv.FNegate %0 : f32
%3 = spv.FNegate %2 : vector<4xf32>
```
1 divided by Operand 2 where if r ≠ 0, the sign of r is the same as the
sign of Operand 1.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
`:` float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.FRemOp %0, %1 : f32
%5 = spv.FRemOp %2, %3 : vector<4xf32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
`:` float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.FRemOp %0, %1 : f32
%5 = spv.FRemOp %2, %3 : vector<4xf32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.IAdd %0, %1 : i32
%5 = spv.IAdd %2, %3 : vector<4xi32>
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.IMul %0, %1 : i32
%5 = spv.IMul %2, %3 : vector<4xi32>
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.ISub %0, %1 : i32
%5 = spv.ISub %2, %3 : vector<4xi32>
Results are computed per component. The resulting value is undefined
if Operand 2 is 0.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.SDiv %0, %1 : i32
%5 = spv.SDiv %2, %3 : vector<4xi32>
1 divided by Operand 2 where if r ≠ 0, the sign of r is the same as the
sign of Operand 2.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
smod-op ::= ssa-id `=` `spv.SMod` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.SMod %0, %1 : i32
%5 = spv.SMod %2, %3 : vector<4xi32>
1 divided by Operand 2 where if r ≠ 0, the sign of r is the same as the
sign of Operand 1.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
srem-op ::= ssa-id `=` `spv.SRem` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.SRem %0, %1 : i32
%5 = spv.SRem %2, %3 : vector<4xi32>
Results are computed per component. The resulting value is undefined
if Operand 2 is 0.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
udiv-op ::= ssa-id `=` `spv.UDiv` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.UDiv %0, %1 : i32
%5 = spv.UDiv %2, %3 : vector<4xi32>
Results are computed per component. The resulting value is undefined
if Operand 2 is 0.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
umod-op ::= ssa-id `=` `spv.UMod` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.UMod %0, %1 : i32
%5 = spv.UMod %2, %3 : vector<4xi32>
Memory must be a valid memory Scope.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
scope ::= `"CrossDevice"` | `"Device"` | `"Workgroup"` | ...
ssa-use `,` ssa-use `:` spv-pointer-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.AtomicAnd "Device" "None" %pointer, %value :
!spv.ptr<i32, StorageBuffer>
```
Memory must be a valid memory Scope.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
atomic-compare-exchange-weak-op ::=
`:` spv-pointer-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.AtomicCompareExchangeWeak "Workgroup" "Acquire" "None"
%pointer, %value, %comparator
: !spv.ptr<i32, WorkGroup>
Memory must be a valid memory Scope.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
atomic-iadd-op ::=
ssa-use `,` ssa-use `:` spv-pointer-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.AtomicIAdd "Device" "None" %pointer, %value :
!spv.ptr<i32, StorageBuffer>
```
Memory must be a valid memory Scope.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
atomic-idecrement-op ::=
`:` spv-pointer-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.AtomicIDecrement "Device" "None" %pointer :
!spv.ptr<i32, StorageBuffer>
```
Memory must be a valid memory Scope.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
atomic-iincrement-op ::=
`:` spv-pointer-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.AtomicIncrement "Device" "None" %pointer :
!spv.ptr<i32, StorageBuffer>
```
Memory must be a valid memory Scope.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
atomic-isub-op ::=
ssa-use `,` ssa-use `:` spv-pointer-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.AtomicISub "Device" "None" %pointer, %value :
!spv.ptr<i32, StorageBuffer>
```
Memory must be a valid memory Scope.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
atomic-or-op ::=
ssa-use `,` ssa-use `:` spv-pointer-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.AtomicOr "Device" "None" %pointer, %value :
!spv.ptr<i32, StorageBuffer>
```
Memory must be a valid memory Scope.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
atomic-smax-op ::=
ssa-use `,` ssa-use `:` spv-pointer-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.AtomicSMax "Device" "None" %pointer, %value :
!spv.ptr<i32, StorageBuffer>
```
Memory must be a valid memory Scope.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
atomic-smin-op ::=
ssa-use `,` ssa-use `:` spv-pointer-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.AtomicSMin "Device" "None" %pointer, %value :
!spv.ptr<i32, StorageBuffer>
```
Memory must be a valid memory Scope.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
atomic-umax-op ::=
ssa-use `,` ssa-use `:` spv-pointer-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.AtomicUMax "Device" "None" %pointer, %value :
!spv.ptr<i32, StorageBuffer>
```
Memory must be a valid memory Scope.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
atomic-umin-op ::=
ssa-use `,` ssa-use `:` spv-pointer-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.AtomicUMin "Device" "None" %pointer, %value :
!spv.ptr<i32, StorageBuffer>
```
Memory must be a valid memory Scope.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
atomic-xor-op ::=
ssa-use `,` ssa-use `:` spv-pointer-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.AtomicXor "Device" "None" %pointer, %value :
!spv.ptr<i32, StorageBuffer>
```
The result is the unsigned value that is the number of bits in Base that
are 1.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.BitCount %0: i32
%3 = spv.BitCount %1: vector<4xi32>
```
The resulting value is undefined if Count or Offset or their sum is
greater than the number of bits in the result.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`,` integer-type `,` integer-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.BitFieldInsert %base, %insert, %offset, %count : vector<3xi32>, i8, i8
```
}];
The resulting value is undefined if Count or Offset or their sum is
greater than the number of bits in the result.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`,` integer-type `,` integer-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.BitFieldSExtract %base, %offset, %count : vector<3xi32>, i8, i8
```
}];
that there is no sign extension. The remaining bits of the result will
all be 0.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`,` integer-type `,` integer-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.BitFieldUExtract %base, %offset, %count : vector<3xi32>, i8, i8
```
}];
The bit-number n of the result will be taken from bit-number Width - 1 -
n of Base, where Width is the OpTypeInt operand of the Result Type.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.BitReverse %0 : i32
%3 = spv.BitReverse %1 : vector<4xi32>
```
They must have the same number of components as Result Type. They must
have the same component width as Result Type.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.BitwiseAnd %0, %1 : i32
%2 = spv.BitwiseAnd %0, %1 : vector<4xi32>
```
They must have the same number of components as Result Type. They must
have the same component width as Result Type.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.BitwiseOr %0, %1 : i32
%2 = spv.BitwiseOr %0, %1 : vector<4xi32>
```
They must have the same number of components as Result Type. They must
have the same component width as Result Type.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.BitwiseXor %0, %1 : i32
%2 = spv.BitwiseXor %0, %1 : vector<4xi32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.ShiftLeftLogical %0, %1 : i32, i16
%5 = spv.ShiftLeftLogical %3, %4 : vector<3xi32>, vector<3xi16>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.ShiftRightArithmetic %0, %1 : i32, i16
%5 = spv.ShiftRightArithmetic %3, %4 : vector<3xi32>, vector<3xi16>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.ShiftRightLogical %0, %1 : i32, i16
%5 = spv.ShiftRightLogical %3, %4 : vector<3xi32>, vector<3xi16>
```
have the same number of components as Result Type. The component width
must equal the component width in Result Type.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
not-op ::= ssa-id `=` `spv.BitNot` ssa-use `:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.Not %0 : i32
%3 = spv.Not %1 : vector<4xi32>
```
component of S (mapping to multiple components of L) maps its lower-
ordered bits to the lower-numbered components of L.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
bitcast-op ::= ssa-id `=` `spv.Bitcast` ssa-use
`:` operand-type `to` result-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%1 = spv.Bitcast %0 : f32 to i32
%1 = spv.Bitcast %0 : vector<2xf32> to i64
%1 = spv.Bitcast %0 : !spv.ptr<f32, Function> to !spv.ptr<i32, Function>
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
convert-f-to-s-op ::= ssa-id `=` `spv.ConvertFToSOp` ssa-use
`:` operand-type `to` result-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%1 = spv.ConvertFToS %0 : f32 to i32
%3 = spv.ConvertFToS %2 : vector<3xf32> to vector<3xi32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
convert-f-to-u-op ::= ssa-id `=` `spv.ConvertFToUOp` ssa-use
`:` operand-type `to` result-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%1 = spv.ConvertFToU %0 : f32 to i32
%3 = spv.ConvertFToU %2 : vector<3xf32> to vector<3xi32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
convert-s-to-f-op ::= ssa-id `=` `spv.ConvertSToFOp` ssa-use
`:` operand-type `to` result-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%1 = spv.ConvertSToF %0 : i32 to f32
%3 = spv.ConvertSToF %2 : vector<3xi32> to vector<3xf32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
convert-u-to-f-op ::= ssa-id `=` `spv.ConvertUToFOp` ssa-use
`:` operand-type `to` result-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%1 = spv.ConvertUToF %0 : i32 to f32
%3 = spv.ConvertUToF %2 : vector<3xi32> to vector<3xf32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
f-convert-op ::= ssa-id `=` `spv.FConvertOp` ssa-use
`:` operand-type `to` result-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%1 = spv.FConvertOp %0 : f32 to f64
%3 = spv.FConvertOp %2 : vector<3xf32> to vector<3xf64>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
s-convert-op ::= ssa-id `=` `spv.SConvertOp` ssa-use
`:` operand-type `to` result-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%1 = spv.SConvertOp %0 : i32 to i64
%3 = spv.SConvertOp %2 : vector<3xi32> to vector<3xi64>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
u-convert-op ::= ssa-id `=` `spv.UConvertOp` ssa-use
`:` operand-type `to` result-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%1 = spv.UConvertOp %0 : i32 to i64
%3 = spv.UConvertOp %2 : vector<3xi32> to vector<3xi64>
```
type of the result. When constructing a vector, there must be at least
two Constituent operands.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
composite-construct-op ::= ssa-id `=` `spv.CompositeConstruct`
(ssa-use (`,` ssa-use)* )? `:` composite-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.CompositeConstruct %1, %2, %3 : vector<3xf32>
```
}];
bounds. All composite constituents use zero-based numbering, as
described by their OpType… instruction.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
composite-extract-op ::= ssa-id `=` `spv.CompositeExtract` ssa-use
`:` composite-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.Variable : !spv.ptr<!spv.array<4x!spv.array<4xf32>>, Function>
%1 = spv.Load "Function" %0 ["Volatile"] : !spv.array<4x!spv.array<4xf32>>
%2 = spv.CompositeExtract %1[1 : i32] : !spv.array<4x!spv.array<4xf32>>
numbering, as described by their OpType… instruction. The type of the
part selected to modify must match the type of Object.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
composite-insert-op ::= ssa-id `=` `spv.CompositeInsert` ssa-use, ssa-use
`:` object-type `into` composite-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.CompositeInsert %object, %composite[1 : i32] : f32 into !spv.array<4xf32>
```
}];
let description = [{
This instruction must be the last instruction in a block.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
branch-op ::= `spv.Branch` successor
branch-use-list ::= `(` ssa-use-list `:` type-list-no-parens `)`
```
- For example:
+ #### Example:
- ```
+ ```mlir
spv.Branch ^target
spv.Branch ^target(%0, %1: i32, f32)
```
This instruction must be the last instruction in a block.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
branch-conditional-op ::= `spv.BranchConditional` ssa-use
branch-use-list ::= `(` ssa-use-list `:` type-list-no-parens `)`
```
- For example:
+ #### Example:
- ```
+ ```mlir
spv.BranchConditional %condition, ^true_branch, ^false_branch
spv.BranchConditional %condition, ^true_branch(%0: i32), ^false_branch(%1: i32)
```
information: Result Type must match the Return Type of the function, and
the calling argument types must match the formal parameter types.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
function-call-op ::= `spv.FunctionCall` function-id `(` ssa-use-list `)`
`:` function-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
spv.FunctionCall @f_void(%arg0) : (i32) -> ()
%0 = spv.FunctionCall @f_iadd(%arg0, %arg1) : (i32, i32) -> i32
```
let description = [{
This instruction must be the last instruction in a block.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
return-op ::= `spv.Return`
let description = [{
This instruction must be the last instruction in a block.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
unreachable-op ::= `spv.Unreachable`
This instruction must be the last instruction in a block.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
return-value-op ::= `spv.ReturnValue` ssa-use `:` spirv-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
spv.ReturnValue %0 : f32
```
}];
Result Type and the type of x must be the same type. Results are computed
per component.
- ### Custom assembly format
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
abs-op ::= ssa-id `=` `spv.GLSL.FAbs` ssa-use `:`
float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.GLSL.FAbs %0 : f32
%3 = spv.GLSL.FAbs %1 : vector<3xf16>
```
types. Result Type and operand types must have the same number of components
with the same component width. Results are computed per component.
- ### Custom assembly format
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
abs-op ::= ssa-id `=` `spv.GLSL.SAbs` ssa-use `:`
integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.GLSL.SAbs %0 : i32
%3 = spv.GLSL.SAbs %1 : vector<3xi16>
```
Result Type and the type of x must be the same type. Results are computed
per component.
- ### Custom assembly format
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
ceil-op ::= ssa-id `=` `spv.GLSL.Ceil` ssa-use `:`
float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.GLSL.Ceil %0 : f32
%3 = spv.GLSL.Ceil %1 : vector<3xf16>
```
Result Type and the type of x must be the same type. Results are computed
per component.
- ### Custom assembly format
+ <!-- End of AutoGen section -->
```
restricted-float-scalar-type ::= `f16` | `f32`
restricted-float-scalar-vector-type ::=
cos-op ::= ssa-id `=` `spv.GLSL.Cos` ssa-use `:`
restricted-float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.GLSL.Cos %0 : f32
%3 = spv.GLSL.Cos %1 : vector<3xf16>
```
Result Type and the type of x must be the same type. Results are computed
per component.
- ### Custom assembly format
+ <!-- End of AutoGen section -->
```
restricted-float-scalar-type ::= `f16` | `f32`
restricted-float-scalar-vector-type ::=
sin-op ::= ssa-id `=` `spv.GLSL.Sin` ssa-use `:`
restricted-float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.GLSL.Sin %0 : f32
%3 = spv.GLSL.Sin %1 : vector<3xf16>
```
Result Type and the type of x must be the same type. Results are
computed per component.";
- ### Custom assembly format
+ <!-- End of AutoGen section -->
```
restricted-float-scalar-type ::= `f16` | `f32`
restricted-float-scalar-vector-type ::=
exp-op ::= ssa-id `=` `spv.GLSL.Exp` ssa-use `:`
restricted-float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.GLSL.Exp %0 : f32
%3 = spv.GLSL.Exp %1 : vector<3xf16>
```
Result Type and the type of x must be the same type. Results are computed
per component.
- ### Custom assembly format
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
floor-op ::= ssa-id `=` `spv.GLSL.Floor` ssa-use `:`
float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.GLSL.Floor %0 : f32
%3 = spv.GLSL.Floor %1 : vector<3xf16>
```
Result Type and the type of x must be the same type. Results are computed
per component.
- ### Custom assembly format
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
rsqrt-op ::= ssa-id `=` `spv.GLSL.InverseSqrt` ssa-use `:`
float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.GLSL.InverseSqrt %0 : f32
%3 = spv.GLSL.InverseSqrt %1 : vector<3xf16>
```
Result Type and the type of x must be the same type. Results are computed
per component.
- ### Custom assembly format
+ <!-- End of AutoGen section -->
```
restricted-float-scalar-type ::= `f16` | `f32`
restricted-float-scalar-vector-type ::=
log-op ::= ssa-id `=` `spv.GLSL.Log` ssa-use `:`
restricted-float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.GLSL.Log %0 : f32
%3 = spv.GLSL.Log %1 : vector<3xf16>
```
Result Type and the type of all operands must be the same
type. Results are computed per component.
- ### Custom assembly format
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
fmax-op ::= ssa-id `=` `spv.GLSL.FMax` ssa-use `:`
float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.GLSL.FMax %0, %1 : f32
%3 = spv.GLSL.FMax %0, %1 : vector<3xf16>
```
components with the same component width. Results are computed per
component.
- ### Custom assembly format
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
smax-op ::= ssa-id `=` `spv.GLSL.SMax` ssa-use `:`
integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.GLSL.SMax %0, %1 : i32
%3 = spv.GLSL.SMax %0, %1 : vector<3xi16>
```
Result Type and the type of all operands must be the same type. Results are
computed per component.
- ### Custom assembly format
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
fmin-op ::= ssa-id `=` `spv.GLSL.FMin` ssa-use `:`
float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.GLSL.FMin %0, %1 : f32
%3 = spv.GLSL.FMin %0, %1 : vector<3xf16>
```
components with the same component width. Results are computed per
component.
- ### Custom assembly format
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
smin-op ::= ssa-id `=` `spv.GLSL.SMin` ssa-use `:`
integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.GLSL.SMin %0, %1 : i32
%3 = spv.GLSL.SMin %0, %1 : vector<3xi16>
```
Result Type and the type of x must be the same type. Results are computed
per component.
- ### Custom assembly format
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
sign-op ::= ssa-id `=` `spv.GLSL.FSign` ssa-use `:`
float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.GLSL.FSign %0 : f32
%3 = spv.GLSL.FSign %1 : vector<3xf16>
```
types. Result Type and operand types must have the same number of components
with the same component width. Results are computed per component.
- ### Custom assembly format
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
sign-op ::= ssa-id `=` `spv.GLSL.SSign` ssa-use `:`
integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.GLSL.SSign %0 : i32
%3 = spv.GLSL.SSign %1 : vector<3xi16>
```
Result Type and the type of x must be the same type. Results are computed
per component.
- ### Custom assembly format
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
sqrt-op ::= ssa-id `=` `spv.GLSL.Sqrt` ssa-use `:`
float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.GLSL.Sqrt %0 : f32
%3 = spv.GLSL.Sqrt %1 : vector<3xf16>
```
Result Type and the type of x must be the same type. Results are computed
per component.
- ### Custom assembly format
+ <!-- End of AutoGen section -->
```
restricted-float-scalar-type ::= `f16` | `f32`
restricted-float-scalar-vector-type ::=
tanh-op ::= ssa-id `=` `spv.GLSL.Tanh` ssa-use `:`
restricted-float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.GLSL.Tanh %0 : f32
%3 = spv.GLSL.Tanh %1 : vector<3xf16>
```
higher bit number of the last bitmask needed to represent all bits of the
subgroup invocations.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
subgroup-ballot-op ::= ssa-id `=` `spv.SubgroupBallotKHR`
ssa-use `:` `vector` `<` 4 `x` `i32` `>`
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.SubgroupBallotKHR %predicate : vector<4xi32>
```
}];
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
fordequal-op ::= ssa-id `=` `spv.FOrdEqual` ssa-use, ssa-use
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.FOrdEqual %0, %1 : f32
%5 = spv.FOrdEqual %2, %3 : vector<4xf32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
fordgt-op ::= ssa-id `=` `spv.FOrdGreaterThan` ssa-use, ssa-use
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.FOrdGreaterThan %0, %1 : f32
%5 = spv.FOrdGreaterThan %2, %3 : vector<4xf32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
fordgte-op ::= ssa-id `=` `spv.FOrdGreaterThanEqual` ssa-use, ssa-use
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.FOrdGreaterThanEqual %0, %1 : f32
%5 = spv.FOrdGreaterThanEqual %2, %3 : vector<4xf32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
fordlt-op ::= ssa-id `=` `spv.FOrdLessThan` ssa-use, ssa-use
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.FOrdLessThan %0, %1 : f32
%5 = spv.FOrdLessThan %2, %3 : vector<4xf32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
fordlte-op ::= ssa-id `=` `spv.FOrdLessThanEqual` ssa-use, ssa-use
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.FOrdLessThanEqual %0, %1 : f32
%5 = spv.FOrdLessThanEqual %2, %3 : vector<4xf32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
fordneq-op ::= ssa-id `=` `spv.FOrdNotEqual` ssa-use, ssa-use
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.FOrdNotEqual %0, %1 : f32
%5 = spv.FOrdNotEqual %2, %3 : vector<4xf32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
funordequal-op ::= ssa-id `=` `spv.FUnordEqual` ssa-use, ssa-use
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.FUnordEqual %0, %1 : f32
%5 = spv.FUnordEqual %2, %3 : vector<4xf32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
funordgt-op ::= ssa-id `=` `spv.FUnordGreaterThan` ssa-use, ssa-use
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.FUnordGreaterThan %0, %1 : f32
%5 = spv.FUnordGreaterThan %2, %3 : vector<4xf32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
funordgte-op ::= ssa-id `=` `spv.FUnordGreaterThanEqual` ssa-use, ssa-use
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.FUnordGreaterThanEqual %0, %1 : f32
%5 = spv.FUnordGreaterThanEqual %2, %3 : vector<4xf32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
funordlt-op ::= ssa-id `=` `spv.FUnordLessThan` ssa-use, ssa-use
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.FUnordLessThan %0, %1 : f32
%5 = spv.FUnordLessThan %2, %3 : vector<4xf32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
funordlte-op ::= ssa-id `=` `spv.FUnordLessThanEqual` ssa-use, ssa-use
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.FUnordLessThanEqual %0, %1 : f32
%5 = spv.FUnordLessThanEqual %2, %3 : vector<4xf32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
funordneq-op ::= ssa-id `=` `spv.FUnordNotEqual` ssa-use, ssa-use
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.FUnordNotEqual %0, %1 : f32
%5 = spv.FUnordNotEqual %2, %3 : vector<4xf32>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
iequal-op ::= ssa-id `=` `spv.IEqual` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.IEqual %0, %1 : i32
%5 = spv.IEqual %2, %3 : vector<4xi32>
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
inot-equal-op ::= ssa-id `=` `spv.INotEqual` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.INotEqual %0, %1 : i32
%5 = spv.INotEqual %2, %3 : vector<4xi32>
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
logical-and ::= `spv.LogicalAnd` ssa-use `,` ssa-use
`:` operand-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.LogicalAnd %0, %1 : i1
%2 = spv.LogicalAnd %0, %1 : vector<4xi1>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
logical-equal ::= `spv.LogicalEqual` ssa-use `,` ssa-use
`:` operand-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.LogicalEqual %0, %1 : i1
%2 = spv.LogicalEqual %0, %1 : vector<4xi1>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
logical-not ::= `spv.LogicalNot` ssa-use `:` operand-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.LogicalNot %0 : i1
%2 = spv.LogicalNot %0 : vector<4xi1>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
logical-not-equal ::= `spv.LogicalNotEqual` ssa-use `,` ssa-use
`:` operand-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.LogicalNotEqual %0, %1 : i1
%2 = spv.LogicalNotEqual %0, %1 : vector<4xi1>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
logical-or ::= `spv.LogicalOr` ssa-use `,` ssa-use
`:` operand-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%2 = spv.LogicalOr %0, %1 : i1
%2 = spv.LogicalOr %0, %1 : vector<4xi1>
```
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
sgreater-than-op ::= ssa-id `=` `spv.SGreaterThan` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.SGreaterThan %0, %1 : i32
%5 = spv.SGreaterThan %2, %3 : vector<4xi32>
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
sgreater-than-equal-op ::= ssa-id `=` `spv.SGreaterThanEqual` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
```
%4 = spv.SGreaterThanEqual %0, %1 : i32
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
sless-than-op ::= ssa-id `=` `spv.SLessThan` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.SLessThan %0, %1 : i32
%5 = spv.SLessThan %2, %3 : vector<4xi32>
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
sless-than-equal-op ::= ssa-id `=` `spv.SLessThanEqual` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.SLessThanEqual %0, %1 : i32
%5 = spv.SLessThanEqual %2, %3 : vector<4xi32>
component in the result is taken from Object 1, otherwise it is taken
from Object 2.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
scalar-type ::= integer-type | float-type | boolean-type
`:` select-condition-type `,` select-object-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%3 = spv.Select %0, %1, %2 : i1, f32
%3 = spv.Select %0, %1, %2 : i1, vector<3xi32>
%3 = spv.Select %0, %1, %2 : vector<3xi1>, vector<3xf32>
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
ugreater-than-op ::= ssa-id `=` `spv.UGreaterThan` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.UGreaterThan %0, %1 : i32
%5 = spv.UGreaterThan %2, %3 : vector<4xi32>
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
ugreater-than-equal-op ::= ssa-id `=` `spv.UGreaterThanEqual` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.UGreaterThanEqual %0, %1 : i32
%5 = spv.UGreaterThanEqual %2, %3 : vector<4xi32>
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
uless-than-op ::= ssa-id `=` `spv.ULessThan` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.ULessThan %0, %1 : i32
%5 = spv.ULessThan %2, %3 : vector<4xi32>
Results are computed per component.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
uless-than-equal-op ::= ssa-id `=` `spv.ULessThanEqual` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%4 = spv.ULessThanEqual %0, %1 : i32
%5 = spv.ULessThanEqual %2, %3 : vector<4xi32>
Predicate must be a Boolean type.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
scope ::= `"Workgroup"` | `"Subgroup"`
ssa-use `:` `vector` `<` 4 `x` `integer-type` `>`
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.GroupNonUniformBallot "SubGroup" %predicate : vector<4xi32>
```
}];
Execution must be Workgroup or Subgroup Scope.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
scope ::= `"Workgroup"` | `"Subgroup"`
`:` `i1`
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.GroupNonUniformElect : i1
```
}];
a power of 2. If ClusterSize is greater than the declared SubGroupSize,
executing this instruction results in undefined behavior.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
scope ::= `"Workgroup"` | `"Subgroup"`
`:` float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%four = spv.constant 4 : i32
%scalar = ... : f32
%vector = ... : vector<4xf32>
a power of 2. If ClusterSize is greater than the declared SubGroupSize,
executing this instruction results in undefined behavior.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
scope ::= `"Workgroup"` | `"Subgroup"`
`:` float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%four = spv.constant 4 : i32
%scalar = ... : f32
%vector = ... : vector<4xf32>
a power of 2. If ClusterSize is greater than the declared SubGroupSize,
executing this instruction results in undefined behavior.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
scope ::= `"Workgroup"` | `"Subgroup"`
`:` float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%four = spv.constant 4 : i32
%scalar = ... : f32
%vector = ... : vector<4xf32>
a power of 2. If ClusterSize is greater than the declared SubGroupSize,
executing this instruction results in undefined behavior.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
scope ::= `"Workgroup"` | `"Subgroup"`
`:` float-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%four = spv.constant 4 : i32
%scalar = ... : f32
%vector = ... : vector<4xf32>
a power of 2. If ClusterSize is greater than the declared SubGroupSize,
executing this instruction results in undefined behavior.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
scope ::= `"Workgroup"` | `"Subgroup"`
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%four = spv.constant 4 : i32
%scalar = ... : i32
%vector = ... : vector<4xi32>
a power of 2. If ClusterSize is greater than the declared SubGroupSize,
executing this instruction results in undefined behavior.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
scope ::= `"Workgroup"` | `"Subgroup"`
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%four = spv.constant 4 : i32
%scalar = ... : i32
%vector = ... : vector<4xi32>
a power of 2. If ClusterSize is greater than the declared SubGroupSize,
executing this instruction results in undefined behavior.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
scope ::= `"Workgroup"` | `"Subgroup"`
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%four = spv.constant 4 : i32
%scalar = ... : i32
%vector = ... : vector<4xi32>
a power of 2. If ClusterSize is greater than the declared SubGroupSize,
executing this instruction results in undefined behavior.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
scope ::= `"Workgroup"` | `"Subgroup"`
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%four = spv.constant 4 : i32
%scalar = ... : i32
%vector = ... : vector<4xi32>
a power of 2. If ClusterSize is greater than the declared SubGroupSize,
executing this instruction results in undefined behavior.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
scope ::= `"Workgroup"` | `"Subgroup"`
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%four = spv.constant 4 : i32
%scalar = ... : i32
%vector = ... : vector<4xi32>
a power of 2. If ClusterSize is greater than the declared SubGroupSize,
executing this instruction results in undefined behavior.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
scope ::= `"Workgroup"` | `"Subgroup"`
`:` integer-scalar-vector-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%four = spv.constant 4 : i32
%scalar = ... : i32
%vector = ... : vector<4xi32>
- must be an OpConstant when indexing into a structure.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
access-chain-op ::= ssa-id `=` `spv.AccessChain` ssa-use
`[` ssa-use (',' ssa-use)* `]`
`:` pointer-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = "spv.constant"() { value = 1: i32} : () -> i32
%1 = spv.Variable : !spv.ptr<!spv.struct<f32, !spv.array<4xf32>>, Function>
%2 = spv.AccessChain %1[%0] : !spv.ptr<!spv.struct<f32, !spv.array<4xf32>>, Function>
OpControlBarrier will be visible to any other invocation after return
from that OpControlBarrier.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
scope ::= `"CrossDevice"` | `"Device"` | `"Workgroup"` | ...
control-barrier-op ::= `spv.ControlBarrier` scope, scope, memory-semantics
```
- For example:
+ #### Example:
- ```
+ ```mlir
spv.ControlBarrier "Workgroup", "Device", "Acquire|UniformMemory"
```
mode that takes no Extra Operands, or takes Extra Operands that are not
<id> operands.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
execution-mode ::= "Invocations" | "SpacingEqual" |
(integer-literal (`, ` integer-literal)* )?
```
- For example:
+ #### Example:
- ```
+ ```mlir
spv.ExecutionMode @foo "ContractionOff"
spv.ExecutionMode @bar "LocalSizeHint", 3, 4, 5
```
literal. If not present, it is the same as specifying the memory operand
None.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
memory-access ::= `"None"` | `"Volatile"` | `"Aligned", ` integer-literal
(`[` memory-access `]`)? ` : ` spirv-element-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.Variable : !spv.ptr<f32, Function>
%1 = spv.Load "Function" %0 : f32
%2 = spv.Load "Function" %0 ["Volatile"] : f32
To execute both a memory barrier and a control barrier, see
OpControlBarrier.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
scope ::= `"CrossDevice"` | `"Device"` | `"Workgroup"` | ...
memory-barrier-op ::= `spv.MemoryBarrier` scope, memory-semantics
```
- For example:
+ #### Example:
- ```
+ ```mlir
spv.MemoryBarrier "Device", "Acquire|UniformMemory"
```
literal. If not present, it is the same as specifying the memory operand
None.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
store-op ::= `spv.Store ` storage-class ssa-use `, ` ssa-use `, `
(`[` memory-access `]`)? `:` spirv-element-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.Variable : !spv.ptr<f32, Function>
%1 = spv.FMul ... : f32
spv.Store "Function" %0, %1 : f32
spv.Store "Function" %0, %1 ["Volatile"] : f32
spv.Store "Function" %0, %1 ["Aligned", 4] : f32
+ ```
}];
let arguments = (ins
OptionalAttr<I32Attr>:$alignment
);
+ let results = (outs);
+
let builders = [
OpBuilder<"Builder *builder, OperationState &state, "
"Value ptr, Value value, ArrayRef<NamedAttribute> namedAttrs = {}", [{
state.addAttributes(namedAttrs);
}]>
];
-
- let results = (outs);
}
// -----
bit pattern or abstract value resulting in possibly different concrete,
abstract, or opaque values.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
undef-op ::= `spv.undef` `:` spirv-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.undef : f32
%1 = spv.undef : !spv.struct<!spv.array<4 x vector<4xi32>>>
```
instruction. Initializer must have the same type as the type pointed to
by Result Type.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
variable-op ::= ssa-id `=` `spv.Variable` (`init(` ssa-use `)`)?
descriptor set and binding number. `built_in` specifies SPIR-V
BuiltIn decoration associated with the op.
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.constant ...
%1 = spv.Variable : !spv.ptr<f32, Function>
type, this op returns a pointer type as well, and the type is the same as
the variable referenced.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
spv-address-of-op ::= ssa-id `=` `spv._address_of` symbol-ref-id
`:` spirv-pointer-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv._address_of @global_var : !spv.ptr<f32, Input>
```
}];
and this op is purely mechanical; so it can be scoped to the binary
(de)serialization process.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
spv-constant-op ::= ssa-id `=` `spv.constant` attribute-value
(`:` spirv-type)?
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv.constant true
%1 = spv.constant dense<[2, 3]> : vector<2xf32>
%2 = spv.constant [dense<3.0> : vector<2xf32>] : !spv.array<1xvector<2xf32>>
storage classes are all storage classes used in declaring all
global variables referenced by the entry point’s call tree.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
execution-model ::= "Vertex" | "TesellationControl" |
symbol-reference (`, ` symbol-reference)*
```
- For example:
+ #### Example:
- ```
+ ```mlir
spv.EntryPoint "GLCompute" @foo
spv.EntryPoint "Kernel" @foo, @var1, @var2
This op itself takes no operands and generates no results. Its region
can take zero or more arguments and return zero or one values.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
spv-function-control ::= "None" | "Inline" | "DontInline" | ...
spv-function-control region
```
- For example:
+ #### Example:
- ```
+ ```mlir
spv.func @foo() -> () "None" { ... }
spv.func @bar() -> () "Inline|Pure" { ... }
```
`spv.globalVariable` operation in module scope. Initializer must
have the same type as the type of the defined symbol.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
variable-op ::= `spv.globalVariable` spirv-type symbol-ref-id
descriptor set and binding number. `built_in` specifies SPIR-V
BuiltIn decoration associated with the op.
- For example:
+ #### Example:
- ```
+ ```mlir
spv.globalVariable @var0 : !spv.ptr<f32, Input> @var0
spv.globalVariable @var1 initializer(@var0) : !spv.ptr<f32, Output>
spv.globalVariable @var2 bind(1, 2) : !spv.ptr<f32, Uniform>
This op has only one region, which only contains one block. The block
must be terminated via the `spv._module_end` op.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
addressing-model ::= `Logical` | `Physical32` | `Physical64` | ...
region
```
- For example:
+ #### Example:
- ```
+ ```mlir
spv.module Logical GLSL450 {}
spv.module Logical Vulkan
for modelling purpose in the SPIR-V dialect. This op's return type is
the same as the specialization constant.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
spv-reference-of-op ::= ssa-id `=` `spv._reference_of` symbol-ref-id
`:` spirv-scalar-type
```
- For example:
+ #### Example:
- ```
+ ```mlir
%0 = spv._reference_of @spec_const : f32
```
}];
`OpSpecConstantComposite` and `OpSpecConstantOp` are modelled with
separate ops.
- ### Custom assembly form
+ <!-- End of AutoGen section -->
```
spv-spec-constant-op ::= `spv.specConstant` symbol-ref-id
where `spec_id` specifies the SPIR-V SpecId decoration associated with
the op.
- For example:
+ #### Example:
- ```
+ ```mlir
spv.specConstant @spec_const1 = true
spv.specConstant @spec_const2 spec_id(5) = 42 : i32
```
"""
assert not (for_op and for_cap), 'cannot set both for_op and for_cap'
+ DEFAULT_MIN_VERSION = 'MinVersion<SPV_V_1_0>'
+ DEFAULT_MAX_VERSION = 'MaxVersion<SPV_V_1_5>'
+ DEFAULT_CAP = 'Capability<[]>'
+ DEFAULT_EXT = 'Extension<[]>'
+
min_version = enum_case.get('version', '')
if min_version == 'None':
min_version = ''
# TODO(antiagainst): delete this once ODS can support dialect-specific content
# and we can use omission to mean no requirements.
if for_op and not min_version:
- min_version = 'MinVersion<SPV_V_1_0>'
+ min_version = DEFAULT_MIN_VERSION
max_version = enum_case.get('lastVersion', '')
if max_version:
# TODO(antiagainst): delete this once ODS can support dialect-specific content
# and we can use omission to mean no requirements.
if for_op and not max_version:
- max_version = 'MaxVersion<SPV_V_1_5>'
+ max_version = DEFAULT_MAX_VERSION
exts = enum_case.get('extensions', [])
if exts:
# under such case should be interpreted as this symbol is introduced as
# a core symbol since the given version, rather than a minimal version
# requirement.
- min_version = 'MinVersion<SPV_V_1_0>' if for_op else ''
+ min_version = DEFAULT_MIN_VERSION if for_op else ''
# TODO(antiagainst): delete this once ODS can support dialect-specific content
# and we can use omission to mean no requirements.
if for_op and not exts:
- exts = 'Extension<[]>'
+ exts = DEFAULT_EXT
caps = enum_case.get('capabilities', [])
implies = ''
# TODO(antiagainst): delete this once ODS can support dialect-specific content
# and we can use omission to mean no requirements.
if for_op and not caps:
- caps = 'Capability<[]>'
+ caps = DEFAULT_CAP
avail = ''
- if min_version or max_version or caps or exts:
+ # Compose availability spec if any of the requirements is not empty.
+ # For ops, because we have a default in SPV_Op class, omit if the spec
+ # is the same.
+ if (min_version or max_version or caps or exts) and not (
+ for_op and min_version == DEFAULT_MIN_VERSION and
+ max_version == DEFAULT_MAX_VERSION and caps == DEFAULT_CAP and
+ exts == DEFAULT_EXT):
joined_spec = ',\n '.join(
[e for e in [min_version, max_version, exts, caps] if e])
avail = '{} availability = [\n {}\n ];'.format(
return '{}:${}'.format(arg_type, name)
-def get_description(text, assembly):
+def get_description(text, appendix):
"""Generates the description for the given SPIR-V instruction.
Arguments:
- text: Textual description of the operation as string.
- - assembly: Custom Assembly format with example as string.
+ - appendix: Additional contents to attach in description as string,
+ includking IR examples, and others.
Returns:
- A string that corresponds to the description of the Tablegen op.
"""
- fmt_str = ('{text}\n\n ### Custom assembly ' 'form\n{assembly}\n ')
- return fmt_str.format(
- text=text, assembly=assembly)
+ fmt_str = '{text}\n\n <!-- End of AutoGen section -->\n{appendix}\n '
+ return fmt_str.format(text=text, appendix=appendix)
def get_op_definition(instruction, doc, existing_info, capability_mapping):
opname = instruction['opname'][2:]
category_args = existing_info.get('category_args', '')
- # Make sure we have ', ' to separate the category arguments from traits
- category_args = category_args.rstrip(', ') + ', '
if '\n' in doc:
summary, text = doc.split('\n', 1)
operands = instruction.get('operands', [])
# Op availability
- avail = get_availability_spec(instruction, capability_mapping, True, False)
- if avail:
- avail = '\n\n {0}'.format(avail)
+ avail = ''
+ # We assume other instruction categories has a base availability spec, so
+ # only add this if this is directly using SPV_Op as the base.
+ if inst_category == 'Op':
+ avail = get_availability_spec(instruction, capability_mapping, True, False)
+ if avail:
+ avail = '\n\n {0}'.format(avail)
# Set op's result
results = ''
if description is None:
assembly = '\n ```\n'\
' [TODO]\n'\
- ' ```\n\n'\
- ' For example:\n\n'\
+ ' ```mlir\n\n'\
+ ' #### Example:\n\n'\
' ```\n'\
' [TODO]\n' \
' ```'
Returns:
- The substring if found
- The part of the base after end of the substring. Is the base string itself
- if the substring wasnt found.
+ if the substring wasn't found.
"""
split = base.split(start, 1)
if len(split) == 2:
while unmatched_start > 0 and index < len(rest):
if rest[index:].startswith(end):
unmatched_start -= 1
+ if unmatched_start == 0:
+ break
index += len(end)
elif rest[index:].startswith(start):
unmatched_start += 1
assert index < len(rest), \
'cannot find end "{end}" while extracting substring '\
'starting with "{start}"'.format(start=start, end=end)
- return rest[:index - len(end)].rstrip(end), rest[index:]
+ return rest[:index], rest[index + len(end):]
return '', split[0]
inst_category = inst_category[0] if len(inst_category) == 1 else 'Op'
# Get category_args
- op_tmpl_params = get_string_between_nested(op_def, '<', '>')[0]
+ op_tmpl_params, _ = get_string_between_nested(op_def, '<', '>')
opstringname, rest = get_string_between(op_tmpl_params, '"', '"')
category_args = rest.split('[', 1)[0]
# Get traits
- traits, _ = get_string_between(rest, '[', ']')
+ traits, _ = get_string_between_nested(rest, '[', ']')
# Get description
description, rest = get_string_between(op_def, 'let description = [{\n',