crypto: qat - add next neighbor to chip_info

Introduce the next neighbor (NN) capability in chip_info as NN registers
are not supported in certain SKUs of QAT.

Signed-off-by: Jack Xu <jack.xu@intel.com>
Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com>
Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h b/drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h
index 6b1ad62..8025be5 100644 (file)
--- a/drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h
+++ b/drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h
@@ -24,6 +24,7 @@ struct icp_qat_fw_loader_hal_handle {
 
 struct icp_qat_fw_loader_chip_info {
        bool sram_visible;
+       bool nn;
        bool fw_auth;
 };
 

diff --git a/drivers/crypto/qat/qat_common/qat_hal.c b/drivers/crypto/qat/qat_common/qat_hal.c
index 2faf863..e0d0ab4 100644 (file)
--- a/drivers/crypto/qat/qat_common/qat_hal.c
+++ b/drivers/crypto/qat/qat_common/qat_hal.c
@@ -603,7 +603,9 @@ static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle)
                qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val);
                csr_val = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);
                csr_val &= IGNORE_W1C_MASK;
-               csr_val |= CE_NN_MODE;
+               if (handle->chip_info->nn)
+                       csr_val |= CE_NN_MODE;
+
                qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, csr_val);
                qat_hal_wr_uwords(handle, ae, 0, ARRAY_SIZE(inst),
                                  (u64 *)inst);
@@ -665,10 +667,12 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
        case PCI_DEVICE_ID_INTEL_QAT_C62X:
        case PCI_DEVICE_ID_INTEL_QAT_C3XXX:
                handle->chip_info->sram_visible = false;
+               handle->chip_info->nn = true;
                handle->chip_info->fw_auth = true;
                break;
        case PCI_DEVICE_ID_INTEL_QAT_DH895XCC:
                handle->chip_info->sram_visible = true;
+               handle->chip_info->nn = true;
                handle->chip_info->fw_auth = false;
                break;
        default:
@@ -1433,6 +1437,11 @@ int qat_hal_init_nn(struct icp_qat_fw_loader_handle *handle,
 {
        int stat = 0;
        unsigned char ctx;
+       if (!handle->chip_info->nn) {
+               dev_err(&handle->pci_dev->dev, "QAT: No next neigh in 0x%x\n",
+                       handle->pci_dev->device);
+               return -EINVAL;
+       }
 
        if (ctx_mask == 0)
                return -EINVAL;

diff --git a/drivers/crypto/qat/qat_common/qat_uclo.c b/drivers/crypto/qat/qat_common/qat_uclo.c
index 5774916..fce0758 100644 (file)
--- a/drivers/crypto/qat/qat_common/qat_uclo.c
+++ b/drivers/crypto/qat/qat_common/qat_uclo.c
@@ -884,11 +884,13 @@ static int qat_hal_set_modes(struct icp_qat_fw_loader_handle *handle,
                pr_err("QAT: qat_hal_set_ae_ctx_mode error\n");
                return ret;
        }
-       mode = ICP_QAT_NN_MODE(uof_image->ae_mode);
-       ret = qat_hal_set_ae_nn_mode(handle, ae, mode);
-       if (ret) {
-               pr_err("QAT: qat_hal_set_ae_nn_mode error\n");
-               return ret;
+       if (handle->chip_info->nn) {
+               mode = ICP_QAT_NN_MODE(uof_image->ae_mode);
+               ret = qat_hal_set_ae_nn_mode(handle, ae, mode);
+               if (ret) {
+                       pr_err("QAT: qat_hal_set_ae_nn_mode error\n");
+                       return ret;
+               }
        }
        mode = ICP_QAT_LOC_MEM0_MODE(uof_image->ae_mode);
        ret = qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM0, mode);