The IRQSTAT register is a W1C register used by the interrupt handler and
may have its BUSY bit changed. This makes it somewhat unreliable for the
polling devready function. So switch it over to use the BUSY bit in the
STAT register that always reflects the current state of the hardware.
This fixes driver hangs seen when the NAND flash is under heavy system
load (like I/O benchmarks).
Signed-off-by: Barry Song <barry.song@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
*/
static int bf5xx_nand_devready(struct mtd_info *mtd)
{
- unsigned short val = bfin_read_NFC_IRQSTAT();
+ unsigned short val = bfin_read_NFC_STAT();
- if ((val & NBUSYIRQ) == NBUSYIRQ)
+ if ((val & NBUSY) == NBUSY)
return 1;
else
return 0;