KVM: PPC: Book3S HV: Don't access XIVE PIPR register using byte accesses

The XIVE interrupt controller on POWER9 machines doesn't support byte
accesses to any register in the thread management area other than the
CPPR (current processor priority register).  In particular, when
reading the PIPR (pending interrupt priority register), we need to
do a 32-bit or 64-bit load.

Cc: stable@vger.kernel.org # v4.13
Fixes: 2c4fb78f78b6 ("KVM: PPC: Book3S HV: Workaround POWER9 DD1.0 bug causing IPB bit loss")
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

diff --git a/arch/powerpc/kvm/book3s_hv_rm_xive.c b/arch/powerpc/kvm/book3s_hv_rm_xive.c
index abf5f01..5b81a80 100644 (file)
--- a/arch/powerpc/kvm/book3s_hv_rm_xive.c
+++ b/arch/powerpc/kvm/book3s_hv_rm_xive.c
@@ -38,7 +38,6 @@ static inline void __iomem *get_tima_phys(void)
 #define __x_tima               get_tima_phys()
 #define __x_eoi_page(xd)       ((void __iomem *)((xd)->eoi_page))
 #define __x_trig_page(xd)      ((void __iomem *)((xd)->trig_page))
-#define __x_readb      __raw_rm_readb
 #define __x_writeb     __raw_rm_writeb
 #define __x_readw      __raw_rm_readw
 #define __x_readq      __raw_rm_readq

diff --git a/arch/powerpc/kvm/book3s_xive.c b/arch/powerpc/kvm/book3s_xive.c
index 08b200a..1330462 100644 (file)
--- a/arch/powerpc/kvm/book3s_xive.c
+++ b/arch/powerpc/kvm/book3s_xive.c
@@ -48,7 +48,6 @@
 #define __x_tima               xive_tima
 #define __x_eoi_page(xd)       ((void __iomem *)((xd)->eoi_mmio))
 #define __x_trig_page(xd)      ((void __iomem *)((xd)->trig_mmio))
-#define __x_readb      __raw_readb
 #define __x_writeb     __raw_writeb
 #define __x_readw      __raw_readw
 #define __x_readq      __raw_readq

diff --git a/arch/powerpc/kvm/book3s_xive_template.c b/arch/powerpc/kvm/book3s_xive_template.c
index d1ed2c4..c7a5dea 100644 (file)
--- a/arch/powerpc/kvm/book3s_xive_template.c
+++ b/arch/powerpc/kvm/book3s_xive_template.c
@@ -28,7 +28,8 @@ static void GLUE(X_PFX,ack_pending)(struct kvmppc_xive_vcpu *xc)
         * bit.
         */
        if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
-               u8 pipr = __x_readb(__x_tima + TM_QW1_OS + TM_PIPR);
+               __be64 qw1 = __x_readq(__x_tima + TM_QW1_OS);
+               u8 pipr = be64_to_cpu(qw1) & 0xff;
                if (pipr >= xc->hw_cppr)
                        return;
        }
@@ -336,7 +337,6 @@ X_STATIC unsigned long GLUE(X_PFX,h_ipoll)(struct kvm_vcpu *vcpu, unsigned long
        struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;
        u8 pending = xc->pending;
        u32 hirq;
-       u8 pipr;
 
        pr_devel("H_IPOLL(server=%ld)\n", server);
 
@@ -353,7 +353,8 @@ X_STATIC unsigned long GLUE(X_PFX,h_ipoll)(struct kvm_vcpu *vcpu, unsigned long
                pending = 0xff;
        } else {
                /* Grab pending interrupt if any */
-               pipr = __x_readb(__x_tima + TM_QW1_OS + TM_PIPR);
+               __be64 qw1 = __x_readq(__x_tima + TM_QW1_OS);
+               u8 pipr = be64_to_cpu(qw1) & 0xff;
                if (pipr < 8)
                        pending |= 1 << pipr;
        }