The mask is based on the format, which can be at most 32-bits per channel. So if
we have 64-bit loads/stores we're still using a 32-bit format with double the
bits set in the mask. This will fix validation fails with spilling.
No shader-db changes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
static unsigned
agx_pack_memory_reg(agx_index index, bool *flag)
{
- assert(index.size == AGX_SIZE_16 || index.size == AGX_SIZE_32);
assert_register_is_aligned(index);
- *flag = (index.size == AGX_SIZE_32);
+ *flag = (index.size >= AGX_SIZE_32);
return index.value;
}
case AGX_OPCODE_DEVICE_LOAD:
case AGX_OPCODE_LOCAL_LOAD:
case AGX_OPCODE_LD_TILE:
- return util_bitcount(I->mask) * size;
+ /* Can write 16-bit or 32-bit. Anything logically 64-bit is already
+ * expanded to 32-bit in the mask.
+ */
+ return util_bitcount(I->mask) * MIN2(size, 2);
case AGX_OPCODE_LDCF:
return 6;
case AGX_OPCODE_DEVICE_STORE:
case AGX_OPCODE_LOCAL_STORE:
case AGX_OPCODE_ST_TILE:
+ /* See agx_write_registers */
if (s == 0)
- return util_bitcount(I->mask) * size;
+ return util_bitcount(I->mask) * MIN2(size, 2);
else
return size;