amd: split GFX1103 into GFX1103_R1 and GFX1103_R2
authorMarek Olšák <marek.olsak@amd.com>
Tue, 24 Jan 2023 08:00:38 +0000 (03:00 -0500)
committerEric Engestrom <eric@engestrom.ch>
Wed, 8 Feb 2023 20:34:43 +0000 (20:34 +0000)
Fixes: caa09f66ae4 - amd: add chip identification for gfx1100-1103

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
(cherry picked from commit 84d59cdb5971424a4297e288b852c8cc15c46163)

.pick_status.json
src/amd/addrlib/src/amdgpu_asic_addr.h
src/amd/addrlib/src/gfx11/gfx11addrlib.cpp
src/amd/common/ac_gpu_info.c
src/amd/common/amd_family.c
src/amd/common/amd_family.h
src/amd/llvm/ac_llvm_util.c
src/gallium/drivers/radeonsi/radeon_vcn_dec.c
src/gallium/drivers/radeonsi/si_state_shaders.cpp

index 7316836..635eec3 100644 (file)
         "description": "amd: split GFX1103 into GFX1103_R1 and GFX1103_R2",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "caa09f66ae4e97972ec9609896b4ad64a9c9d115"
     },
index 36d39e5..34c16e2 100644 (file)
 #define AMDGPU_GFX1101_RANGE    0x20, 0xFF //# 32 <= x < 255
 #define AMDGPU_GFX1102_RANGE    0x10, 0x20 //# 16 <= x < 32
 
-#define AMDGPU_GFX1103_RANGE    0x01, 0xFF //# 1 <= x < max
+#define AMDGPU_GFX1103_R1_RANGE 0x01, 0x10 //# 1 <= x < 16
+#define AMDGPU_GFX1103_R2_RANGE 0x80, 0xFF //# 128 <= x < max
 
 #define AMDGPU_REMBRANDT_RANGE  0x01, 0xFF //# 01 <= x < 255
 
 #define ASICREV_IS_GFX1100(r)          ASICREV_IS(r, GFX1100)
 #define ASICREV_IS_GFX1101(r)          ASICREV_IS(r, GFX1101)
 #define ASICREV_IS_GFX1102(r)          ASICREV_IS(r, GFX1102)
-#define ASICREV_IS_GFX1103(r)          ASICREV_IS(r, GFX1103)
+#define ASICREV_IS_GFX1103_R1(r)       ASICREV_IS(r, GFX1103_R1)
+#define ASICREV_IS_GFX1103_R2(r)       ASICREV_IS(r, GFX1103_R2)
 
 #define ASICREV_IS_REMBRANDT(r)        ASICREV_IS(r, REMBRANDT)
 
index 9adc28a..af48e77 100644 (file)
@@ -752,9 +752,6 @@ ChipFamily Gfx11Lib::HwlConvertChipFamily(
             }
             break;
         case FAMILY_GFX1103:
-            if (ASICREV_IS_GFX1103(chipRevision))
-            {
-            }
             break;
         default:
             ADDR_ASSERT(!"Unknown chip family");
index 2745a2c..397130f 100644 (file)
@@ -834,7 +834,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info)
       identify_chip(GFX1102);
       break;
    case FAMILY_GFX1103:
-      identify_chip(GFX1103);
+      identify_chip(GFX1103_R1);
+      identify_chip(GFX1103_R2);
       break;
    }
 
index be65757..90ec21c 100644 (file)
@@ -108,8 +108,10 @@ const char *ac_get_family_name(enum radeon_family family)
       return "GFX1101";
    case CHIP_GFX1102:
       return "GFX1102";
-   case CHIP_GFX1103:
-      return "GFX1103";
+   case CHIP_GFX1103_R1:
+      return "GFX1103_R1";
+   case CHIP_GFX1103_R2:
+      return "GFX1103_R2";
    default:
       unreachable("Unknown GPU family");
    }
index 67e6ee2..fa2852a 100644 (file)
@@ -131,7 +131,8 @@ enum radeon_family
    CHIP_GFX1100,
    CHIP_GFX1101,
    CHIP_GFX1102,
-   CHIP_GFX1103,
+   CHIP_GFX1103_R1,
+   CHIP_GFX1103_R2,
    CHIP_LAST,
 };
 
index bfd9ec7..558456b 100644 (file)
@@ -183,7 +183,8 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
       return "gfx1101";
    case CHIP_GFX1102:
       return "gfx1102";
-   case CHIP_GFX1103:
+   case CHIP_GFX1103_R1:
+   case CHIP_GFX1103_R2:
       return "gfx1103";
    default:
       return "";
index 414a8d6..3bdcc7d 100644 (file)
@@ -3160,7 +3160,8 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
    case CHIP_GFX1100:
    case CHIP_GFX1101:
    case CHIP_GFX1102:
-   case CHIP_GFX1103:
+   case CHIP_GFX1103_R1:
+   case CHIP_GFX1103_R2:
       dec->jpg.direct_reg = true;
       dec->addr_gfx_mode = RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX11;
       dec->av1_version = RDECODE_AV1_VER_1;
index 1601234..a52bd78 100644 (file)
@@ -673,7 +673,7 @@ unsigned si_get_shader_prefetch_size(struct si_shader *shader)
    /* Return 0 for some A0 chips only. Other chips don't need it. */
    if ((shader->selector->screen->info.family == CHIP_GFX1100 ||
         shader->selector->screen->info.family == CHIP_GFX1102 ||
-        shader->selector->screen->info.family == CHIP_GFX1103) &&
+        shader->selector->screen->info.family == CHIP_GFX1103_R1) &&
        shader->selector->screen->info.chip_rev == 0)
       return 0;