powerpc/mpc85xx: Workaround for A-005812

Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can
result in invalid atomic operations. For u-boot, this erratum only impacts
SoCs running in write shadow mode.

Signed-off-by: York Sun <yorksun@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 5cd02cc..cbb443f 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -245,6 +245,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
        puts("Work-around for Erratum A006593 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
+       puts("Work-around for Erratum A-005812 enabled\n");
+#endif
        return 0;
 }
 

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 1774462..48b3826 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -399,6 +399,14 @@ int cpu_init_r(void)
                sync();
        }
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
+       /*
+        * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
+        * in write shadow mode. Checking DCWS before setting SPR 976.
+        */
+       if (mfspr(L1CSR2) & L1CSR2_DCWS)
+               mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
+#endif
 
 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
        spin = getenv("spin_table_compat");

diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 15bbbc1..c15e83b 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -226,6 +226,21 @@ __secondary_start_page:
 2:
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
+       /*
+        * A-005812 workaround sets bit 32 of SPR 976 for SoCs running in
+        * write shadow mode. This code should run after other code setting
+        * DCWS.
+        */
+       mfspr   r3,L1CSR2
+       andis.  r3,r3,(L1CSR2_DCWS)@h
+       beq     1f
+       mfspr   r3, SPRN_HDBCR0
+       oris    r3, r3, 0x8000
+       mtspr   SPRN_HDBCR0, r3
+1:
+#endif
+
 #ifdef CONFIG_BACKSIDE_L2_CACHE
        /* skip L2 setup on P2040/P2040E as they have no L2 */
        mfspr   r3,SPRN_SVR

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index c3a3760..91fda7e 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -368,6 +368,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ERRATUM_A005812
 
 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -413,6 +414,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004849
 #define CONFIG_SYS_FSL_ERRATUM_A004580
 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
+#define CONFIG_SYS_FSL_ERRATUM_A005812
 
 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
 #define CONFIG_SYS_PPC64               /* 64-bit core */
@@ -474,6 +476,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CONFIG_SYS_FSL_ERRATUM_A005812
 
 #elif defined(CONFIG_BSC9131)
 #define CONFIG_MAX_CPUS                        1