cl::value_desc("0|1|2"),
cl::init(0), cl::Hidden);
+// Threshold to keep compile time reasonable.
+static cl::opt<unsigned> VRegThresh("amdgpu-regbanks-reassign-threshold",
+ cl::desc("Max number of vregs to run the regbanks reassign pass"),
+ cl::init(100000), cl::Hidden);
+
#define DEBUG_TYPE "amdgpu-regbanks-reassign"
#define NUM_VGPR_BANKS 4
return false;
MRI = &MF.getRegInfo();
+
+ LLVM_DEBUG(dbgs() << "=== RegBanks reassign analysis on function " << MF.getName()
+ << "\nNumVirtRegs = " << MRI->getNumVirtRegs() << "\n\n");
+
+ if (MRI->getNumVirtRegs() > VRegThresh) {
+ LLVM_DEBUG(dbgs() << "NumVirtRegs > " << VRegThresh
+ << " threshold, skipping function.\n\n");
+ return false;
+ }
+
TRI = ST->getRegisterInfo();
MLI = &getAnalysis<MachineLoopInfo>();
VRM = &getAnalysis<VirtRegMap>();
AMDGPU::SReg_32RegClass.getNumRegs() / 2 + 1;
RegsUsed.resize(NumRegBanks);
- LLVM_DEBUG(dbgs() << "=== RegBanks reassign analysis on function " << MF.getName()
- << '\n');
-
unsigned StallCycles = collectCandidates(MF);
NumStallsDetected += StallCycles;