/// Adds all live-in registers of basic block @p MBB.
/// Live in registers are the registers in the blocks live-in list and the
/// pristine registers.
- void addLiveIns(const MachineBasicBlock *MBB);
+ void addLiveIns(const MachineBasicBlock &MBB);
/// Adds all live-out registers of basic block @p MBB.
/// Live out registers are the union of the live-in registers of the successor
/// blocks and pristine registers. Live out registers of the end block are the
/// callee saved registers.
- void addLiveOuts(const MachineBasicBlock *MBB);
+ void addLiveOuts(const MachineBasicBlock &MBB);
/// Like addLiveOuts() but does not add pristine registers/callee saved
/// registers.
- void addLiveOutsNoPristines(const MachineBasicBlock *MBB);
+ void addLiveOutsNoPristines(const MachineBasicBlock &MBB);
typedef SparseSet<unsigned>::const_iterator const_iterator;
const_iterator begin() const { return LiveRegs.begin(); }
LiveRegSet.init(TRI);
// We do not need to care about pristine registers as they are just preserved
// but not actually used in the function.
- LiveRegSet.addLiveOutsNoPristines(MBB);
+ LiveRegSet.addLiveOutsNoPristines(*MBB);
MachineInstr *UndefMI = UndefReads.back().first;
unsigned OpIdx = UndefReads.back().second;
// Initialize liveins to the first BB. These are potentiall redefined by
// predicated instructions.
Redefs.init(TRI);
- Redefs.addLiveIns(CvtBBI->BB);
- Redefs.addLiveIns(NextBBI->BB);
+ Redefs.addLiveIns(*CvtBBI->BB);
+ Redefs.addLiveIns(*NextBBI->BB);
// Compute a set of registers which must not be killed by instructions in
// BB1: This is everything live-in to BB2.
DontKill.init(TRI);
- DontKill.addLiveIns(NextBBI->BB);
+ DontKill.addLiveIns(*NextBBI->BB);
if (CvtBBI->BB->pred_size() > 1) {
BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
// Initialize liveins to the first BB. These are potentially redefined by
// predicated instructions.
Redefs.init(TRI);
- Redefs.addLiveIns(CvtBBI->BB);
- Redefs.addLiveIns(NextBBI->BB);
+ Redefs.addLiveIns(*CvtBBI->BB);
+ Redefs.addLiveIns(*NextBBI->BB);
DontKill.clear();
// Initialize liveins to the first BB. These are potentially redefined by
// predicated instructions.
Redefs.init(TRI);
- Redefs.addLiveIns(BBI1->BB);
+ Redefs.addLiveIns(*BBI1->BB);
// Remove the duplicated instructions at the beginnings of both paths.
// Skip dbg_value instructions
LiveRegs.removeReg(Info.getReg());
}
-void LivePhysRegs::addLiveOutsNoPristines(const MachineBasicBlock *MBB) {
+void LivePhysRegs::addLiveOutsNoPristines(const MachineBasicBlock &MBB) {
// To get the live-outs we simply merge the live-ins of all successors.
- for (const MachineBasicBlock *Succ : MBB->successors())
+ for (const MachineBasicBlock *Succ : MBB.successors())
::addLiveIns(*this, *Succ);
}
-void LivePhysRegs::addLiveOuts(const MachineBasicBlock *MBB) {
- const MachineFunction &MF = *MBB->getParent();
+void LivePhysRegs::addLiveOuts(const MachineBasicBlock &MBB) {
+ const MachineFunction &MF = *MBB.getParent();
const MachineFrameInfo &MFI = *MF.getFrameInfo();
if (MFI.isCalleeSavedInfoValid()) {
addPristines(*this, MF, MFI, *TRI);
- if (MBB->isReturnBlock()) {
+ if (MBB.isReturnBlock()) {
// The return block has no successors whose live-ins we could merge
// below. So instead we add the callee saved registers manually.
for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I)
addLiveOutsNoPristines(MBB);
}
-void LivePhysRegs::addLiveIns(const MachineBasicBlock *MBB) {
- const MachineFunction &MF = *MBB->getParent();
+void LivePhysRegs::addLiveIns(const MachineBasicBlock &MBB) {
+ const MachineFunction &MF = *MBB.getParent();
const MachineFrameInfo &MFI = *MF.getFrameInfo();
if (MFI.isCalleeSavedInfoValid())
addPristines(*this, MF, MFI, *TRI);
- ::addLiveIns(*this, *MBB);
+ ::addLiveIns(*this, MBB);
}
DEBUG(dbgs() << "****** BB " << MBB.getName() << " ******\n");
LiveRegs.init(TRI);
// FIXME: This should probably be addLiveOuts().
- LiveRegs.addLiveOutsNoPristines(&MBB);
+ LiveRegs.addLiveOutsNoPristines(MBB);
bool HasStackMap = false;
// Reverse iterate over all instructions and add the current live register
// set to an instruction if we encounter a patchpoint instruction.
MachineOperand &New = MI.getOperand(4);
LivePhysRegs LiveRegs(&TII->getRegisterInfo());
- LiveRegs.addLiveOuts(&MBB);
+ LiveRegs.addLiveOuts(MBB);
for (auto I = std::prev(MBB.end()); I != MBBI; --I)
LiveRegs.stepBackward(*I);
MachineOperand &NewHi = MI.getOperand(7);
LivePhysRegs LiveRegs(&TII->getRegisterInfo());
- LiveRegs.addLiveOuts(&MBB);
+ LiveRegs.addLiveOuts(MBB);
for (auto I = std::prev(MBB.end()); I != MBBI; --I)
LiveRegs.stepBackward(*I);
MachineOperand &New = MI.getOperand(4);
LivePhysRegs LiveRegs(&TII->getRegisterInfo());
- LiveRegs.addLiveOuts(&MBB);
+ LiveRegs.addLiveOuts(MBB);
for (auto I = std::prev(MBB.end()); I != MBBI; --I)
LiveRegs.stepBackward(*I);
unsigned DesiredHi = TRI->getSubReg(Desired.getReg(), ARM::gsub_1);
LivePhysRegs LiveRegs(&TII->getRegisterInfo());
- LiveRegs.addLiveOuts(&MBB);
+ LiveRegs.addLiveOuts(MBB);
for (auto I = std::prev(MBB.end()); I != MBBI; --I)
LiveRegs.stepBackward(*I);
// Initialize if we never queried in this block.
if (!LiveRegsValid) {
LiveRegs.init(TRI);
- LiveRegs.addLiveOuts(&MBB);
+ LiveRegs.addLiveOuts(MBB);
LiveRegPos = MBB.end();
LiveRegsValid = true;
}
// Look for a temporary register to use.
// First, compute the liveness information.
LivePhysRegs UsedRegs(STI.getRegisterInfo());
- UsedRegs.addLiveOuts(&MBB);
+ UsedRegs.addLiveOuts(MBB);
// The semantic of pristines changed recently and now,
// the callee-saved registers that are touched in the function
// are not part of the pristines set anymore.
// Set up the set of live registers at the end of MBB (live out)
LiveRegs.clear();
- LiveRegs.addLiveOuts(&MBB);
+ LiveRegs.addLiveOuts(MBB);
// Iterate backwards through the block looking for instructions to change.
for (auto MBBI = MBB.rbegin(), MBBE = MBB.rend(); MBBI != MBBE; ++MBBI) {
// to update this for each instruction.
LiveRegs.clear();
// We run after PEI, so we need to AddPristinesAndCSRs.
- LiveRegs.addLiveOuts(&MBB);
+ LiveRegs.addLiveOuts(MBB);
for (auto I = MBB.rbegin(); I != MBB.rend(); ++I) {
MachineInstr *NewMI = nullptr;
MBB.getParent()->getSubtarget().getRegisterInfo();
LivePhysRegs LPR(TRI);
- LPR.addLiveOuts(&MBB);
+ LPR.addLiveOuts(MBB);
for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
I != E; ++I) {
// as this is usually wrong to read an undef value.
if (MachineBasicBlock::LQR_Unknown == LQR) {
LivePhysRegs LPR(&getRegisterInfo());
- LPR.addLiveOuts(&MBB);
+ LPR.addLiveOuts(MBB);
MachineBasicBlock::iterator I = MBB.end();
while (I != MI) {
--I;