setOperationAction(ISD::SRA, VT, Custom);
setOperationAction(ISD::SHL, VT, Custom);
setOperationAction(ISD::SRL, VT, Custom);
+
+ setOperationAction(ISD::BR_CC, VT, Expand);
+ setOperationAction(ISD::SELECT_CC, VT, Expand);
}
// Types natively supported:
setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
+
if (UseHVX) {
if (UseHVXSgl) {
setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8, Custom);
}
// Should we expand the build vector with shuffles?
-bool
-HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
- unsigned DefinedValues) const {
+bool HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
+ unsigned DefinedValues) const {
// Hexagon vector shuffle operates on element sizes of bytes or halfwords
EVT EltVT = VT.getVectorElementType();
int EltBits = EltVT.getSizeInBits();
return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
}
-static StridedLoadKind isStridedLoad(ArrayRef<int> &Mask) {
+static StridedLoadKind isStridedLoad(const ArrayRef<int> &Mask) {
int even_start = -2;
int odd_start = -1;
size_t mask_len = Mask.size();
return StridedLoadKind::NoPattern;
}
+bool HexagonTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
+ EVT VT) const {
+ if (Subtarget.useHVXOps())
+ return isStridedLoad(Mask) != StridedLoadKind::NoPattern;
+ return true;
+}
+
// Lower a vector shuffle (V1, V2, V3). V1 and V2 are the two vectors
// to select data from, V3 is the permutation.
SDValue
bool shouldExpandBuildVectorWithShuffles(EVT VT,
unsigned DefinedValues) const override;
+ bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, EVT VT)
+ const override;
+
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
const char *getTargetNodeName(unsigned Opcode) const override;
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
--- /dev/null
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; Check that we don't crash.
+; CHECK: vshuff
+
+target triple = "hexagon"
+
+define void @hex_interleaved.s0.__outermost() local_unnamed_addr #0 {
+entry:
+ %0 = icmp eq i32 undef, 0
+ %sel2 = select i1 %0, <32 x i16> undef, <32 x i16> zeroinitializer
+ %1 = bitcast <32 x i16> %sel2 to <16 x i32>
+ %2 = tail call <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32> %1)
+ store <16 x i32> %2, <16 x i32>* undef, align 2
+ unreachable
+}
+
+; Function Attrs: nounwind readnone
+declare <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32>) #1
+
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }
+attributes #1 = { nounwind readnone }