arm64: tegra: Fix order of XUSB controller clocks

This is purely to make the json-schema validation tools happy because
they cannot deal with string arrays that may be in arbitrary order.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index c0efa19..f4e0cc2 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -997,8 +997,8 @@
                         <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
                         <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
                         <&tegra_car TEGRA210_CLK_XUSB_SS>,
-                        <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
                         <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
+                        <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
                         <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
                         <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
                         <&tegra_car TEGRA210_CLK_PLL_U_480M>,
@@ -1006,7 +1006,7 @@
                         <&tegra_car TEGRA210_CLK_PLL_E>;
                clock-names = "xusb_host", "xusb_host_src",
                              "xusb_falcon_src", "xusb_ss",
-                             "xusb_ss_div2", "xusb_ss_src",
+                             "xusb_ss_src", "xusb_ss_div2",
                              "xusb_hs_src", "xusb_fs_src",
                              "pll_u_480m", "clk_m", "pll_e";
                resets = <&tegra_car 89>, <&tegra_car 156>,