ARM: dts: uniphier: Set SCSSI clock and reset IDs for each channel

Currently common clock and reset IDs were used, however, each clock and
reset ID should be used for each channel.

Pro5 and PXs2 are affected by this fix, but the SCSSI clock gate of Pro5 is
common to all channels.

Fixes: 92fa4f4cc2cd ("ARM: dts: uniphier: add SPI node for UniPhier 32bit SoCs")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index 36e4f31..8f1ae09 100644 (file)
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -174,8 +174,8 @@
                        interrupts = <0 216 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_spi1>;
-                       clocks = <&peri_clk 11>;
-                       resets = <&peri_rst 11>;
+                       clocks = <&peri_clk 11>;        /* common with spi0 */
+                       resets = <&peri_rst 12>;
                };
 
                serial0: serial@54006800 {

diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 7044f87..2f2a249 100644 (file)
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -187,8 +187,8 @@
                        interrupts = <0 216 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_spi1>;
-                       clocks = <&peri_clk 11>;
-                       resets = <&peri_rst 11>;
+                       clocks = <&peri_clk 12>;
+                       resets = <&peri_rst 12>;
                };
 
                serial0: serial@54006800 {