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raw | patch | inline | side by side (parent: d452f27)
move data structure out of cpu.h
authorYork Sun <york.sun@nxp.com>
Mon, 5 Nov 2018 18:01:06 +0000 (18:01 +0000)
committerYork Sun <york.sun@nxp.com>
Tue, 4 Dec 2018 16:30:23 +0000 (08:30 -0800)
Move static definitions to cpu.c file, as it doesn't allow
the cpu.h file to be included in multiple c files.

Signed-off-by: York Sun <york.sun@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/cpu.c patch | blob | history
arch/arm/include/asm/arch-fsl-layerscape/cpu.h patch | blob | history

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index be00bd55ab68906d1132cb8e31d15b865bacb20f..e01b029d64424952cce99e03052f7eaa1ab088a7 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -33,6 +33,303 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct cpu_type cpu_type_list[] = {
+       CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
+       CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
+       CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
+       CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
+       CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
+       CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
+       CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
+       CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
+       CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
+       CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
+       CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
+       CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
+       CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
+       CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
+       CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+       CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
+       CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
+       CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
+       CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
+};
+
+#define EARLY_PGTABLE_SIZE 0x5000
+static struct mm_region early_map[] = {
+#ifdef CONFIG_FSL_LSCH3
+       { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+         CONFIG_SYS_FSL_CCSR_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+         SYS_FSL_OCRAM_SPACE_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+       },
+       { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+         CONFIG_SYS_FSL_QSPI_SIZE1,
+         PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
+#ifdef CONFIG_FSL_IFC
+       /* For IFC Region #1, only the first 4MB is cache-enabled */
+       { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
+         CONFIG_SYS_FSL_IFC_SIZE1_1,
+         PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+       },
+       { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+         CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+         CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+       },
+       { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
+         CONFIG_SYS_FSL_IFC_SIZE1,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+       },
+#endif
+       { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+         CONFIG_SYS_FSL_DRAM_SIZE1,
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+#else  /* Start with nGnRnE and PXN and UXN to prevent speculative access */
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+#endif
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+       },
+#ifdef CONFIG_FSL_IFC
+       /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
+       { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+         CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+       },
+#endif
+       { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+         CONFIG_SYS_FSL_DCSR_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+         CONFIG_SYS_FSL_DRAM_SIZE2,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+       },
+#elif defined(CONFIG_FSL_LSCH2)
+       { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+         CONFIG_SYS_FSL_CCSR_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+         SYS_FSL_OCRAM_SPACE_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+       },
+       { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+         CONFIG_SYS_FSL_DCSR_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+         CONFIG_SYS_FSL_QSPI_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+       },
+#ifdef CONFIG_FSL_IFC
+       { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
+         CONFIG_SYS_FSL_IFC_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+       },
+#endif
+       { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+         CONFIG_SYS_FSL_DRAM_SIZE1,
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+#else  /* Start with nGnRnE and PXN and UXN to prevent speculative access */
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+#endif
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+       },
+       { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+         CONFIG_SYS_FSL_DRAM_SIZE2,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+       },
+#endif
+       {},     /* list terminator */
+};
+
+static struct mm_region final_map[] = {
+#ifdef CONFIG_FSL_LSCH3
+       { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+         CONFIG_SYS_FSL_CCSR_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+         SYS_FSL_OCRAM_SPACE_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+       },
+       { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+         CONFIG_SYS_FSL_DRAM_SIZE1,
+         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+       },
+       { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+         CONFIG_SYS_FSL_QSPI_SIZE1,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
+         CONFIG_SYS_FSL_QSPI_SIZE2,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+#ifdef CONFIG_FSL_IFC
+       { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+         CONFIG_SYS_FSL_IFC_SIZE2,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+#endif
+       { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+         CONFIG_SYS_FSL_DCSR_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
+         CONFIG_SYS_FSL_MC_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
+         CONFIG_SYS_FSL_NI_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       /* For QBMAN portal, only the first 64MB is cache-enabled */
+       { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
+         CONFIG_SYS_FSL_QBMAN_SIZE_1,
+         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
+       },
+       { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
+         CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
+         CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
+         CONFIG_SYS_PCIE1_PHYS_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
+         CONFIG_SYS_PCIE2_PHYS_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
+         CONFIG_SYS_PCIE3_PHYS_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+#ifdef CONFIG_ARCH_LS2080A
+       { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
+         CONFIG_SYS_PCIE4_PHYS_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+#endif
+       { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
+         CONFIG_SYS_FSL_WRIOP1_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
+         CONFIG_SYS_FSL_AIOP1_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
+         CONFIG_SYS_FSL_PEBUF_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+         CONFIG_SYS_FSL_DRAM_SIZE2,
+         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+       },
+#elif defined(CONFIG_FSL_LSCH2)
+       { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
+         CONFIG_SYS_FSL_BOOTROM_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+         CONFIG_SYS_FSL_CCSR_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+         SYS_FSL_OCRAM_SPACE_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+       },
+       { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+         CONFIG_SYS_FSL_DCSR_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+         CONFIG_SYS_FSL_QSPI_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+#ifdef CONFIG_FSL_IFC
+       { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
+         CONFIG_SYS_FSL_IFC_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+       },
+#endif
+       { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+         CONFIG_SYS_FSL_DRAM_SIZE1,
+         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+       },
+       { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
+         CONFIG_SYS_FSL_QBMAN_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+         CONFIG_SYS_FSL_DRAM_SIZE2,
+         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+       },
+       { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
+         CONFIG_SYS_PCIE1_PHYS_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
+         CONFIG_SYS_PCIE2_PHYS_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
+         CONFIG_SYS_PCIE3_PHYS_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+       { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
+         CONFIG_SYS_FSL_DRAM_SIZE3,
+         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+       },
+#endif
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+       {},     /* space holder for secure mem */
+#endif
+       {},
+};
+
 struct mm_region *mem_map = early_map;
 
 void cpu_name(char *name)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 48d0ab163a8325921ddfe2fb5b2cbb21adf5ae38..3926aa30397303ba504e6ad0020c752bb2604b42 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -7,30 +7,6 @@
 #ifndef _FSL_LAYERSCAPE_CPU_H
 #define _FSL_LAYERSCAPE_CPU_H
 
-static struct cpu_type cpu_type_list[] = {
-       CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
-       CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
-       CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
-       CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
-       CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
-       CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
-       CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
-       CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
-       CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
-       CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
-       CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
-       CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
-       CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
-       CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
-       CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
-       CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
-       CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
-       CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
-       CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
-};
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-
 #ifdef CONFIG_FSL_LSCH3
 #define CONFIG_SYS_FSL_CCSR_BASE       0x00000000
 #define CONFIG_SYS_FSL_CCSR_SIZE       0x10000000
@@ -90,282 +66,6 @@ static struct cpu_type cpu_type_list[] = {
 #define CONFIG_SYS_FSL_DRAM_SIZE3      0x7800000000    /* 480GB */
 #endif
 
-#define EARLY_PGTABLE_SIZE 0x5000
-static struct mm_region early_map[] = {
-#ifdef CONFIG_FSL_LSCH3
-       { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-         CONFIG_SYS_FSL_CCSR_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-         SYS_FSL_OCRAM_SPACE_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
-       },
-       { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
-         CONFIG_SYS_FSL_QSPI_SIZE1,
-         PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
-#ifdef CONFIG_FSL_IFC
-       /* For IFC Region #1, only the first 4MB is cache-enabled */
-       { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
-         CONFIG_SYS_FSL_IFC_SIZE1_1,
-         PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
-       },
-       { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
-         CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
-         CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
-       },
-       { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
-         CONFIG_SYS_FSL_IFC_SIZE1,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
-       },
-#endif
-       { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-         CONFIG_SYS_FSL_DRAM_SIZE1,
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-#else  /* Start with nGnRnE and PXN and UXN to prevent speculative access */
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
-#endif
-         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-       },
-#ifdef CONFIG_FSL_IFC
-       /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
-       { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
-         CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
-       },
-#endif
-       { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-         CONFIG_SYS_FSL_DCSR_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-         CONFIG_SYS_FSL_DRAM_SIZE2,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
-         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-       },
-#elif defined(CONFIG_FSL_LSCH2)
-       { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-         CONFIG_SYS_FSL_CCSR_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-         SYS_FSL_OCRAM_SPACE_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
-       },
-       { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-         CONFIG_SYS_FSL_DCSR_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
-         CONFIG_SYS_FSL_QSPI_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
-       },
-#ifdef CONFIG_FSL_IFC
-       { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
-         CONFIG_SYS_FSL_IFC_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
-       },
-#endif
-       { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-         CONFIG_SYS_FSL_DRAM_SIZE1,
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-#else  /* Start with nGnRnE and PXN and UXN to prevent speculative access */
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
-#endif
-         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-       },
-       { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-         CONFIG_SYS_FSL_DRAM_SIZE2,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
-         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-       },
-#endif
-       {},     /* list terminator */
-};
-
-static struct mm_region final_map[] = {
-#ifdef CONFIG_FSL_LSCH3
-       { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-         CONFIG_SYS_FSL_CCSR_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-         SYS_FSL_OCRAM_SPACE_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
-       },
-       { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-         CONFIG_SYS_FSL_DRAM_SIZE1,
-         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-       },
-       { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
-         CONFIG_SYS_FSL_QSPI_SIZE1,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
-         CONFIG_SYS_FSL_QSPI_SIZE2,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-#ifdef CONFIG_FSL_IFC
-       { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
-         CONFIG_SYS_FSL_IFC_SIZE2,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-#endif
-       { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-         CONFIG_SYS_FSL_DCSR_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
-         CONFIG_SYS_FSL_MC_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
-         CONFIG_SYS_FSL_NI_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       /* For QBMAN portal, only the first 64MB is cache-enabled */
-       { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
-         CONFIG_SYS_FSL_QBMAN_SIZE_1,
-         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
-       },
-       { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
-         CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
-         CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-         CONFIG_SYS_PCIE1_PHYS_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-         CONFIG_SYS_PCIE2_PHYS_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-         CONFIG_SYS_PCIE3_PHYS_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-#ifdef CONFIG_ARCH_LS2080A
-       { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
-         CONFIG_SYS_PCIE4_PHYS_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-#endif
-       { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
-         CONFIG_SYS_FSL_WRIOP1_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
-         CONFIG_SYS_FSL_AIOP1_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
-         CONFIG_SYS_FSL_PEBUF_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-         CONFIG_SYS_FSL_DRAM_SIZE2,
-         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-       },
-#elif defined(CONFIG_FSL_LSCH2)
-       { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
-         CONFIG_SYS_FSL_BOOTROM_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-         CONFIG_SYS_FSL_CCSR_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-         SYS_FSL_OCRAM_SPACE_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
-       },
-       { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-         CONFIG_SYS_FSL_DCSR_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
-         CONFIG_SYS_FSL_QSPI_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-#ifdef CONFIG_FSL_IFC
-       { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
-         CONFIG_SYS_FSL_IFC_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
-       },
-#endif
-       { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-         CONFIG_SYS_FSL_DRAM_SIZE1,
-         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-       },
-       { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
-         CONFIG_SYS_FSL_QBMAN_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-         CONFIG_SYS_FSL_DRAM_SIZE2,
-         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-       },
-       { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-         CONFIG_SYS_PCIE1_PHYS_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-         CONFIG_SYS_PCIE2_PHYS_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-         CONFIG_SYS_PCIE3_PHYS_SIZE,
-         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       },
-       { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
-         CONFIG_SYS_FSL_DRAM_SIZE3,
-         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
-       },
-#endif
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-       {},     /* space holder for secure mem */
-#endif
-       {},
-};
-#endif /* !CONFIG_SYS_DCACHE_OFF */
-
 int fsl_qoriq_core_to_cluster(unsigned int core);
 u32 cpu_mask(void);
 
Domain: System / Kernel;