#
VERSION_MAJOR = 0
VERSION_MINOR = 9
-VERSION_PATCH = 6
-EXTRAVERSION = +
+VERSION_PATCH = 7
+EXTRAVERSION =
MM_VERSION = $(VERSION_MAJOR).$(VERSION_MINOR)
VERSION = $(MM_VERSION).$(VERSION_PATCH)$(EXTRAVERSION)
CFLAGS += -DVERSION_MAJOR=$(VERSION_MAJOR) \
ASFLAGS += $(EXTRA_ASFLAGS)
LDFLAGS += $(EXTRA_LDFLAGS)
-# Embedded image(s), or default if not set
-#
-EMBEDDED_IMAGE = image/default.gpxe
-
# Inhibit -Werror if NO_WERROR is specified on make command line
#
ifneq ($(NO_WERROR),1)
}
/**
+ * Read IP address from iBFT (for debugging)
+ *
+ * @v strings iBFT string block descriptor
+ * @v string String field
+ * @ret ipaddr IP address string
+ */
+static const char * ibft_ipaddr ( struct ibft_ipaddr *ipaddr ) {
+ return inet_ntoa ( ipaddr->in );
+}
+
+/**
* Allocate a string within iBFT
*
* @v strings iBFT string block descriptor
}
/**
+ * Read string from iBFT (for debugging)
+ *
+ * @v strings iBFT string block descriptor
+ * @v string String field
+ * @ret data String content (or "<empty>")
+ */
+static const char * ibft_string ( struct ibft_string_block *strings,
+ struct ibft_string *string ) {
+ return ( ( ( char * ) strings->table ) + string->offset );
+}
+
+/**
* Fill in NIC portion of iBFT
*
* @v nic NIC portion of iBFT
/* Extract values from DHCP configuration */
ibft_set_ipaddr_option ( &nic->ip_address, &ip_setting );
+ DBG ( "iBFT NIC IP = %s\n", ibft_ipaddr ( &nic->ip_address ) );
ibft_set_ipaddr_option ( &nic->gateway, &gateway_setting );
+ DBG ( "iBFT NIC gateway = %s\n", ibft_ipaddr ( &nic->gateway ) );
ibft_set_ipaddr_option ( &nic->dns[0], &dns_setting );
+ DBG ( "iBFT NIC DNS = %s\n", ibft_ipaddr ( &nic->dns[0] ) );
if ( ( rc = ibft_set_string_option ( strings, &nic->hostname,
&hostname_setting ) ) != 0 )
return rc;
+ DBG ( "iBFT NIC hostname = %s\n",
+ ibft_string ( strings, &nic->hostname ) );
/* Derive subnet mask prefix from subnet mask */
fetch_ipv4_setting ( NULL, &netmask_setting, &netmask_addr );
netmask_addr.s_addr >>= 1;
}
nic->subnet_mask_prefix = netmask_count;
+ DBG ( "iBFT NIC subnet = /%d\n", nic->subnet_mask_prefix );
/* Extract values from net-device configuration */
memcpy ( nic->mac_address, netdev->ll_addr,
sizeof ( nic->mac_address ) );
+ DBG ( "iBFT NIC MAC = %s\n",
+ netdev->ll_protocol->ntoa ( nic->mac_address ) );
nic->pci_bus_dev_func = netdev->dev->desc.location;
+ DBG ( "iBFT NIC PCI = %04x\n", nic->pci_bus_dev_func );
return 0;
}
if ( ( rc = ibft_set_string ( strings, &initiator->initiator_name,
initiator_iqn ) ) != 0 )
return rc;
+ DBG ( "iBFT initiator hostname = %s\n",
+ ibft_string ( strings, &initiator->initiator_name ) );
return 0;
}
struct iscsi_session *iscsi ) {
int rc;
- if ( ! iscsi->initiator_username )
+ if ( ! ( iscsi->status & ISCSI_STATUS_AUTH_FORWARD_REQUIRED ) )
return 0;
+
+ assert ( iscsi->initiator_username );
assert ( iscsi->initiator_password );
target->chap_type = IBFT_CHAP_ONE_WAY;
if ( ( rc = ibft_set_string ( strings, &target->chap_name,
iscsi->initiator_username ) ) != 0 )
return rc;
+ DBG ( "iBFT target username = %s\n",
+ ibft_string ( strings, &target->chap_name ) );
if ( ( rc = ibft_set_string ( strings, &target->chap_secret,
iscsi->initiator_password ) ) != 0 )
return rc;
+ DBG ( "iBFT target password = <redacted>\n" );
+
return 0;
}
struct iscsi_session *iscsi ) {
int rc;
- if ( ! iscsi->target_username )
+ if ( ! ( iscsi->status & ISCSI_STATUS_AUTH_REVERSE_REQUIRED ) )
return 0;
- assert ( iscsi->target_password );
+
assert ( iscsi->initiator_username );
assert ( iscsi->initiator_password );
+ assert ( iscsi->target_username );
+ assert ( iscsi->target_password );
target->chap_type = IBFT_CHAP_MUTUAL;
if ( ( rc = ibft_set_string ( strings, &target->reverse_chap_name,
iscsi->target_username ) ) != 0 )
return rc;
+ DBG ( "iBFT target reverse username = %s\n",
+ ibft_string ( strings, &target->chap_name ) );
if ( ( rc = ibft_set_string ( strings, &target->reverse_chap_secret,
iscsi->target_password ) ) != 0 )
return rc;
+ DBG ( "iBFT target reverse password = <redacted>\n" );
+
return 0;
}
/* Fill in Target values */
ibft_set_ipaddr ( &target->ip_address, sin_target->sin_addr );
+ DBG ( "iBFT target IP = %s\n", ibft_ipaddr ( &target->ip_address ) );
target->socket = ntohs ( sin_target->sin_port );
+ DBG ( "iBFT target port = %d\n", target->socket );
if ( ( rc = ibft_set_string ( strings, &target->target_name,
iscsi->target_iqn ) ) != 0 )
return rc;
+ DBG ( "iBFT target name = %s\n",
+ ibft_string ( strings, &target->target_name ) );
if ( ( rc = ibft_fill_target_chap ( target, strings, iscsi ) ) != 0 )
return rc;
if ( ( rc = ibft_fill_target_reverse_chap ( target, strings,
* @ret rc Return status code
*/
int pxe_start_nbp ( void ) {
- int discard_b, discard_c;
+ int discard_b, discard_c, discard_d, discard_D;
uint16_t rc;
/* Far call to PXE NBP */
- __asm__ __volatile__ ( REAL_CODE ( "pushw %%cx\n\t"
- "pushw %%ax\n\t"
- "movw %%cx, %%es\n\t"
+ __asm__ __volatile__ ( REAL_CODE ( "movw %%cx, %%es\n\t"
+ "pushw %%es\n\t"
+ "pushw %%di\n\t"
"sti\n\t"
"lcall $0, $0x7c00\n\t"
"addw $4, %%sp\n\t" )
: "=a" ( rc ), "=b" ( discard_b ),
- "=c" ( discard_c )
- : "a" ( __from_text16 ( &ppxe ) ),
- "b" ( __from_text16 ( &pxenv ) ),
- "c" ( rm_cs )
- : "edx", "esi", "edi", "ebp", "memory" );
+ "=c" ( discard_c ), "=d" ( discard_d ),
+ "=D" ( discard_D )
+ : "a" ( 0 ), "b" ( __from_text16 ( &pxenv ) ),
+ "c" ( rm_cs ),
+ "d" ( virt_to_phys ( &pxenv ) ),
+ "D" ( __from_text16 ( &ppxe ) )
+ : "esi", "ebp", "memory" );
return rc;
}
* Returns:
* %ax : 0x564e
* %es:bx : Far pointer to the PXENV+ structure
+ * %edx : Physical address of the PXENV+ structure
* CF cleared
* Corrupts:
* none
cmpw $0x5650, %ax
jne 1f
/* INT 1A,5650 - PXE installation check */
- pushw %cs
- popw %es
+ xorl %edx, %edx
+ movw %cs, %dx
+ movw %dx, %es
movw $pxenv, %bx
+ shll $4, %edx
+ addl $pxenv, %edx
movw $0x564e, %ax
popfw
clc
pushl $STACK_MAGIC
movw %ss, %cs:pxe_ss
movl %esp, %cs:pxe_esp
- movw %sp, %bp
- movl (10*4+4*2+4)(%bp),%ebp /* !PXE address */
- /* Set up %ds */
+ /* Set up segments */
movw %cs, %ax
movw %ax, %ds
- /* Record PXENV+ and !PXE nominal addresses */
- movw %es, pxenv_segment /* PXENV+ address */
- movw %bx, pxenv_offset
- movl %ebp, ppxe_segoff /* !PXE address */
- /* Set up %es and %fs */
- movw %ax, %es
movw $0x40, %ax /* BIOS data segment access */
movw %ax, %fs
/* Set up stack just below 0x7c00 */
.previous
/*****************************************************************************
- * Verify PXENV+ structure and record parameters of interest
+ * Find us a usable !PXE or PXENV+ entry point
*****************************************************************************
*/
-detect_pxenv:
- /* Signature check */
- les pxenv_segoff, %bx
- cmpl $0x4e455850, %es:(%bx) /* 'PXEN' signature */
- jne no_pxenv
- cmpw $0x2b56, %es:4(%bx) /* 'V+' signature */
- jne no_pxenv
+detect_pxe:
+ /* Plan A: !PXE pointer from the stack */
+ lgsl pxe_esp, %ebp /* %gs:%bp -> original stack */
+ lesw %gs:52(%bp), %bx
+ call is_valid_ppxe
+ je have_ppxe
+
+ /* Plan B: PXENV+ pointer from initial ES:BX */
+ movw %gs:32(%bp),%bx
+ movw %gs:8(%bp),%es
+ call is_valid_pxenv
+ je have_pxenv
+
+ /* Plan C: PXENV+ structure via INT 1Ah */
+ movw $0x5650, %ax
+ int $0x1a
+ jc 1f
+ cmpw $0x564e, %ax
+ jne 1f
+ call is_valid_pxenv
+ je have_pxenv
+1:
+ /* Plan D: scan base memory for !PXE */
+ call memory_scan_ppxe
+ je have_ppxe
+
+ /* Plan E: scan base memory for PXENV+ */
+ call memory_scan_pxenv
+ jne stack_not_found
+
+have_pxenv:
+ movw %bx, pxenv_offset
+ movw %es, pxenv_segment
+
+ cmpw $0x201, %es:6(%bx) /* API version >= 2.01 */
+ jb 1f
+ cmpb $0x2c, %es:8(%bx) /* ... and structure long enough */
+ jb 2f
+
+ lesw %es:0x28(%bx), %bx /* Find !PXE from PXENV+ */
+ call is_valid_ppxe
+ je have_ppxe
+2:
+ call memory_scan_ppxe /* We are *supposed* to have !PXE... */
+ je have_ppxe
+1:
+ lesw pxenv_segoff, %bx /* Nope, we're stuck with PXENV+ */
+
/* Record entry point and UNDI segments */
pushl %es:0x0a(%bx) /* Entry point */
popl entry_segoff
pushw %es:0x20(%bx) /* UNDI data segment */
pushw %es:0x22(%bx) /* UNDI data size */
popl undi_data_segoff
+
/* Print "PXENV+ at <address>" */
movw $10f, %si
call print_message
call print_segoff
movb $( ',' ), %al
call print_character
- jmp 99f
+ jmp check_have_stack
.section ".prefix.data", "aw", @progbits
10: .asciz " PXENV+ at "
.previous
-no_pxenv:
- xorl %eax, %eax
- movl %eax, pxenv_segoff
-
-99:
-
-/*****************************************************************************
- * Verify !PXE structure and record parameters of interest
- *****************************************************************************
- */
-detect_ppxe:
- /* Signature check */
- les ppxe_segoff, %bx
- cmpl $0x45585021, %es:(%bx) /* '!PXE' signature */
- jne no_ppxe
- /* Record structure address, entry point, and UNDI segments */
- pushw %es
- popw ppxe_segment
+have_ppxe:
movw %bx, ppxe_offset
+ movw %es, ppxe_segment
+
pushl %es:0x10(%bx) /* Entry point */
popl entry_segoff
pushw %es:0x30(%bx) /* UNDI code segment */
call print_segoff
movb $( ',' ), %al
call print_character
- jmp 99f
+ jmp check_have_stack
.section ".prefix.data", "aw", @progbits
10: .asciz " !PXE at "
.previous
-no_ppxe:
- xorl %eax, %eax
- movl %eax, ppxe_segoff
+is_valid_ppxe:
+ cmpl $0x45585021, %es:(%bx)
+ jne 1f
+ movzbw %es:4(%bx), %cx
+ cmpw $0x58, %cx
+ jae is_valid_checksum
+1:
+ ret
+
+is_valid_pxenv:
+ cmpl $0x4e455850, %es:(%bx)
+ jne 1b
+ cmpw $0x2b56, %es:4(%bx)
+ jne 1b
+ movzbw %es:8(%bx), %cx
+ cmpw $0x28, %cx
+ jb 1b
+
+is_valid_checksum:
+ pushw %ax
+ movw %bx, %si
+ xorw %ax, %ax
+2:
+ es lodsb
+ addb %al, %ah
+ loopw 2b
+ popw %ax
+ ret
+
+memory_scan_ppxe:
+ movw $is_valid_ppxe, %dx
+ jmp memory_scan_common
-99:
+memory_scan_pxenv:
+ movw $is_valid_pxenv, %dx
+memory_scan_common:
+ movw %fs:(0x13), %ax
+ shlw $6, %ax
+ decw %ax
+1: incw %ax
+ cmpw $( 0xa000 - 1 ), %ax
+ ja 2f
+ movw %ax, %es
+ xorw %bx, %bx
+ call *%dx
+ jne 1b
+2: ret
+
/*****************************************************************************
* Sanity check: we must have an entry point
*****************************************************************************
testl %eax, %eax
jnz 99f
/* No entry point: print message and skip everything else */
+stack_not_found:
movw $10f, %si
call print_message
jmp finished
*/
.section ".prefix.data"
-pxe_ss: .word 0
pxe_esp: .long 0
+pxe_ss: .word 0
pxe_parameter_structure: .fill 20
shell();
} else {
/* User doesn't want shell; load and execute the first
- * image. If booting fails (i.e. if the image
- * returns, or fails to execute), offer a second
- * chance to enter the shell for diagnostics.
+ * image, or autoboot() if we have no images. If
+ * booting fails for any reason, offer a second chance
+ * to enter the shell for diagnostics.
*/
- for_each_image ( image ) {
- image_exec ( image );
- break;
+ if ( have_images() ) {
+ for_each_image ( image ) {
+ image_exec ( image );
+ break;
+ }
+ } else {
+ autoboot();
}
if ( shell_banner() )
0xb3,0x7d,0xfa,0xef,0xc5,0x91,
};
-/* ----- static functions ----- */
-static void AES_encrypt(const AES_CTX *ctx, uint32_t *data);
-static void AES_decrypt(const AES_CTX *ctx, uint32_t *data);
-
/* Perform doubling in Galois Field GF(2^8) using the irreducible polynomial
x^8+x^4+x^3+x+1 */
static unsigned char AES_xtime(uint32_t x)
}
}
+#if 0
/**
* Encrypt a byte sequence (with a block size 16) using the AES cipher.
*/
l2n(xor2, iv);
l2n(xor3, iv);
}
+#endif
/**
* Encrypt a single block (16 bytes) of data
*/
-static void AES_encrypt(const AES_CTX *ctx, uint32_t *data)
+void AES_encrypt(const AES_CTX *ctx, uint32_t *data)
{
/* To make this code smaller, generate the sbox entries on the fly.
* This will have a really heavy effect upon performance.
/**
* Decrypt a single block (16 bytes) of data
*/
-static void AES_decrypt(const AES_CTX *ctx, uint32_t *data)
+void AES_decrypt(const AES_CTX *ctx, uint32_t *data)
{
uint32_t tmp[4];
uint32_t xt0,xt1,xt2,xt3,xt4,xt5,xt6;
uint8_t *out, int length);
void AES_cbc_decrypt(AES_CTX *ks, const uint8_t *in, uint8_t *out, int length);
void AES_convert_key(AES_CTX *ctx);
+void AES_encrypt(const AES_CTX *ctx, uint32_t *data);
+void AES_decrypt(const AES_CTX *ctx, uint32_t *data);
/**************************************************************************
* RC4 declarations
-#include "crypto/axtls/crypto.h"
+/*
+ * Copyright (C) 2007 Michael Brown <mbrown@fensystems.co.uk>.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
#include <string.h>
#include <errno.h>
+#include <byteswap.h>
#include <gpxe/crypto.h>
+#include <gpxe/cbc.h>
#include <gpxe/aes.h>
+#include "crypto/axtls/crypto.h"
+
+/** @file
+ *
+ * AES algorithm
+ *
+ */
+
+/** Basic AES blocksize */
+#define AES_BLOCKSIZE 16
+
+/** AES context */
+struct aes_context {
+ /** AES context for AXTLS */
+ AES_CTX axtls_ctx;
+ /** Cipher is being used for decrypting */
+ int decrypting;
+};
+/**
+ * Set key
+ *
+ * @v ctx Context
+ * @v key Key
+ * @v keylen Key length
+ * @ret rc Return status code
+ */
static int aes_setkey ( void *ctx, const void *key, size_t keylen ) {
- AES_CTX *aesctx = ctx;
+ struct aes_context *aes_ctx = ctx;
AES_MODE mode;
+ void *iv;
switch ( keylen ) {
case ( 128 / 8 ):
return -EINVAL;
}
- AES_set_key ( aesctx, key, aesctx->iv, mode );
+ /* IV is not a relevant concept at this stage; use a dummy
+ * value that will have no side-effects.
+ */
+ iv = &aes_ctx->axtls_ctx.iv;
+
+ AES_set_key ( &aes_ctx->axtls_ctx, key, iv, mode );
+
+ aes_ctx->decrypting = 0;
+
return 0;
}
-static void aes_setiv ( void *ctx, const void *iv ) {
- AES_CTX *aesctx = ctx;
+/**
+ * Set initialisation vector
+ *
+ * @v ctx Context
+ * @v iv Initialisation vector
+ */
+static void aes_setiv ( void *ctx __unused, const void *iv __unused ) {
+ /* Nothing to do */
+}
- memcpy ( aesctx->iv, iv, sizeof ( aesctx->iv ) );
+/**
+ * Call AXTLS' AES_encrypt() or AES_decrypt() functions
+ *
+ * @v axtls_ctx AXTLS AES context
+ * @v src Data to process
+ * @v dst Buffer for output
+ * @v func AXTLS AES function to call
+ */
+static void aes_call_axtls ( AES_CTX *axtls_ctx, const void *src, void *dst,
+ void ( * func ) ( const AES_CTX *axtls_ctx,
+ uint32_t *data ) ){
+ const uint32_t *srcl = src;
+ uint32_t *dstl = dst;
+ unsigned int i;
+
+ /* AXTLS' AES_encrypt() and AES_decrypt() functions both
+ * expect to deal with an array of four dwords in host-endian
+ * order.
+ */
+ for ( i = 0 ; i < 4 ; i++ )
+ dstl[i] = ntohl ( srcl[i] );
+ func ( axtls_ctx, dstl );
+ for ( i = 0 ; i < 4 ; i++ )
+ dstl[i] = htonl ( dstl[i] );
}
-static void aes_encrypt ( void *ctx, const void *data, void *dst,
+/**
+ * Encrypt data
+ *
+ * @v ctx Context
+ * @v src Data to encrypt
+ * @v dst Buffer for encrypted data
+ * @v len Length of data
+ */
+static void aes_encrypt ( void *ctx, const void *src, void *dst,
size_t len ) {
- AES_CTX *aesctx = ctx;
+ struct aes_context *aes_ctx = ctx;
- AES_cbc_encrypt ( aesctx, data, dst, len );
+ assert ( len == AES_BLOCKSIZE );
+ if ( aes_ctx->decrypting )
+ assert ( 0 );
+ aes_call_axtls ( &aes_ctx->axtls_ctx, src, dst, AES_encrypt );
}
-static void aes_decrypt ( void *ctx, const void *data, void *dst,
+/**
+ * Decrypt data
+ *
+ * @v ctx Context
+ * @v src Data to decrypt
+ * @v dst Buffer for decrypted data
+ * @v len Length of data
+ */
+static void aes_decrypt ( void *ctx, const void *src, void *dst,
size_t len ) {
- AES_CTX *aesctx = ctx;
+ struct aes_context *aes_ctx = ctx;
- AES_cbc_decrypt ( aesctx, data, dst, len );
+ assert ( len == AES_BLOCKSIZE );
+ if ( ! aes_ctx->decrypting ) {
+ AES_convert_key ( &aes_ctx->axtls_ctx );
+ aes_ctx->decrypting = 1;
+ }
+ aes_call_axtls ( &aes_ctx->axtls_ctx, src, dst, AES_decrypt );
}
-struct crypto_algorithm aes_algorithm = {
- .name = "aes",
- .ctxsize = sizeof ( AES_CTX ),
- .blocksize = 16,
- .setkey = aes_setkey,
- .setiv = aes_setiv,
- .encode = aes_encrypt,
- .decode = aes_decrypt,
+/** Basic AES algorithm */
+static struct cipher_algorithm aes_algorithm = {
+ .name = "aes",
+ .ctxsize = sizeof ( struct aes_context ),
+ .blocksize = AES_BLOCKSIZE,
+ .setkey = aes_setkey,
+ .setiv = aes_setiv,
+ .encrypt = aes_encrypt,
+ .decrypt = aes_decrypt,
};
+
+/* AES with cipher-block chaining */
+CBC_CIPHER ( aes_cbc, aes_cbc_algorithm,
+ aes_algorithm, struct aes_context, AES_BLOCKSIZE );
SHA1Init ( ctx );
}
-static void sha1_update ( void *ctx, const void *data, void *dst __unused,
- size_t len ) {
+static void sha1_update ( void *ctx, const void *data, size_t len ) {
SHA1Update ( ctx, data, len );
}
SHA1Final ( ctx, out );
}
-struct crypto_algorithm sha1_algorithm = {
+struct digest_algorithm sha1_algorithm = {
.name = "sha1",
.ctxsize = SHA1_CTX_SIZE,
.blocksize = 64,
.digestsize = SHA1_DIGEST_SIZE,
.init = sha1_init,
- .encode = sha1_update,
+ .update = sha1_update,
.final = sha1_final,
};
--- /dev/null
+/*
+ * Copyright (C) 2009 Michael Brown <mbrown@fensystems.co.uk>.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <gpxe/crypto.h>
+#include <gpxe/cbc.h>
+
+/** @file
+ *
+ * Cipher-block chaining
+ *
+ */
+
+/**
+ * XOR data blocks
+ *
+ * @v src Input data
+ * @v dst Second input data and output data buffer
+ * @v len Length of data
+ */
+static void cbc_xor ( const void *src, void *dst, size_t len ) {
+ const uint32_t *srcl = src;
+ uint32_t *dstl = dst;
+ unsigned int i;
+
+ /* Assume that block sizes will always be dword-aligned, for speed */
+ assert ( ( len % sizeof ( *srcl ) ) == 0 );
+
+ for ( i = 0 ; i < ( len / sizeof ( *srcl ) ) ; i++ )
+ dstl[i] ^= srcl[i];
+}
+
+/**
+ * Encrypt data
+ *
+ * @v ctx Context
+ * @v src Data to encrypt
+ * @v dst Buffer for encrypted data
+ * @v len Length of data
+ * @v raw_cipher Underlying cipher algorithm
+ * @v cbc_ctx CBC context
+ */
+void cbc_encrypt ( void *ctx, const void *src, void *dst, size_t len,
+ struct cipher_algorithm *raw_cipher, void *cbc_ctx ) {
+ size_t blocksize = raw_cipher->blocksize;
+
+ assert ( ( len % blocksize ) == 0 );
+
+ while ( len ) {
+ cbc_xor ( src, cbc_ctx, blocksize );
+ cipher_encrypt ( raw_cipher, ctx, cbc_ctx, dst, blocksize );
+ memcpy ( cbc_ctx, dst, blocksize );
+ dst += blocksize;
+ src += blocksize;
+ len -= blocksize;
+ }
+}
+
+/**
+ * Decrypt data
+ *
+ * @v ctx Context
+ * @v src Data to decrypt
+ * @v dst Buffer for decrypted data
+ * @v len Length of data
+ * @v raw_cipher Underlying cipher algorithm
+ * @v cbc_ctx CBC context
+ */
+void cbc_decrypt ( void *ctx, const void *src, void *dst, size_t len,
+ struct cipher_algorithm *raw_cipher, void *cbc_ctx ) {
+ size_t blocksize = raw_cipher->blocksize;
+
+ assert ( ( len % blocksize ) == 0 );
+
+ while ( len ) {
+ cipher_decrypt ( raw_cipher, ctx, src, dst, blocksize );
+ cbc_xor ( cbc_ctx, dst, blocksize );
+ memcpy ( cbc_ctx, src, blocksize );
+ dst += blocksize;
+ src += blocksize;
+ len -= blocksize;
+ }
+}
* eventually be freed by a call to chap_finish().
*/
int chap_init ( struct chap_response *chap,
- struct crypto_algorithm *digest ) {
+ struct digest_algorithm *digest ) {
size_t state_len;
void *state;
+++ /dev/null
-#include <stdint.h>
-#include <errno.h>
-#include <gpxe/crypto.h>
-
-int cipher_encrypt ( struct crypto_algorithm *crypto,
- void *ctx, const void *src, void *dst,
- size_t len ) {
- if ( ( len & ( crypto->blocksize - 1 ) ) ) {
- return -EINVAL;
- }
- crypto->encode ( ctx, src, dst, len );
- return 0;
-}
-
-int cipher_decrypt ( struct crypto_algorithm *crypto,
- void *ctx, const void *src, void *dst,
- size_t len ) {
- if ( ( len & ( crypto->blocksize - 1 ) ) ) {
- return -EINVAL;
- }
- crypto->decode ( ctx, src, dst, len );
- return 0;
-}
-
#include <string.h>
#include <gpxe/crypto.h>
-static void null_init ( void *ctx __unused ) {
+static void digest_null_init ( void *ctx __unused ) {
/* Do nothing */
}
-static int null_setkey ( void *ctx __unused, const void *key __unused,
- size_t keylen __unused ) {
+static void digest_null_update ( void *ctx __unused, const void *src __unused,
+ size_t len __unused ) {
/* Do nothing */
- return 0;
}
-static void null_setiv ( void *ctx __unused, const void *iv __unused ) {
+static void digest_null_final ( void *ctx __unused, void *out __unused ) {
/* Do nothing */
}
-static void null_encode ( void *ctx __unused, const void *src,
- void *dst, size_t len ) {
- if ( dst )
- memcpy ( dst, src, len );
-}
+struct digest_algorithm digest_null = {
+ .name = "null",
+ .ctxsize = 0,
+ .blocksize = 1,
+ .digestsize = 0,
+ .init = digest_null_init,
+ .update = digest_null_update,
+ .final = digest_null_final,
+};
-static void null_decode ( void *ctx __unused, const void *src,
- void *dst, size_t len ) {
- if ( dst )
- memcpy ( dst, src, len );
+static int cipher_null_setkey ( void *ctx __unused, const void *key __unused,
+ size_t keylen __unused ) {
+ /* Do nothing */
+ return 0;
}
-static void null_final ( void *ctx __unused, void *out __unused ) {
+static void cipher_null_setiv ( void *ctx __unused,
+ const void *iv __unused ) {
/* Do nothing */
}
-struct crypto_algorithm crypto_null = {
+static void cipher_null_encrypt ( void *ctx __unused, const void *src,
+ void *dst, size_t len ) {
+ memcpy ( dst, src, len );
+}
+
+static void cipher_null_decrypt ( void *ctx __unused, const void *src,
+ void *dst, size_t len ) {
+ memcpy ( dst, src, len );
+}
+
+struct cipher_algorithm cipher_null = {
.name = "null",
.ctxsize = 0,
.blocksize = 1,
- .digestsize = 0,
- .init = null_init,
- .setkey = null_setkey,
- .setiv = null_setiv,
- .encode = null_encode,
- .decode = null_decode,
- .final = null_final,
+ .setkey = cipher_null_setkey,
+ .setiv = cipher_null_setiv,
+ .encrypt = cipher_null_encrypt,
+ .decrypt = cipher_null_decrypt,
+};
+
+struct pubkey_algorithm pubkey_null = {
+ .name = "null",
+ .ctxsize = 0,
};
* @v key Key
* @v key_len Length of key
*/
-static void hmac_reduce_key ( struct crypto_algorithm *digest,
+static void hmac_reduce_key ( struct digest_algorithm *digest,
void *key, size_t *key_len ) {
uint8_t digest_ctx[digest->ctxsize];
* will be replaced with its own digest, and key_len will be updated
* accordingly).
*/
-void hmac_init ( struct crypto_algorithm *digest, void *digest_ctx,
+void hmac_init ( struct digest_algorithm *digest, void *digest_ctx,
void *key, size_t *key_len ) {
unsigned char k_ipad[digest->blocksize];
unsigned int i;
* will be replaced with its own digest, and key_len will be updated
* accordingly).
*/
-void hmac_final ( struct crypto_algorithm *digest, void *digest_ctx,
+void hmac_final ( struct digest_algorithm *digest, void *digest_ctx,
void *key, size_t *key_len, void *hmac ) {
unsigned char k_opad[digest->blocksize];
unsigned int i;
mctx->byte_count = 0;
}
-static void md5_update(void *context, const void *data, void *dst __unused,
- size_t len)
+static void md5_update(void *context, const void *data, size_t len)
{
struct md5_ctx *mctx = context;
const u32 avail = sizeof(mctx->block) - (mctx->byte_count & 0x3f);
memset(mctx, 0, sizeof(*mctx));
}
-struct crypto_algorithm md5_algorithm = {
+struct digest_algorithm md5_algorithm = {
.name = "md5",
.ctxsize = MD5_CTX_SIZE,
.blocksize = ( MD5_BLOCK_WORDS * 4 ),
.digestsize = MD5_DIGEST_SIZE,
.init = md5_init,
- .encode = md5_update,
+ .update = md5_update,
.final = md5_final,
};
+++ /dev/null
-#!gpxe
-kernel http://www.zytor.com/dl360/pxelinux.0
-set filename http://www.zytor.com/dl360/pxelinux.0
-boot
/* Something went wrong with the issuing mechanism,
* (rather than with the command itself)
*/
- DBG ( "SCSI %p " SCSI_CDB_FORMAT " err %d\n",
- scsi, SCSI_CDB_DATA ( command->cdb ), rc );
+ DBG ( "SCSI %p " SCSI_CDB_FORMAT " err %s\n",
+ scsi, SCSI_CDB_DATA ( command->cdb ), strerror ( rc ) );
return rc;
}
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-
-/***
- *** This file was generated at "Tue Sep 6 09:14:00 2005"
- *** by:
- *** % csp_bf -copyright=/mswg/misc/license-header.txt -prefix tavorprm_ -bits -fixnames MT23108_PRM.csp
- ***/
-
-#ifndef H_prefix_tavorprm_bits_fixnames_MT23108_PRM_csp_H
-#define H_prefix_tavorprm_bits_fixnames_MT23108_PRM_csp_H
-
-#include "bit_ops.h"
-
-/* Send doorbell */
-
-struct tavorprm_send_doorbell_st { /* Little Endian */
- pseudo_bit_t nopcode[0x00005]; /* Opcode of descriptor to be executed */
- pseudo_bit_t f[0x00001]; /* Fence bit. If set, descriptor is fenced */
- pseudo_bit_t nda[0x0001a]; /* Bits 31:6 of descriptors virtual address */
-/* -------------- */
- pseudo_bit_t nds[0x00006]; /* Next descriptor size (in 16-byte chunks) */
- pseudo_bit_t reserved0[0x00002];
- pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */
-/* -------------- */
-};
-
-/* ACCESS_DDR_inject_errors_input_modifier */
-
-struct tavorprm_access_ddr_inject_errors_input_modifier_st { /* Little Endian */
- pseudo_bit_t index3[0x00007];
- pseudo_bit_t q3[0x00001];
- pseudo_bit_t index2[0x00007];
- pseudo_bit_t q2[0x00001];
- pseudo_bit_t index1[0x00007];
- pseudo_bit_t q1[0x00001];
- pseudo_bit_t index0[0x00007];
- pseudo_bit_t q0[0x00001];
-/* -------------- */
-};
-
-/* ACCESS_DDR_inject_errors_input_parameter */
-
-struct tavorprm_access_ddr_inject_errors_input_parameter_st { /* Little Endian */
- pseudo_bit_t ba[0x00002]; /* Bank Address */
- pseudo_bit_t da[0x00002]; /* Dimm Address */
- pseudo_bit_t reserved0[0x0001c];
-/* -------------- */
- pseudo_bit_t ra[0x00010]; /* Row Address */
- pseudo_bit_t ca[0x00010]; /* Column Address */
-/* -------------- */
-};
-
-/* Address Path */
-
-struct tavorprm_address_path_st { /* Little Endian */
- pseudo_bit_t pkey_index[0x00007]; /* PKey table index */
- pseudo_bit_t reserved0[0x00011];
- pseudo_bit_t port_number[0x00002]; /* Specific port associated with this QP/EE.
- 1 - Port 1
- 2 - Port 2
- other - reserved */
- pseudo_bit_t reserved1[0x00006];
-/* -------------- */
- pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */
- pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */
- pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */
- pseudo_bit_t reserved2[0x00005];
- pseudo_bit_t rnr_retry[0x00003]; /* RNR retry count (see C9-132 in IB spec Vol 1)
- 0-6 - number of retries
- 7 - infinite */
-/* -------------- */
- pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */
- pseudo_bit_t max_stat_rate[0x00003];/* Maximum static rate control.
- 0 - 4X injection rate
- 1 - 1X injection rate
- other - reserved
- */
- pseudo_bit_t reserved3[0x00005];
- pseudo_bit_t mgid_index[0x00006]; /* Index to port GID table */
- pseudo_bit_t reserved4[0x00005];
- pseudo_bit_t ack_timeout[0x00005]; /* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details.
- The transport timer is set to 4.096us*2^ack_timeout, if ack_timeout is 0 then transport timer is disabled. */
-/* -------------- */
- pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */
- pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */
- pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */
-/* -------------- */
- pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */
-/* -------------- */
- pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */
-/* -------------- */
- pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */
-/* -------------- */
- pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] */
-/* -------------- */
-};
-
-/* HCA Command Register (HCR) */
-
-struct tavorprm_hca_command_register_st { /* Little Endian */
- pseudo_bit_t in_param_h[0x00020]; /* Input Parameter: parameter[63:32] or pointer[63:32] to input mailbox (see command description) */
-/* -------------- */
- pseudo_bit_t in_param_l[0x00020]; /* Input Parameter: parameter[31:0] or pointer[31:0] to input mailbox (see command description) */
-/* -------------- */
- pseudo_bit_t input_modifier[0x00020];/* Input Parameter Modifier */
-/* -------------- */
- pseudo_bit_t out_param_h[0x00020]; /* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */
-/* -------------- */
- pseudo_bit_t out_param_l[0x00020]; /* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */
-/* -------------- */
- pseudo_bit_t reserved0[0x00010];
- pseudo_bit_t token[0x00010]; /* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */
-/* -------------- */
- pseudo_bit_t opcode[0x0000c]; /* Command opcode */
- pseudo_bit_t opcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */
- pseudo_bit_t reserved1[0x00006];
- pseudo_bit_t e[0x00001]; /* Event Request
- 0 - Don't report event (software will poll the GO bit)
- 1 - Report event to EQ when the command completes */
- pseudo_bit_t go[0x00001]; /* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR)
- Software can write to the HCR only if Go bit is cleared.
- Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */
- pseudo_bit_t status[0x00008]; /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared)
- 0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */
-/* -------------- */
-};
-
-/* EQ Doorbell */
-
-struct tavorprm_eq_cmd_doorbell_st { /* Little Endian */
- pseudo_bit_t eqn[0x00006]; /* EQ accessed */
- pseudo_bit_t reserved0[0x00012];
- pseudo_bit_t eq_cmd[0x00008]; /* Command to be executed on EQ
- 01 - increment Consumer_indx by one
- 02 - Request notification for next event (Arm EQ)
- 03 - Disarm CQ (CQ number is specified in EQ_param)
- 04 - set Consumer_indx to value of EQ_param
- 05 - move EQ to Always Armed state
- other - reserved */
-/* -------------- */
- pseudo_bit_t eq_param[0x00020]; /* parameter to be used by EQ commands 03 and 04. Reserved for other commands. */
-/* -------------- */
-};
-
-/* CQ Doorbell */
-
-struct tavorprm_cq_cmd_doorbell_st { /* Little Endian */
- pseudo_bit_t cqn[0x00018]; /* CQ number accessed */
- pseudo_bit_t cq_cmd[0x00008]; /* Command to be executed on CQ
- 01 - Increment Consumer_indx by cq_param plus 1
- 02 - Request notification for next Solicited or Unsolicited completion event. CQ_param must contain last succesfully polled consumer index. For newly generated CQs the CQ_param should contain (initial consumer index-1) modulu CQ size. When working with CQs with overrun detection, CQ_param can be set to 0xFFFFFFFF (HW will use the last polled index).
- 03 - Request notification for next Solicited completion event CQ_param must contain last succesfully polled consumer index. For newly generated CQs the CQ_param should contain (initial consumer index-1) modulu CQ size. When working with CQs with overrun detection, CQ_param can be set to 0xFFFFFFFF (HW will use the last polled index).
- 04 - Set Consumer_indx to value of CQ_param
- 05 - Request notification for multiple completions (see Advanced Topics chater)
- other - reserved */
-/* -------------- */
- pseudo_bit_t cq_param[0x00020]; /* parameter to be used by CQ command */
-/* -------------- */
-};
-
-/* Receive doorbell */
-
-struct tavorprm_receive_doorbell_st { /* Little Endian */
- pseudo_bit_t nds[0x00006]; /* Next descriptor size (in 16-byte chunks)
- Must be zero for SRQ doorbells */
- pseudo_bit_t nda[0x0001a]; /* Bits 31:6 of descriptors virtual address */
-/* -------------- */
- pseudo_bit_t credits[0x00008]; /* Amount of credits ((length of the chain) posted with the doorbell on receive queue. Chain of up to 256 descriptors can be linked with single doorbell. Zero value in this field means 256. */
- pseudo_bit_t qpn[0x00018]; /* QP number or SRQ number this doorbell is rung on */
-/* -------------- */
-};
-
-/* RD-send doorbell */
-
-struct tavorprm_rd_send_doorbell_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00008];
- pseudo_bit_t een[0x00018]; /* End-to-end context number (reliable datagram)
- Must be zero for Nop and Bind operations */
-/* -------------- */
- pseudo_bit_t reserved1[0x00008];
- pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */
-/* -------------- */
- struct tavorprm_send_doorbell_st snd_params;/* Send parameters */
-/* -------------- */
-};
-
-/* Multicast Group Member QP */
-
-struct tavorprm_mgmqp_st { /* Little Endian */
- pseudo_bit_t qpn_i[0x00018]; /* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */
- pseudo_bit_t reserved0[0x00007];
- pseudo_bit_t qi[0x00001]; /* Qi: QPN_i is valid */
-/* -------------- */
-};
-
-/* vsd */
-
-struct tavorprm_vsd_st { /* Little Endian */
- pseudo_bit_t vsd_dw0[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw1[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw2[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw3[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw4[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw5[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw6[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw7[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw8[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw9[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw10[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw11[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw12[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw13[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw14[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw15[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw16[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw17[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw18[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw19[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw20[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw21[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw22[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw23[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw24[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw25[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw26[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw27[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw28[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw29[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw30[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw31[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw32[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw33[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw34[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw35[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw36[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw37[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw38[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw39[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw40[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw41[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw42[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw43[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw44[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw45[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw46[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw47[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw48[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw49[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw50[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw51[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw52[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw53[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw54[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw55[0x00020];
-/* -------------- */
-};
-
-/* ACCESS_DDR_inject_errors */
-
-struct tavorprm_access_ddr_inject_errors_st { /* Little Endian */
- struct tavorprm_access_ddr_inject_errors_input_parameter_st access_ddr_inject_errors_input_parameter;
-/* -------------- */
- struct tavorprm_access_ddr_inject_errors_input_modifier_st access_ddr_inject_errors_input_modifier;
-/* -------------- */
- pseudo_bit_t reserved0[0x00020];
-/* -------------- */
-};
-
-/* Logical DIMM Information */
-
-struct tavorprm_dimminfo_st { /* Little Endian */
- pseudo_bit_t dimmsize[0x00010]; /* Size of DIMM in units of 2^20 Bytes. This value is valid only when DIMMStatus is 0. */
- pseudo_bit_t reserved0[0x00008];
- pseudo_bit_t dimmstatus[0x00001]; /* DIMM Status
- 0 - Enabled
- 1 - Disabled
- */
- pseudo_bit_t dh[0x00001]; /* When set, the DIMM is Hidden and can not be accessed from the PCI bus. */
- pseudo_bit_t wo[0x00001]; /* When set, the DIMM is write only.
- If data integrity is configured (other than none), the DIMM must be
- only targeted by write transactions where the address and size are multiples of 16 bytes. */
- pseudo_bit_t reserved1[0x00005];
-/* -------------- */
- pseudo_bit_t spd[0x00001]; /* 0 - DIMM SPD was read from DIMM
- 1 - DIMM SPD was read from InfiniHost NVMEM */
- pseudo_bit_t sladr[0x00003]; /* SPD Slave Address 3 LSBits.
- Valid only if spd bit is 0. */
- pseudo_bit_t sock_num[0x00002]; /* DIMM socket number (for double sided DIMM one of the two numbers will be reported) */
- pseudo_bit_t syn[0x00004]; /* Error syndrome (valid regardless of status value)
- 0 - DIMM has no error
- 1 - SPD error (e.g. checksum error, no response, error while reading)
- 2 - DIMM out of bounds (e.g. DIMM rows number is not between 7 and 14, DIMM type is not 2)
- 3 - DIMM conflict (e.g. mix of registered and unbuffered DIMMs, CAS latency conflict)
- 5 - DIMM size trimmed due to configuration (size exceeds)
- other - Error, reserved
- */
- pseudo_bit_t reserved2[0x00016];
-/* -------------- */
- pseudo_bit_t vendor_id_h[0x00020]; /* JDEC Manufacturer ID[63:32] */
-/* -------------- */
- pseudo_bit_t vendor_id_l[0x00020]; /* JDEC Manufacturer ID[31:0] */
-/* -------------- */
- pseudo_bit_t dimm_start_adr_h[0x00020];/* DIMM memory start address [63:32]. This value is valid only when DIMMStatus is 0. */
-/* -------------- */
- pseudo_bit_t dimm_start_adr_l[0x00020];/* DIMM memory start address [31:0]. This value is valid only when DIMMStatus is 0. */
-/* -------------- */
- pseudo_bit_t reserved3[0x00040];
-/* -------------- */
-};
-
-/* UAR Parameters */
-
-struct tavorprm_uar_params_st { /* Little Endian */
- pseudo_bit_t uar_base_addr_h[0x00020];/* UAR Base Address [63:32] (QUERY_HCA only) */
-/* -------------- */
- pseudo_bit_t reserved0[0x00014];
- pseudo_bit_t uar_base_addr_l[0x0000c];/* UAR Base Address [31:20] (QUERY_HCA only) */
-/* -------------- */
- pseudo_bit_t uar_page_sz[0x00008]; /* This field defines the size of each UAR page.
- Size of UAR Page is 4KB*2^UAR_Page_Size */
- pseudo_bit_t reserved1[0x00018];
-/* -------------- */
- pseudo_bit_t reserved2[0x00020];
-/* -------------- */
- pseudo_bit_t uar_scratch_base_addr_h[0x00020];/* Base address of UAR scratchpad [63:32].
- Number of entries in table is UAR BAR size divided by UAR Page Size.
- Table must be aligned to entry size. */
-/* -------------- */
- pseudo_bit_t uar_scratch_base_addr_l[0x00020];/* Base address of UAR scratchpad [31:0].
- Number of entries in table is UAR BAR size divided by UAR Page Size.
- Table must be aligned to entry size. */
-/* -------------- */
- pseudo_bit_t reserved3[0x00040];
-/* -------------- */
-};
-
-/* Translation and Protection Tables Parameters */
-
-struct tavorprm_tptparams_st { /* Little Endian */
- pseudo_bit_t mpt_base_adr_h[0x00020];/* MPT - Memory Protection Table base physical address [63:32].
- Entry size is 64 bytes.
- Table must be aligned to its size.
- Address may be set to zero if address translation and protection is not supported. */
-/* -------------- */
- pseudo_bit_t mpt_base_adr_l[0x00020];/* MPT - Memory Protection Table base physical address [31:0].
- Entry size is 64 bytes.
- Table must be aligned to its size.
- Address may be set to zero if address translation and protection is not supported. */
-/* -------------- */
- pseudo_bit_t log_mpt_sz[0x00006]; /* Log (base 2) of the number of region/windows entries in the MPT table. */
- pseudo_bit_t reserved0[0x00002];
- pseudo_bit_t pfto[0x00005]; /* Page Fault RNR Timeout -
- The field returned in RNR Naks generated when a page fault is detected.
- It has no effect when on-demand-paging is not used. */
- pseudo_bit_t reserved1[0x00003];
- pseudo_bit_t mtt_segment_size[0x00003];/* The size of MTT segment is 64*2^MTT_Segment_Size bytes */
- pseudo_bit_t reserved2[0x0000d];
-/* -------------- */
- pseudo_bit_t mtt_version[0x00008]; /* Version of MTT page walk. Must be zero */
- pseudo_bit_t reserved3[0x00018];
-/* -------------- */
- pseudo_bit_t mtt_base_addr_h[0x00020];/* MTT - Memory Translation table base physical address [63:32].
- Table must be aligned to its size.
- Address may be set to zero if address translation and protection is not supported. */
-/* -------------- */
- pseudo_bit_t mtt_base_addr_l[0x00020];/* MTT - Memory Translation table base physical address [31:0].
- Table must be aligned to its size.
- Address may be set to zero if address translation and protection is not supported. */
-/* -------------- */
- pseudo_bit_t reserved4[0x00040];
-/* -------------- */
-};
-
-/* Multicast Support Parameters */
-
-struct tavorprm_multicastparam_st { /* Little Endian */
- pseudo_bit_t mc_base_addr_h[0x00020];/* Base Address of the Multicast Table [63:32].
- The base address must be aligned to the entry size.
- Address may be set to zero if multicast is not supported. */
-/* -------------- */
- pseudo_bit_t mc_base_addr_l[0x00020];/* Base Address of the Multicast Table [31:0].
- The base address must be aligned to the entry size.
- Address may be set to zero if multicast is not supported. */
-/* -------------- */
- pseudo_bit_t reserved0[0x00040];
-/* -------------- */
- pseudo_bit_t log_mc_table_entry_sz[0x00010];/* Log2 of the Size of multicast group member (MGM) entry.
- Must be greater than 5 (to allow CTRL and GID sections).
- That implies the number of QPs per MC table entry. */
- pseudo_bit_t reserved1[0x00010];
-/* -------------- */
- pseudo_bit_t mc_table_hash_sz[0x00011];/* Number of entries in multicast DGID hash table (must be power of 2)
- INIT_HCA - the required number of entries
- QUERY_HCA - the actual number of entries assigned by firmware (will be less than or equal to the amount required in INIT_HCA) */
- pseudo_bit_t reserved2[0x0000f];
-/* -------------- */
- pseudo_bit_t log_mc_table_sz[0x00005];/* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */
- pseudo_bit_t reserved3[0x00013];
- pseudo_bit_t mc_hash_fn[0x00003]; /* Multicast hash function
- 0 - Default hash function
- other - reserved */
- pseudo_bit_t reserved4[0x00005];
-/* -------------- */
- pseudo_bit_t reserved5[0x00020];
-/* -------------- */
-};
-
-/* Memory Access Parameters for UD Address Vector Table */
-
-struct tavorprm_udavtable_memory_parameters_st { /* Little Endian */
- pseudo_bit_t l_key[0x00020]; /* L_Key used to access TPT */
-/* -------------- */
- pseudo_bit_t pd[0x00018]; /* PD used by TPT for matching against PD of region entry being accessed. */
- pseudo_bit_t reserved0[0x00005];
- pseudo_bit_t xlation_en[0x00001]; /* When cleared, address is physical address and no translation will be done. When set, address is virtual. TPT will be accessed in both cases for address decoding purposes. */
- pseudo_bit_t reserved1[0x00002];
-/* -------------- */
-};
-
-/* QPC/EEC/CQC/EQC/RDB Parameters */
-
-struct tavorprm_qpcbaseaddr_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00080];
-/* -------------- */
- pseudo_bit_t qpc_base_addr_h[0x00020];/* QPC Base Address [63:32]
- Table must be aligned on its size */
-/* -------------- */
- pseudo_bit_t log_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */
- pseudo_bit_t reserved1[0x00002];
- pseudo_bit_t qpc_base_addr_l[0x00019];/* QPC Base Address [31:7]
- Table must be aligned on its size */
-/* -------------- */
- pseudo_bit_t reserved2[0x00040];
-/* -------------- */
- pseudo_bit_t eec_base_addr_h[0x00020];/* EEC Base Address [63:32]
- Table must be aligned on its size.
- Address may be set to zero if RD is not supported. */
-/* -------------- */
- pseudo_bit_t log_num_of_ee[0x00005];/* Log base 2 of number of supported EEs. */
- pseudo_bit_t reserved3[0x00002];
- pseudo_bit_t eec_base_addr_l[0x00019];/* EEC Base Address [31:7]
- Table must be aligned on its size
- Address may be set to zero if RD is not supported. */
-/* -------------- */
- pseudo_bit_t srqc_base_addr_h[0x00020];/* SRQ Context Base Address [63:32]
- Table must be aligned on its size
- Address may be set to zero if SRQ is not supported. */
-/* -------------- */
- pseudo_bit_t log_num_of_srq[0x00005];/* Log base 2 of number of supported SRQs. */
- pseudo_bit_t srqc_base_addr_l[0x0001b];/* SRQ Context Base Address [31:5]
- Table must be aligned on its size
- Address may be set to zero if SRQ is not supported. */
-/* -------------- */
- pseudo_bit_t cqc_base_addr_h[0x00020];/* CQC Base Address [63:32]
- Table must be aligned on its size */
-/* -------------- */
- pseudo_bit_t log_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */
- pseudo_bit_t reserved4[0x00001];
- pseudo_bit_t cqc_base_addr_l[0x0001a];/* CQC Base Address [31:6]
- Table must be aligned on its size */
-/* -------------- */
- pseudo_bit_t reserved5[0x00040];
-/* -------------- */
- pseudo_bit_t eqpc_base_addr_h[0x00020];/* Extended QPC Base Address [63:32]
- Table has same number of entries as QPC table.
- Table must be aligned to entry size. */
-/* -------------- */
- pseudo_bit_t eqpc_base_addr_l[0x00020];/* Extended QPC Base Address [31:0]
- Table has same number of entries as QPC table.
- Table must be aligned to entry size. */
-/* -------------- */
- pseudo_bit_t reserved6[0x00040];
-/* -------------- */
- pseudo_bit_t eeec_base_addr_h[0x00020];/* Extended EEC Base Address [63:32]
- Table has same number of entries as EEC table.
- Table must be aligned to entry size.
- Address may be set to zero if RD is not supported. */
-/* -------------- */
- pseudo_bit_t eeec_base_addr_l[0x00020];/* Extended EEC Base Address [31:0]
- Table has same number of entries as EEC table.
- Table must be aligned to entry size.
- Address may be set to zero if RD is not supported. */
-/* -------------- */
- pseudo_bit_t reserved7[0x00040];
-/* -------------- */
- pseudo_bit_t eqc_base_addr_h[0x00020];/* EQC Base Address [63:32]
- Address may be set to zero if EQs are not supported.
- Table must be aligned to entry size. */
-/* -------------- */
- pseudo_bit_t log_num_eq[0x00004]; /* Log base 2 of number of supported EQs.
- Must be 6 or less in InfiniHost. */
- pseudo_bit_t reserved8[0x00002];
- pseudo_bit_t eqc_base_addr_l[0x0001a];/* EQC Base Address [31:6]
- Address may be set to zero if EQs are not supported.
- Table must be aligned to entry size. */
-/* -------------- */
- pseudo_bit_t reserved9[0x00040];
-/* -------------- */
- pseudo_bit_t rdb_base_addr_h[0x00020];/* Base address of table that holds remote read and remote atomic requests [63:32].
- Table must be aligned to RDB entry size (32 bytes).
- Address may be set to zero if remote RDMA reads are not supported.
- Please refer to QP and EE chapter for further explanation on RDB allocation. */
-/* -------------- */
- pseudo_bit_t rdb_base_addr_l[0x00020];/* Base address of table that holds remote read and remote atomic requests [31:0].
- Table must be aligned to RDB entry size (32 bytes).
- This field must always be zero.
- Please refer to QP and EE chapter for further explanation on RDB allocation. */
-/* -------------- */
- pseudo_bit_t reserved10[0x00040];
-/* -------------- */
-};
-
-/* Performance Monitors */
-
-struct tavorprm_performance_monitors_st { /* Little Endian */
- pseudo_bit_t e0[0x00001]; /* Enables counting of respective performance counter */
- pseudo_bit_t e1[0x00001]; /* Enables counting of respective performance counter */
- pseudo_bit_t e2[0x00001]; /* Enables counting of respective performance counter */
- pseudo_bit_t reserved0[0x00001];
- pseudo_bit_t r0[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
- pseudo_bit_t r1[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
- pseudo_bit_t r2[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
- pseudo_bit_t reserved1[0x00001];
- pseudo_bit_t i0[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
- pseudo_bit_t i1[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
- pseudo_bit_t i2[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
- pseudo_bit_t reserved2[0x00001];
- pseudo_bit_t f0[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
- pseudo_bit_t f1[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
- pseudo_bit_t f2[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
- pseudo_bit_t reserved3[0x00001];
- pseudo_bit_t ev_cnt1[0x00005]; /* Specifies event to be counted by Event_counter1 See XXX for events' definition. */
- pseudo_bit_t reserved4[0x00003];
- pseudo_bit_t ev_cnt2[0x00005]; /* Specifies event to be counted by Event_counter2 See XXX for events' definition. */
- pseudo_bit_t reserved5[0x00003];
-/* -------------- */
- pseudo_bit_t clock_counter[0x00020];
-/* -------------- */
- pseudo_bit_t event_counter1[0x00020];
-/* -------------- */
- pseudo_bit_t event_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */
-/* -------------- */
-};
-
-/* QP and EE Context Entry */
-
-struct tavorprm_queue_pair_ee_context_entry_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00008];
- pseudo_bit_t de[0x00001]; /* Send/Receive Descriptor Event enable - if set, events can be generated upon descriptors' completion on send/receive queue (controlled by E bit in WQE). Invalid in EE context */
- pseudo_bit_t reserved1[0x00002];
- pseudo_bit_t pm_state[0x00002]; /* Path migration state (Migrated, Armed or Rearm)
- 11-Migrated
- 00-Armed
- 01-Rearm
- 10-Reserved
- Should be set to 11 for UD QPs and for QPs which do not support APM */
- pseudo_bit_t reserved2[0x00003];
- pseudo_bit_t st[0x00003]; /* Service type (invalid in EE context):
- 000-Reliable Connection
- 001-Unreliable Connection
- 010-Reliable Datagram (Not supported for InfiniHost MT23108)
- 011-Unreliable Datagram
- 111-MLX transport (raw bits injection). Used for management QPs and RAW */
- pseudo_bit_t reserved3[0x00009];
- pseudo_bit_t state[0x00004]; /* QP/EE state:
- 0 - RST
- 1 - INIT
- 2 - RTR
- 3 - RTS
- 4 - SQEr
- 5 - SQD (Send Queue Drained)
- 6 - ERR
- 7 - Send Queue Draining
- 8 - F - RESERVED
- (Valid for QUERY_QPEE and ERR2RST_QPEE commands only) */
-/* -------------- */
- pseudo_bit_t sched_queue[0x00004]; /* Schedule queue to be used for WQE scheduling to execution. Determines QOS for this QP. */
- pseudo_bit_t reserved4[0x0001c];
-/* -------------- */
- pseudo_bit_t reserved5[0x00018];
- pseudo_bit_t msg_max[0x00005]; /* Max message size allowed on the QP. Maximum message size is 2^msg_Max.
- Must be equal to MTU for UD and MLX QPs. */
- pseudo_bit_t mtu[0x00003]; /* MTU of the QP (Must be the same for both paths: primary and alternative):
- 0x1 - 256 bytes
- 0x2 - 512
- 0x3 - 1024
- 0x4 - 2048
- other - reserved
-
- Should be configured to 0x4 for UD and MLX QPs. */
-/* -------------- */
- pseudo_bit_t usr_page[0x00018]; /* Index (offset) of user page allocated for this QP (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */
- pseudo_bit_t reserved6[0x00008];
-/* -------------- */
- pseudo_bit_t local_qpn_een[0x00018];/* Local QP/EE number Lower bits determine position of this record in QPC table, and - thus - constrained
- This field is valid for QUERY and ERR2RST commands only. */
- pseudo_bit_t reserved7[0x00008];
-/* -------------- */
- pseudo_bit_t remote_qpn_een[0x00018];/* Remote QP/EE number */
- pseudo_bit_t reserved8[0x00008];
-/* -------------- */
- pseudo_bit_t reserved9[0x00040];
-/* -------------- */
- struct tavorprm_address_path_st primary_address_path;/* Primary address path for the QP/EE */
-/* -------------- */
- struct tavorprm_address_path_st alternative_address_path;/* Alternate address path for the QP/EE */
-/* -------------- */
- pseudo_bit_t rdd[0x00018]; /* Reliable Datagram Domain */
- pseudo_bit_t reserved10[0x00008];
-/* -------------- */
- pseudo_bit_t pd[0x00018]; /* QP protection domain. Not valid (reserved) in EE context. */
- pseudo_bit_t reserved11[0x00008];
-/* -------------- */
- pseudo_bit_t wqe_base_adr[0x00020]; /* Bits 63:32 of WQE address for both SQ and RQ.
- Reserved for EE context. */
-/* -------------- */
- pseudo_bit_t wqe_lkey[0x00020]; /* memory key (L-Key) to be used to access WQEs. Not valid (reserved) in EE context. */
-/* -------------- */
- pseudo_bit_t reserved12[0x00003];
- pseudo_bit_t ssc[0x00001]; /* Send Signaled Completion
- 1 - all send WQEs generate CQEs.
- 0 - only send WQEs with C bit set generate completion.
- Not valid (reserved) in EE context. */
- pseudo_bit_t sic[0x00001]; /* If set - Ignore end to end credits on send queue. Not valid (reserved) in EE context. */
- pseudo_bit_t cur_retry_cnt[0x00003];/* Current transport retry counter (QUERY_QPEE only).
- The current transport retry counter can vary from retry_count down to 1, where 1 means that the last retry attempt is currently executing. */
- pseudo_bit_t cur_rnr_retry[0x00003];/* Current RNR retry counter (QUERY_QPEE only).
- The current RNR retry counter can vary from rnr_retry to 1, where 1 means that the last retry attempt is currently executing. */
- pseudo_bit_t reserved13[0x00002];
- pseudo_bit_t sae[0x00001]; /* If set - Atomic operations enabled on send queue. Not valid (reserved) in EE context. */
- pseudo_bit_t swe[0x00001]; /* If set - RDMA - write enabled on send queue. Not valid (reserved) in EE context. */
- pseudo_bit_t sre[0x00001]; /* If set - RDMA - read enabled on send queue. Not valid (reserved) in EE context. */
- pseudo_bit_t retry_count[0x00003]; /* Transport timeout Retry count */
- pseudo_bit_t reserved14[0x00002];
- pseudo_bit_t sra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */
- pseudo_bit_t flight_lim[0x00004]; /* Number of outstanding (in-flight) messages on the wire allowed for this send queue.
- Number of outstanding messages is 2^Flight_Lim.
- Use 0xF for unlimited number of outstanding messages. */
- pseudo_bit_t ack_req_freq[0x00004]; /* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */
-/* -------------- */
- pseudo_bit_t reserved15[0x00020];
-/* -------------- */
- pseudo_bit_t next_send_psn[0x00018];/* Next PSN to be sent */
- pseudo_bit_t reserved16[0x00008];
-/* -------------- */
- pseudo_bit_t cqn_snd[0x00018]; /* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */
- pseudo_bit_t reserved17[0x00008];
-/* -------------- */
- pseudo_bit_t next_snd_wqe_0[0x00020];/* Pointer and properties of next WQE on send queue. The format is same as next segment (first 8 bytes) in the WQE. This field is read-only and provided for debug purposes. Not valid (reserved) in EE context. */
-/* -------------- */
- pseudo_bit_t next_snd_wqe_1[0x00020];/* Pointer and properties of next WQE on send queue. The format is same as next segment (first 8 bytes) in the WQE. This field is read-only and provided for debug purposes. Not valid (reserved) in EE context. */
-/* -------------- */
- pseudo_bit_t last_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */
- pseudo_bit_t reserved18[0x00008];
-/* -------------- */
- pseudo_bit_t ssn[0x00018]; /* Requester Send Sequence Number (QUERY_QPEE only) */
- pseudo_bit_t reserved19[0x00008];
-/* -------------- */
- pseudo_bit_t reserved20[0x00003];
- pseudo_bit_t rsc[0x00001]; /* 1 - all receive WQEs generate CQEs.
- 0 - only receive WQEs with C bit set generate completion.
- Not valid (reserved) in EE context.
- */
- pseudo_bit_t ric[0x00001]; /* Invalid Credits.
- 1 - place "Invalid Credits" to ACKs sent from this queue.
- 0 - ACKs report the actual number of end to end credits on the connection.
- Not valid (reserved) in EE context.
- Must be set to 1 on QPs which are attached to SRQ. */
- pseudo_bit_t reserved21[0x00008];
- pseudo_bit_t rae[0x00001]; /* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */
- pseudo_bit_t rwe[0x00001]; /* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */
- pseudo_bit_t rre[0x00001]; /* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */
- pseudo_bit_t reserved22[0x00005];
- pseudo_bit_t rra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max.
- Must be 0 for EE context. */
- pseudo_bit_t reserved23[0x00008];
-/* -------------- */
- pseudo_bit_t next_rcv_psn[0x00018]; /* Next (expected) PSN on receive */
- pseudo_bit_t min_rnr_nak[0x00005]; /* Minimum RNR NAK timer value (TTTTT field encoding according to the IB spec Vol1 9.7.5.2.8).
- Not valid (reserved) in EE context. */
- pseudo_bit_t reserved24[0x00003];
-/* -------------- */
- pseudo_bit_t reserved25[0x00005];
- pseudo_bit_t ra_buff_indx[0x0001b]; /* Index to outstanding read/atomic buffer.
- This field constructs the address to the RDB for maintaining the incoming RDMA read and atomic requests. */
-/* -------------- */
- pseudo_bit_t cqn_rcv[0x00018]; /* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */
- pseudo_bit_t reserved26[0x00008];
-/* -------------- */
- pseudo_bit_t next_rcv_wqe_0[0x00020];/* Pointer and properties of next WQE on the receive queue. This format is same as next segment (first 8 bytes) in the WQE.This field is read-only and provided for debug purposes. Not valid (reserved) in EE context. */
-/* -------------- */
- pseudo_bit_t next_rcv_wqe_1[0x00020];/* Pointer and properties of next WQE on the receive queue. This format is same as next segment (first 8 bytes) in the WQE.This field is read-only and provided for debug purposes. Not valid (reserved) in EE context. */
-/* -------------- */
- pseudo_bit_t q_key[0x00020]; /* Q_Key to be validated against received datagrams.
- On send datagrams, if Q_Key[31] specified in the WQE is set, then this Q_Key will be transmitted in the outgoing message.
- Not valid (reserved) in EE context. */
-/* -------------- */
- pseudo_bit_t srqn[0x00018]; /* SRQN - Shared Receive Queue Number - specifies the SRQ number from which the QP dequeues receive descriptors.
- SRQN is valid only if SRQ bit is set. Not valid (reserved) in EE context. */
- pseudo_bit_t srq[0x00001]; /* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */
- pseudo_bit_t reserved27[0x00007];
-/* -------------- */
- pseudo_bit_t rmsn[0x00018]; /* Responder current message sequence number (QUERY_QPEE only) */
- pseudo_bit_t reserved28[0x00008];
-/* -------------- */
- pseudo_bit_t reserved29[0x00260];
-/* -------------- */
-};
-
-/* MOD_STAT_CFG */
-
-struct tavorprm_mod_stat_cfg_st { /* Little Endian */
- pseudo_bit_t log_max_srqs[0x00005]; /* Log (base 2) of the number of SRQs to allocate (0 if no SRQs are required), valid only if srq bit is set. */
- pseudo_bit_t reserved0[0x00001];
- pseudo_bit_t srq[0x00001]; /* When set SRQs are supported */
- pseudo_bit_t srq_m[0x00001]; /* Modify SRQ parameters */
- pseudo_bit_t reserved1[0x00018];
-/* -------------- */
- pseudo_bit_t reserved2[0x007e0];
-/* -------------- */
-};
-
-/* SRQ Context */
-
-struct tavorprm_srq_context_st { /* Little Endian */
- pseudo_bit_t wqe_addr_h[0x00020]; /* WQE base address for the SRQ [63:32]
- Must be set at SW2HW_SRQ */
-/* -------------- */
- pseudo_bit_t ds[0x00006]; /* Descriptor Size on the SRQ in units of 16 bytes */
- pseudo_bit_t next_wqe_addr_l[0x0001a];/* Next WQE address for the SRQ [31:6]
- Valid only on QUERY_SRQ and HW2SW_SRQ commands. */
-/* -------------- */
- pseudo_bit_t pd[0x00018]; /* SRQ PD - used for descriptor fetching on the SRQ and for data scatter on send operations on QPs attached to SRQ.
- In InfiniHost MT23108 SRQ.PD must be equal to the PD of all QPs which are attached to the SRQ */
- pseudo_bit_t reserved0[0x00004];
- pseudo_bit_t state[0x00004]; /* SRQ State:
- 1111 - SW Ownership
- 0000 - HW Ownership
- 0001 - Error
- Valid only on QUERY_SRQ and HW2SW_SRQ commands. */
-/* -------------- */
- pseudo_bit_t l_key[0x00020]; /* L_Key for descriptor fetching on the SRQ */
-/* -------------- */
- pseudo_bit_t uar[0x00018]; /* SRQ User Access Region - Index (offset) of user page allocated for the SRQ (see "Non Privileged Access to the HCA HW"). */
- pseudo_bit_t reserved1[0x00008];
-/* -------------- */
- pseudo_bit_t wqe_cnt[0x00010]; /* WQE count on the SRQ.
- Valid only on QUERY_SRQ and HW2SW_SRQ commands. */
- pseudo_bit_t lwm[0x00010]; /* Limit Water Mark - if the LWM is not zero, and the wqe_cnt drops below LWM when a WQE is dequeued from the SRQ, then a SRQ limit event is fired and the LWM is set to zero. */
-/* -------------- */
- pseudo_bit_t reserved2[0x00010];
- pseudo_bit_t reserved3[0x00010];
-/* -------------- */
- pseudo_bit_t reserved4[0x00020];
-/* -------------- */
-};
-
-/* InfiniHost Configuration Registers */
-
-struct tavorprm_mt23108_configuration_registers_st { /* Little Endian */
- pseudo_bit_t reserved0[0x403400];
-/* -------------- */
- struct tavorprm_hca_command_register_st hca_command_interface_register;/* HCA Command Register */
-/* -------------- */
- pseudo_bit_t reserved1[0x00320];
-/* -------------- */
- pseudo_bit_t ecr_h[0x00020]; /* Event Cause Register[63:32]. Each bit in the ECR corresponds to one of the 64 Event Queues in InfiniHost. If bit is set, interrupt was asserted due to event reported on corresponding event queue. This register is read-only; writing to this register will cause undefined results
- */
-/* -------------- */
- pseudo_bit_t ecr_l[0x00020]; /* Event Cause Register[31:0]. Each bit in the ECR corresponds to one of the 64 Event Queues in InfiniHost. If bit is set, interrupt was asserted due to event reported on corresponding event queue. This register is read-only; writing to this register will cause undefined results
- */
-/* -------------- */
- pseudo_bit_t clr_ecr_h[0x00020]; /* Clear Event Cause Register[63:32].
- This register is used to clear bits in ECR register. Each set bit in data written to this register clears corresponding bit in the ECR register, Each bit written with zero has no effect. This register is write-only. Reading from this register will cause undefined result
- */
-/* -------------- */
- pseudo_bit_t clr_ecr_l[0x00020]; /* Clear Event Cause Register[31:0].
- This register is used to clear bits in ECR register. Each set bit in data written to this register clears corresponding bit in the ECR register, Each bit written with zero has no effect. This register is write-only. Reading from this register will cause undefined result
- */
-/* -------------- */
- pseudo_bit_t reserved2[0x4c780];
-/* -------------- */
- pseudo_bit_t reserved3[0x01000];
-/* -------------- */
- pseudo_bit_t reserved4[0x32f6c0];
-/* -------------- */
- pseudo_bit_t clr_int_h[0x00020]; /* Clear Interrupt [63:32]
- This register is used to clear (de-assert) interrupt output pins of InfiniHost. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. This register is write-only. Reading from this register will cause undefined result */
-/* -------------- */
- pseudo_bit_t clr_int_l[0x00020]; /* Clear Interrupt [31:0]
- This register is used to clear (de-assert) interrupt output pins of InfiniHost. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. This register is write-only. Reading from this register will cause undefined result */
-/* -------------- */
- pseudo_bit_t reserved5[0x7f900];
-/* -------------- */
-};
-
-/* Schedule queues configuration */
-
-struct tavorprm_cfg_schq_st { /* Little Endian */
- pseudo_bit_t quota[0x00008]; /* Number of WQEs that are executed until preemption of the scheduling queue and switching to the next schedule queue */
- pseudo_bit_t reserved0[0x00018];
-/* -------------- */
- pseudo_bit_t rqsq0[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq0[0x00008]; /* Weight for responder schedule queue */
- pseudo_bit_t rqsq1[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq1[0x00008]; /* Weight for responder schedule queue */
-/* -------------- */
- pseudo_bit_t rqsq2[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq2[0x00008]; /* Weight for responder schedule queue */
- pseudo_bit_t rqsq3[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq3[0x00008]; /* Weight for responder schedule queue */
-/* -------------- */
- pseudo_bit_t rqsq4[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq4[0x00008]; /* Weight for responder schedule queue */
- pseudo_bit_t rqsq5[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq5[0x00008]; /* Weight for responder schedule queue */
-/* -------------- */
- pseudo_bit_t rqsq6[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq6[0x00008]; /* Weight for responder schedule queue */
- pseudo_bit_t rqsq7[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq7[0x00008]; /* Weight for responder schedule queue */
-/* -------------- */
- pseudo_bit_t rqsq8[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq8[0x00008]; /* Weight for responder schedule queue */
- pseudo_bit_t rqsq9[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq9[0x00008]; /* Weight for responder schedule queue */
-/* -------------- */
- pseudo_bit_t rqsq10[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq10[0x00008]; /* Weight for responder schedule queue */
- pseudo_bit_t rqsq11[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq11[0x00008]; /* Weight for responder schedule queue */
-/* -------------- */
- pseudo_bit_t rqsq12[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq12[0x00008]; /* Weight for responder schedule queue */
- pseudo_bit_t rqsq13[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq13[0x00008]; /* Weight for responder schedule queue */
-/* -------------- */
- pseudo_bit_t rqsq14[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq14[0x00008]; /* Weight for responder schedule queue */
- pseudo_bit_t rqsq15[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq15[0x00008]; /* Weight for responder schedule queue */
-/* -------------- */
- pseudo_bit_t rqsq16[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq16[0x00008]; /* Weight for responder schedule queue */
- pseudo_bit_t rqsq17[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq17[0x00008]; /* Weight for responder schedule queue */
-/* -------------- */
- pseudo_bit_t rqsq18[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq18[0x00008]; /* Weight for responder schedule queue */
- pseudo_bit_t rqsq19[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq19[0x00008]; /* Weight for responder schedule queue */
-/* -------------- */
- pseudo_bit_t rqsq20[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq20[0x00008]; /* Weight for responder schedule queue */
- pseudo_bit_t rqsq21[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq21[0x00008]; /* Weight for responder schedule queue */
-/* -------------- */
- pseudo_bit_t rqsq22[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq22[0x00008]; /* Weight for responder schedule queue */
- pseudo_bit_t rqsq23[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq23[0x00008]; /* Weight for responder schedule queue */
-/* -------------- */
- pseudo_bit_t rqsq24[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq24[0x00008]; /* Weight for responder schedule queue */
- pseudo_bit_t rqsq25[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq25[0x00008]; /* Weight for responder schedule queue */
-/* -------------- */
- pseudo_bit_t rqsq26[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq26[0x00008]; /* Weight for responder schedule queue */
- pseudo_bit_t rqsq27[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq27[0x00008]; /* Weight for responder schedule queue */
-/* -------------- */
- pseudo_bit_t rqsq28[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq28[0x00008]; /* Weight for responder schedule queue */
- pseudo_bit_t rqsq29[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq29[0x00008]; /* Weight for responder schedule queue */
-/* -------------- */
- pseudo_bit_t rqsq30[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq30[0x00008]; /* Weight for responder schedule queue */
- pseudo_bit_t rqsq31[0x00008]; /* Weight for requestor schedule queue */
- pseudo_bit_t rssq31[0x00008]; /* Weight for responder schedule queue */
-/* -------------- */
- pseudo_bit_t reserved1[0x005e0];
-/* -------------- */
-};
-
-/* Query BAR */
-
-struct tavorprm_query_bar_st { /* Little Endian */
- pseudo_bit_t bar_base_h[0x00020]; /* BAR base [63:32] */
-/* -------------- */
- pseudo_bit_t reserved0[0x00014];
- pseudo_bit_t bar_base_l[0x0000c]; /* BAR base [31:20] */
-/* -------------- */
-};
-
-/* Performance Counters */
-
-struct tavorprm_performance_counters_st { /* Little Endian */
- pseudo_bit_t sqpc_access_cnt[0x00020];/* SQPC cache access count */
-/* -------------- */
- pseudo_bit_t sqpc_miss_cnt[0x00020];/* SQPC cache miss count */
-/* -------------- */
- pseudo_bit_t reserved0[0x00040];
-/* -------------- */
- pseudo_bit_t rqpc_access_cnt[0x00020];/* RQPC cache access count */
-/* -------------- */
- pseudo_bit_t rqpc_miss_cnt[0x00020];/* RQPC cache miss count */
-/* -------------- */
- pseudo_bit_t reserved1[0x00040];
-/* -------------- */
- pseudo_bit_t cqc_access_cnt[0x00020];/* CQC cache access count */
-/* -------------- */
- pseudo_bit_t cqc_miss_cnt[0x00020]; /* CQC cache miss count */
-/* -------------- */
- pseudo_bit_t reserved2[0x00040];
-/* -------------- */
- pseudo_bit_t tpt_access_cnt[0x00020];/* TPT cache access count */
-/* -------------- */
- pseudo_bit_t mpt_miss_cnt[0x00020]; /* MPT cache miss count */
-/* -------------- */
- pseudo_bit_t mtt_miss_cnt[0x00020]; /* MTT cache miss count */
-/* -------------- */
- pseudo_bit_t reserved3[0x00620];
-/* -------------- */
-};
-
-/* Transport and CI Error Counters */
-
-struct tavorprm_transport_and_ci_error_counters_st { /* Little Endian */
- pseudo_bit_t rq_num_lle[0x00020]; /* Responder - number of local length errors.
- Local Length Errors: Inbound "Send" request message exceeded the responders available buffer space. */
-/* -------------- */
- pseudo_bit_t sq_num_lle[0x00020]; /* Requester - number of local length errors.
- Length Errors: RDMA READ response message contained too much or too little payload data. */
-/* -------------- */
- pseudo_bit_t rq_num_lqpoe[0x00020]; /* Responder - number local QP operation error.
- 1. Malformed WQE: Responder detected a malformed Receive Queue WQE while processing the packet.
- 2. Local QP Error: Responder detected a local QP related error while executing the request message. The local error prevented the responder from completing the request. */
-/* -------------- */
- pseudo_bit_t sq_num_lqpoe[0x00020]; /* Requester - number local QP operation error
- 1. Local Operation Error: (WQE gather, affiliated or unaffiliated): An error occurred in the requesters local channel interface that either cannot be associated with a certain WQE, or occurred when reading a WQE.
- */
-/* -------------- */
- pseudo_bit_t rq_num_leeoe[0x00020]; /* Responder - number local EE operation error.
- RD */
-/* -------------- */
- pseudo_bit_t sq_num_leeoe[0x00020]; /* Requester - number local EE operation error.
- RD */
-/* -------------- */
- pseudo_bit_t rq_num_lpe[0x00020]; /* Responder - number of local protection errors.
- Local QP (Protection) Error: Responder detected a local access violation error while executing a send request message. The error prevented the responder from completing the request. */
-/* -------------- */
- pseudo_bit_t sq_num_lpe[0x00020]; /* Requester - number of local protection errors.
- Local Memory Protection Error: Requester detected a memory translation/protection (TPT) error.
- */
-/* -------------- */
- pseudo_bit_t rq_num_wrfe[0x00020]; /* Responder - number of CQEs with error generated. */
-/* -------------- */
- pseudo_bit_t sq_num_wrfe[0x00020]; /* Requester - number of CQEs with error generated. */
-/* -------------- */
- pseudo_bit_t reserved0[0x00020];
-/* -------------- */
- pseudo_bit_t sq_num_mwbe[0x00020]; /* Requester - number of memory window bind errors. */
-/* -------------- */
- pseudo_bit_t reserved1[0x00020];
-/* -------------- */
- pseudo_bit_t sq_num_bre[0x00020]; /* Requester - number of bad response errors.
- Bad response: Unexpected opcode for the response packet received at the expected response PSN. */
-/* -------------- */
- pseudo_bit_t rq_num_lae[0x00020]; /* Responder - number of local access errors.
- Unused. */
-/* -------------- */
- pseudo_bit_t reserved2[0x00040];
-/* -------------- */
- pseudo_bit_t sq_num_rire[0x00020]; /* Requester - number of remote invalid request errors.
- NAK-Invalid Request on:
- 1. Unsupported OpCode: Responder detected an unsupported OpCode.
- 2. Unexpected OpCode: Responder detected an error in the sequence of OpCodes, such as a missing "Last" packet.
- Note: there is no PSN error, thus this does not indicate a dropped packet. */
-/* -------------- */
- pseudo_bit_t rq_num_rire[0x00020]; /* Responder - number of remote invalid request errors.
- NAK may or may not be sent.
- 1. Unsupported or Reserved OpCode: Inbound request OpCode was either reserved, or was for a function not supported by this QP. (E.G. RDMA or ATOMIC on QP not set up for this). For RC this is "QP Async affiliated".
- 2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic operation.
- 3. Too many RDMA READ or ATOMIC Requests: There were more requests received and not ACKed than allowed for the connection.
- 4. Out of Sequence OpCode, current packet is "first" or "Only": The Responder detected an error in the sequence of OpCodes; a missing "Last" packet
- 5. Out of Sequence OpCode, current packet is not "first" or "Only": The Responder detected an error in the sequence of OpCodes; a missing "First" packet
- 6. Local Length Error: Inbound "Send" request message exceeded the responder.s available buffer space.
- 7. Length error: RDMA WRITE request message contained too much or too little payload data compared to the DMA length advertised in the first or only packet.
- 8. Length error: Payload length was not consistent with the opcode:
- a: 0 byte <= "only" <= PMTU bytes
- b: ("first" or "middle") == PMTU bytes
- c: 1byte <= "last" <= PMTU bytes
- 9. Length error: Inbound message exceeded the size supported by the CA port. */
-/* -------------- */
- pseudo_bit_t sq_num_rae[0x00020]; /* Requester - number of remote access errors.
- NAK-Remote Access Error on:
- R_Key Violation: Responder detected an invalid R_Key while executing an RDMA Request. */
-/* -------------- */
- pseudo_bit_t rq_num_rae[0x00020]; /* Responder - number of remote access errors.
- R_Key Violation Responder detected an R_Key violation while executing an RDMA request.
- NAK may or may not be sent. */
-/* -------------- */
- pseudo_bit_t sq_num_roe[0x00020]; /* Requester - number of remote operation errors.
- NAK-Remote Operation Error on:
- Remote Operation Error: Responder encountered an error, (local to the responder), which prevented it from completing the request. */
-/* -------------- */
- pseudo_bit_t rq_num_roe[0x00020]; /* Responder - number of remote operation errors.
- NAK-Remote Operation Error on:
- 1. Malformed WQE: Responder detected a malformed Receive Queue WQE while processing the packet.
- 2. Remote Operation Error: Responder encountered an error, (local to the responder), which prevented it from completing the request. */
-/* -------------- */
- pseudo_bit_t sq_num_tree[0x00020]; /* Requester - number of transport retries exceeded errors.
- 1. Packet sequence error: Retry limit exceeded. Responder detected a PSN larger than it expected. The requestor performed retries, and automatic path migration and additional retries, if applicable, but all attempts failed.
- 2. Implied NAK sequence error: Retry limit exceeded. Requestor detected an ACK with a PSN larger than the expected PSN for an RDMA READ or atomic response. The requestor performed retries, and automatic path migration and additional retries, if applicable, but all attempts failed.
- 3. Local Ack Timeout error: Retry limit exceeded. No ACK response within timer interval. The requestor performed retries, and automatic path migration and additional retries, but all attempts failed. */
-/* -------------- */
- pseudo_bit_t reserved3[0x00020];
-/* -------------- */
- pseudo_bit_t sq_num_rree[0x00020]; /* Requester - number of RNR nak retries exceeded errors.
- RNR NAK Retry error. Retry limit exceeded. Excessive RNR NAKs returned by the responder: Requestor retried the request "n" times, but received RNR NAK each time. */
-/* -------------- */
- pseudo_bit_t reserved4[0x00020];
-/* -------------- */
- pseudo_bit_t sq_num_lrdve[0x00020]; /* Requester - number of local RDD violation errors.
- RD only. */
-/* -------------- */
- pseudo_bit_t rq_num_rirdre[0x00020];/* Responder - number of remote invalid RD request errors.
- RD only. */
-/* -------------- */
- pseudo_bit_t reserved5[0x00040];
-/* -------------- */
- pseudo_bit_t sq_num_rabrte[0x00020];/* Requester - number of remote aborted errors.
- RD only. */
-/* -------------- */
- pseudo_bit_t reserved6[0x00020];
-/* -------------- */
- pseudo_bit_t sq_num_ieecne[0x00020];/* Requester - number of invalid EE context number errors.
- RD only. */
-/* -------------- */
- pseudo_bit_t reserved7[0x00020];
-/* -------------- */
- pseudo_bit_t sq_num_ieecse[0x00020];/* Requester - invalid EE context state errors.
- RD only. */
-/* -------------- */
- pseudo_bit_t reserved8[0x00380];
-/* -------------- */
- pseudo_bit_t rq_num_oos[0x00020]; /* Responder - number of out of sequence requests received.
- Out of Sequence Request Packet: Packet PSN of the inbound request is outside the responders valid PSN window.
- NAK may or may not be sent. */
-/* -------------- */
- pseudo_bit_t sq_num_oos[0x00020]; /* Requester - number of out of sequence Naks received.
- NAK-Sequence Error on:
- 1. Packet sequence error. Retry limit not exceeded: Responder detected a PSN larger than it expected. Requester may retry the request.
- 2. Packet sequence error. Retry limit exceeded: Responder detected a PSN larger than it expected. The requestor performed retries, and automatic path migration and additional retries, if applicable, but all attempts failed. */
-/* -------------- */
- pseudo_bit_t rq_num_mce[0x00020]; /* Responder - number of bad multicast packets received.
- Missing GID or bad GID. */
-/* -------------- */
- pseudo_bit_t reserved9[0x00020];
-/* -------------- */
- pseudo_bit_t rq_num_rsync[0x00020]; /* Responder - number of RESYNC operations.
- RD only. */
-/* -------------- */
- pseudo_bit_t sq_num_rsync[0x00020]; /* Requester - number of RESYNC operations.
- RD only. */
-/* -------------- */
- pseudo_bit_t rq_num_udsdprd[0x00020];/* The number of UD packets silently discarded on the receive queue due to lack of receive descriptor.
- Resources Not Ready Error: A UD WQE is not currently available. */
-/* -------------- */
- pseudo_bit_t reserved10[0x00020];
-/* -------------- */
- pseudo_bit_t rq_num_ucsdprd[0x00020];/* The number of UC packets silently discarded on the receive queue due to lack of receive descriptor.
- Resources Not Ready Error: A UC WQE is not currently available. */
-/* -------------- */
- pseudo_bit_t reserved11[0x003e0];
-/* -------------- */
- pseudo_bit_t num_cqovf[0x00020]; /* Number of CQ overflows.
- Incremented each time a completion is discarded due CQ overflow. */
-/* -------------- */
- pseudo_bit_t num_eqovf[0x00020]; /* Number of EQ overflows.
- Incremented each time EQ enters the overflow state. */
-/* -------------- */
- pseudo_bit_t num_baddb[0x00020]; /* Number of bad doorbells.
- Doorbell dropped due to UAR violation or bad resource state. */
-/* -------------- */
- pseudo_bit_t reserved12[0x002a0];
-/* -------------- */
-};
-
-/* Event_data Field - HCR Completion Event */
-
-struct tavorprm_hcr_completion_event_st { /* Little Endian */
- pseudo_bit_t token[0x00010]; /* HCR Token */
- pseudo_bit_t reserved0[0x00010];
-/* -------------- */
- pseudo_bit_t reserved1[0x00020];
-/* -------------- */
- pseudo_bit_t status[0x00008]; /* HCR Status */
- pseudo_bit_t reserved2[0x00018];
-/* -------------- */
- pseudo_bit_t out_param_h[0x00020]; /* HCR Output Parameter [63:32] */
-/* -------------- */
- pseudo_bit_t out_param_l[0x00020]; /* HCR Output Parameter [31:0] */
-/* -------------- */
- pseudo_bit_t reserved3[0x00020];
-/* -------------- */
-};
-
-/* Completion with Error CQE */
-
-struct tavorprm_completion_with_error_st { /* Little Endian */
- pseudo_bit_t myqpn[0x00018]; /* Indicates the QP for which completion is being reported */
- pseudo_bit_t reserved0[0x00008];
-/* -------------- */
- pseudo_bit_t reserved1[0x00060];
-/* -------------- */
- pseudo_bit_t db_cnt[0x00010]; /* Doorbell count */
- pseudo_bit_t reserved2[0x00008];
- pseudo_bit_t syndrome[0x00008]; /* Completion with error syndrome:
- 0x01 - Local Length Error
- 0x02 - Local QP Operation Error
- 0x03 - Local EE Context Operation Error
- 0x04 - Local Protection Error
- 0x05 - Work Request Flushed Error
- 0x06 - Memory Window Bind Error
- 0x10 - Bad Response Error
- 0x11 - Local Access Error
- 0x12 - Remote Invalid Request Error
- 0x13 - Remote Access Error
- 0x14 - Remote Operation Error
- 0x15 - Transport Retry Counter Exceeded
- 0x16 - RNR Retry Counter Exceeded
- 0x20 - Local RDD Violation Error
- 0x21 - Remote Invalid RD Request
- 0x22 - Remote Aborted Error
- 0x23 - Invalid EE Context Number
- 0x24 - Invalid EE Context State
- other - Reserved
- Syndrome is defined according to the IB specification volume 1. For detailed explanation of the syndromes, refer to chapters 10-11 of the IB specification rev 1.1. */
-/* -------------- */
- pseudo_bit_t reserved3[0x00020];
-/* -------------- */
- pseudo_bit_t wqe_size[0x00006]; /* Size (in 16-byte chunks) of WQE completion is reported for */
- pseudo_bit_t wqe_addr[0x0001a]; /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */
-/* -------------- */
- pseudo_bit_t reserved4[0x00007];
- pseudo_bit_t owner[0x00001]; /* Owner field. Zero value of this field means SW ownership of CQE. */
- pseudo_bit_t reserved5[0x00010];
- pseudo_bit_t opcode[0x00008]; /* The opcode of WQE completion is reported for.
-
- The following values are reported in case of completion with error:
- 0xFE - For completion with error on Receive Queues
- 0xFF - For completion with error on Send Queues */
-/* -------------- */
-};
-
-/* Resize CQ Input Mailbox */
-
-struct tavorprm_resize_cq_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00020];
-/* -------------- */
- pseudo_bit_t start_addr_h[0x00020]; /* Start address of CQ[63:32].
- Must be aligned on CQE size (32 bytes) */
-/* -------------- */
- pseudo_bit_t start_addr_l[0x00020]; /* Start address of CQ[31:0].
- Must be aligned on CQE size (32 bytes) */
-/* -------------- */
- pseudo_bit_t reserved1[0x00018];
- pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries) */
- pseudo_bit_t reserved2[0x00003];
-/* -------------- */
- pseudo_bit_t reserved3[0x00060];
-/* -------------- */
- pseudo_bit_t l_key[0x00020]; /* Memory key (L_Key) to be used to access CQ */
-/* -------------- */
- pseudo_bit_t reserved4[0x00100];
-/* -------------- */
-};
-
-/* SYS_EN Output Parameter */
-
-struct tavorprm_sys_en_out_param_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00020];
-/* -------------- */
- pseudo_bit_t spd[0x00001]; /* 0 - DIMM SPD was read from DIMM
- 1 - DIMM SPD was read from InfiniHost NVMEM */
- pseudo_bit_t sladr[0x00003]; /* SPD Slave Address 3 LSBits.
- Valid only if spd bit is 0. */
- pseudo_bit_t sock_num[0x00002]; /* DIMM socket number (for double sided DIMM one of the two numbers will be reported) */
- pseudo_bit_t syn[0x00004]; /* Error Syndrome
- 0 - reserved
- 1 - SPD error (e.g. checksum error, no response, error while reading)
- 2 - DIMM out of bounds (e.g. DIMM rows number is not between 7 and 14, DIMM type is not 2)
- 3 - DIMM conflict (e.g. mix of registered and unbuffered DIMMs, CAS latency conflict)
- 4 - Calibration error
- 5 - reserved
- 6- DDR Memory check failed
- other - Error, reserved */
- pseudo_bit_t reserved1[0x00016];
-/* -------------- */
-};
-
-/* Query Debug Message */
-
-struct tavorprm_query_debug_msg_st { /* Little Endian */
- pseudo_bit_t base_addr_h[0x00020]; /* Debug Buffers Base Address [63:32] */
-/* -------------- */
- pseudo_bit_t base_addr_l[0x00020]; /* Debug Buffers Base Address [31:0] */
-/* -------------- */
- pseudo_bit_t buf_sz[0x00020]; /* Debug Buffer Size (in bytes) */
-/* -------------- */
- pseudo_bit_t reserved0[0x00020];
-/* -------------- */
- pseudo_bit_t trc_hdr_sz[0x00020]; /* Trace message header size in dwords. */
-/* -------------- */
- pseudo_bit_t trc_arg_num[0x00020]; /* The number of arguments per trace message. */
-/* -------------- */
- pseudo_bit_t reserved1[0x000c0];
-/* -------------- */
- pseudo_bit_t dbg_msk_h[0x00020]; /* Debug messages mask [63:32] */
-/* -------------- */
- pseudo_bit_t dbg_msk_l[0x00020]; /* Debug messages mask [31:0] */
-/* -------------- */
- pseudo_bit_t reserved2[0x00040];
-/* -------------- */
- pseudo_bit_t fs_base_addr0_h[0x00020];/* Base address for format string for irisc 0 bits[63:32] */
-/* -------------- */
- pseudo_bit_t fs_base_addr0_l[0x00020];/* Base address for format string for irisc 0 bits[31:0] */
-/* -------------- */
- pseudo_bit_t fs_base_addr1_h[0x00020];/* Base address for format string for irisc 1 bits[63:32] */
-/* -------------- */
- pseudo_bit_t fs_base_addr1_l[0x00020];/* Base address for format string for irisc 1 bits[31:0] */
-/* -------------- */
- pseudo_bit_t fs_base_addr2_h[0x00020];/* Base address for format string for irisc 2 bits[63:32] */
-/* -------------- */
- pseudo_bit_t fs_base_addr2_l[0x00020];/* Base address for format string for irisc 2 bits[31:0] */
-/* -------------- */
- pseudo_bit_t fs_base_addr3_h[0x00020];/* Base address for format string for irisc 3 bits[63:32] */
-/* -------------- */
- pseudo_bit_t fs_base_addr3_l[0x00020];/* Base address for format string for irisc 3 bits[31:0] */
-/* -------------- */
- pseudo_bit_t fs_base_addr4_h[0x00020];/* Base address for format string for irisc 4 bits[63:32] */
-/* -------------- */
- pseudo_bit_t fs_base_addr4_l[0x00020];/* Base address for format string for irisc 4 bits[31:0] */
-/* -------------- */
- pseudo_bit_t fs_base_addr5_h[0x00020];/* Base address for format string for irisc 5 bits[63:32] */
-/* -------------- */
- pseudo_bit_t fs_base_addr5_l[0x00020];/* Base address for format string for irisc 5 bits[31:0] */
-/* -------------- */
- pseudo_bit_t reserved3[0x00480];
-/* -------------- */
-};
-
-/* User Access Region */
-
-struct tavorprm_uar_st { /* Little Endian */
- struct tavorprm_rd_send_doorbell_st rd_send_doorbell;/* Reliable Datagram SQ Doorbell */
-/* -------------- */
- struct tavorprm_send_doorbell_st send_doorbell;/* SQ Doorbell */
-/* -------------- */
- struct tavorprm_receive_doorbell_st receive_doorbell;/* RQ Doorbell */
-/* -------------- */
- struct tavorprm_cq_cmd_doorbell_st cq_command_doorbell;/* CQ Doorbell */
-/* -------------- */
- struct tavorprm_eq_cmd_doorbell_st eq_command_doorbell;/* EQ Doorbell */
-/* -------------- */
- pseudo_bit_t reserved0[0x01e80];
-/* -------------- */
- pseudo_bit_t infini_blast[256][0x00020];/* InfiniBlast buffer (same format as WQE format)
- Infiniblast is not supported by InfiniHost MT23108 */
-/* -------------- */
-};
-
-/* SET_IB Parameters */
-
-struct tavorprm_set_ib_st { /* Little Endian */
- pseudo_bit_t rqk[0x00001]; /* Reset QKey Violation Counter */
- pseudo_bit_t reserved0[0x00011];
- pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified.
- system_image_guid and sig must be the same for all ports. */
- pseudo_bit_t reserved1[0x0000d];
-/* -------------- */
- pseudo_bit_t capability_mask[0x00020];/* PortInfo Capability Mask */
-/* -------------- */
- pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set
- Must be the same for both ports. */
-/* -------------- */
- pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set
- Must be the same for both ports. */
-/* -------------- */
- pseudo_bit_t reserved2[0x00180];
-/* -------------- */
-};
-
-/* Multicast Group Member */
-
-struct tavorprm_mgm_entry_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00006];
- pseudo_bit_t next_gid_index[0x0001a];/* Index of next Multicast Group Member whose GID maps to same MGID_HASH number.
- The index is into the Multicast Group Table, which is the comprised the MGHT and AMGM tables.
- next_gid_index=0 means end of the chain. */
-/* -------------- */
- pseudo_bit_t reserved1[0x00060];
-/* -------------- */
- pseudo_bit_t mgid_128_96[0x00020]; /* Multicast group GID[128:96] in big endian format.
- Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
-/* -------------- */
- pseudo_bit_t mgid_95_64[0x00020]; /* Multicast group GID[95:64] in big endian format.
- Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
-/* -------------- */
- pseudo_bit_t mgid_63_32[0x00020]; /* Multicast group GID[63:32] in big endian format.
- Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
-/* -------------- */
- pseudo_bit_t mgid_31_0[0x00020]; /* Multicast group GID[31:0] in big endian format.
- Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
-/* -------------- */
- struct tavorprm_mgmqp_st mgmqp_0; /* Multicast Group Member QP */
-/* -------------- */
- struct tavorprm_mgmqp_st mgmqp_1; /* Multicast Group Member QP */
-/* -------------- */
- struct tavorprm_mgmqp_st mgmqp_2; /* Multicast Group Member QP */
-/* -------------- */
- struct tavorprm_mgmqp_st mgmqp_3; /* Multicast Group Member QP */
-/* -------------- */
- struct tavorprm_mgmqp_st mgmqp_4; /* Multicast Group Member QP */
-/* -------------- */
- struct tavorprm_mgmqp_st mgmqp_5; /* Multicast Group Member QP */
-/* -------------- */
- struct tavorprm_mgmqp_st mgmqp_6; /* Multicast Group Member QP */
-/* -------------- */
- struct tavorprm_mgmqp_st mgmqp_7; /* Multicast Group Member QP */
-/* -------------- */
-};
-
-/* INIT_IB Parameters */
-
-struct tavorprm_init_ib_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00004];
- pseudo_bit_t vl_cap[0x00004]; /* Maximum VLs supported on the port, excluding VL15.
- Legal values are 1,2,4 and 8. */
- pseudo_bit_t port_width_cap[0x00004];/* IB Port Width
- 1 - 1x
- 3 - 1x, 4x
- 11 - 1x, 4x or 12x (must not be used in InfiniHost MT23108)
- else - Reserved */
- pseudo_bit_t mtu_cap[0x00004]; /* Maximum MTU Supported
- 0x0 - Reserved
- 0x1 - 256
- 0x2 - 512
- 0x3 - 1024
- 0x4 - 2048
- 0x5 - 0xF Reserved */
- pseudo_bit_t g0[0x00001]; /* Set port GUID0 to GUID0 specified */
- pseudo_bit_t ng[0x00001]; /* Set node GUID to node_guid specified.
- node_guid and ng must be the same for all ports. */
- pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified.
- system_image_guid and sig must be the same for all ports. */
- pseudo_bit_t reserved1[0x0000d];
-/* -------------- */
- pseudo_bit_t max_gid[0x00010]; /* Maximum number of GIDs for the port */
- pseudo_bit_t reserved2[0x00010];
-/* -------------- */
- pseudo_bit_t max_pkey[0x00010]; /* Maximum pkeys for the port.
- Must be the same for both ports. */
- pseudo_bit_t reserved3[0x00010];
-/* -------------- */
- pseudo_bit_t reserved4[0x00020];
-/* -------------- */
- pseudo_bit_t guid0_h[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 63:32) */
-/* -------------- */
- pseudo_bit_t guid0_l[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 31:0) */
-/* -------------- */
- pseudo_bit_t node_guid_h[0x00020]; /* Node GUID[63:32], takes effect only if the NG bit is set
- Must be the same for both ports. */
-/* -------------- */
- pseudo_bit_t node_guid_l[0x00020]; /* Node GUID[31:0], takes effect only if the NG bit is set
- Must be the same for both ports. */
-/* -------------- */
- pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set
- Must be the same for both ports. */
-/* -------------- */
- pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set
- Must be the same for both ports. */
-/* -------------- */
- pseudo_bit_t reserved5[0x006c0];
-/* -------------- */
-};
-
-/* Query Device Limitations */
-
-struct tavorprm_query_dev_lim_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00080];
-/* -------------- */
- pseudo_bit_t log_max_qp[0x00005]; /* Log2 of the Maximum number of QPs supported */
- pseudo_bit_t reserved1[0x00003];
- pseudo_bit_t log2_rsvd_qps[0x00004];/* Log (base 2) of the number of QPs reserved for firmware use
- The reserved resources are numbered from 0 to 2^log2_rsvd_qps-1 */
- pseudo_bit_t reserved2[0x00004];
- pseudo_bit_t log_max_qp_sz[0x00008];/* The maximum number of WQEs allowed on the RQ or the SQ is 2^log_max_qp_sz-1 */
- pseudo_bit_t log_max_srq_sz[0x00008];/* The maximum number of WQEs allowed on the SRQ is 2^log_max_srq_sz-1 */
-/* -------------- */
- pseudo_bit_t log_max_ee[0x00005]; /* Log2 of the Maximum number of EE contexts supported */
- pseudo_bit_t reserved3[0x00003];
- pseudo_bit_t log2_rsvd_ees[0x00004];/* Log (base 2) of the number of EECs reserved for firmware use
- The reserved resources are numbered from 0 to 2^log2_rsvd_ees-1 */
- pseudo_bit_t reserved4[0x00004];
- pseudo_bit_t log_max_srqs[0x00005]; /* Log base 2 of the maximum number of SRQs supported, valid only if SRQ bit is set.
- */
- pseudo_bit_t reserved5[0x00007];
- pseudo_bit_t log2_rsvd_srqs[0x00004];/* Log (base 2) of the number of reserved SRQs for firmware use
- The reserved resources are numbered from 0 to 2^log2_rsvd_srqs-1
- This parameter is valid only if the SRQ bit is set. */
-/* -------------- */
- pseudo_bit_t log_max_cq[0x00005]; /* Log2 of the Maximum number of CQs supported */
- pseudo_bit_t reserved6[0x00003];
- pseudo_bit_t log2_rsvd_cqs[0x00004];/* Log (base 2) of the number of CQs reserved for firmware use
- The reserved resources are numbered from 0 to 2^log2_rsrvd_cqs-1 */
- pseudo_bit_t reserved7[0x00004];
- pseudo_bit_t log_max_cq_sz[0x00008];/* Log2 of the Maximum CQEs allowed in a CQ */
- pseudo_bit_t reserved8[0x00008];
-/* -------------- */
- pseudo_bit_t log_max_eq[0x00003]; /* Log2 of the Maximum number of EQs */
- pseudo_bit_t reserved9[0x00005];
- pseudo_bit_t num_rsvd_eqs[0x00004]; /* The number of EQs reserved for firmware use
- The reserved resources are numbered from 0 to num_rsvd_eqs-1
- If 0 - no resources are reserved. */
- pseudo_bit_t reserved10[0x00004];
- pseudo_bit_t log_max_mpts[0x00006]; /* Log (base 2) of the maximum number of MPT entries (the number of Regions/Windows) */
- pseudo_bit_t reserved11[0x0000a];
-/* -------------- */
- pseudo_bit_t log_max_mtt_seg[0x00006];/* Log2 of the Maximum number of MTT segments */
- pseudo_bit_t reserved12[0x00002];
- pseudo_bit_t log2_rsvd_mrws[0x00004];/* Log (base 2) of the number of MPTs reserved for firmware use
- The reserved resources are numbered from 0 to 2^log2_rsvd_mrws-1 */
- pseudo_bit_t reserved13[0x00004];
- pseudo_bit_t log_max_mrw_sz[0x00008];/* Log2 of the Maximum Size of Memory Region/Window */
- pseudo_bit_t reserved14[0x00004];
- pseudo_bit_t log2_rsvd_mtts[0x00004];/* Log (base 2) of the number of MTT segments reserved for firmware use
- The reserved resources are numbered from 0 to 2^log2_rsvd_mtts-1
- */
-/* -------------- */
- pseudo_bit_t log_max_av[0x00006]; /* Log2 of the Maximum number of Address Vectors */
- pseudo_bit_t reserved15[0x0001a];
-/* -------------- */
- pseudo_bit_t log_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */
- pseudo_bit_t reserved16[0x0000a];
- pseudo_bit_t log_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */
- pseudo_bit_t reserved17[0x0000a];
-/* -------------- */
- pseudo_bit_t log_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */
- pseudo_bit_t reserved18[0x0001a];
-/* -------------- */
- pseudo_bit_t reserved19[0x00020];
-/* -------------- */
- pseudo_bit_t num_ports[0x00004]; /* Number of IB ports. */
- pseudo_bit_t max_vl[0x00004]; /* Maximum VLs supported on each port, excluding VL15 */
- pseudo_bit_t max_port_width[0x00004];/* IB Port Width
- 1 - 1x
- 3 - 1x, 4x
- 11 - 1x, 4x or 12x
- else - Reserved */
- pseudo_bit_t max_mtu[0x00004]; /* Maximum MTU Supported
- 0x0 - Reserved
- 0x1 - 256
- 0x2 - 512
- 0x3 - 1024
- 0x4 - 2048
- 0x5 - 0xF Reserved */
- pseudo_bit_t local_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb.
- The delay value in microseconds is computed using 4.096us * 2^(Local_CA_ACK_Delay). */
- pseudo_bit_t reserved20[0x0000b];
-/* -------------- */
- pseudo_bit_t log_max_gid[0x00004]; /* Log2 of the maximum number of GIDs per port */
- pseudo_bit_t reserved21[0x0001c];
-/* -------------- */
- pseudo_bit_t log_max_pkey[0x00004]; /* Log2 of the max PKey Table Size (per IB port) */
- pseudo_bit_t reserved22[0x0001c];
-/* -------------- */
- pseudo_bit_t reserved23[0x00020];
-/* -------------- */
- pseudo_bit_t rc[0x00001]; /* RC Transport supported */
- pseudo_bit_t uc[0x00001]; /* UC Transport Supported */
- pseudo_bit_t ud[0x00001]; /* UD Transport Supported */
- pseudo_bit_t rd[0x00001]; /* RD Transport Supported
- RD is not supported in InfiniHost MT23108 */
- pseudo_bit_t raw_ipv6[0x00001]; /* Raw IPv6 Transport Supported */
- pseudo_bit_t raw_ether[0x00001]; /* Raw Ethertype Transport Supported */
- pseudo_bit_t srq[0x00001]; /* SRQ is supported
- */
- pseudo_bit_t reserved24[0x00001];
- pseudo_bit_t pkv[0x00001]; /* PKey Violation Counter Supported */
- pseudo_bit_t qkv[0x00001]; /* QKey Violation Coutner Supported */
- pseudo_bit_t reserved25[0x00006];
- pseudo_bit_t mw[0x00001]; /* Memory windows supported */
- pseudo_bit_t apm[0x00001]; /* Automatic Path Migration Supported */
- pseudo_bit_t atm[0x00001]; /* Atomic operations supported (atomicity is guaranteed between QPs on this HCA) */
- pseudo_bit_t rm[0x00001]; /* Raw Multicast Supported */
- pseudo_bit_t avp[0x00001]; /* Address Vector Port checking supported */
- pseudo_bit_t udm[0x00001]; /* UD Multicast Supported */
- pseudo_bit_t reserved26[0x00002];
- pseudo_bit_t pg[0x00001]; /* Paging on demand supported */
- pseudo_bit_t r[0x00001]; /* Router mode supported */
- pseudo_bit_t reserved27[0x00006];
-/* -------------- */
- pseudo_bit_t log_pg_sz[0x00008]; /* Minimum system page size supported (log2) .
- For proper operation it must be less than or equal the hosting platform (CPU) minimum page size. */
- pseudo_bit_t reserved28[0x00008];
- pseudo_bit_t uar_sz[0x00006]; /* UAR Area Size = 1MB * 2^uar_sz */
- pseudo_bit_t reserved29[0x00006];
- pseudo_bit_t num_rsvd_uars[0x00004];/* The number of UARs reserved for firmware use
- The reserved resources are numbered from 0 to num_reserved_uars-1
- Note that UAR 1 is always for the kernel
- If 0 - no resources are reserved. */
-/* -------------- */
- pseudo_bit_t reserved30[0x00020];
-/* -------------- */
- pseudo_bit_t max_desc_sz[0x00010]; /* Max descriptor size in bytes */
- pseudo_bit_t max_sg[0x00008]; /* The maximum S/G list elements in a WQE (max_desc_sz/16 - 3) */
- pseudo_bit_t reserved31[0x00008];
-/* -------------- */
- pseudo_bit_t reserved32[0x00060];
-/* -------------- */
- pseudo_bit_t log_max_mcg[0x00008]; /* Log2 of the maximum number of multicast groups */
- pseudo_bit_t num_rsvd_mcgs[0x00004];/* The number of MGMs reserved for firmware use in the MGHT.
- The reserved resources are numbered from 0 to num_reserved_mcgs-1
- If 0 - no resources are reserved. */
- pseudo_bit_t reserved33[0x00004];
- pseudo_bit_t log_max_qp_mcg[0x00008];/* Log2 of the maximum number of QPs per multicast group */
- pseudo_bit_t reserved34[0x00008];
-/* -------------- */
- pseudo_bit_t log_max_rdds[0x00006]; /* Log2 of the maximum number of RDDs */
- pseudo_bit_t reserved35[0x00006];
- pseudo_bit_t num_rsvd_rdds[0x00004];/* The number of RDDs reserved for firmware use
- The reserved resources are numbered from 0 to num_reserved_rdds-1.
- If 0 - no resources are reserved. */
- pseudo_bit_t log_max_pd[0x00006]; /* Log2 of the maximum number of PDs */
- pseudo_bit_t reserved36[0x00006];
- pseudo_bit_t num_rsvd_pds[0x00004]; /* The number of PDs reserved for firmware use
- The reserved resources are numbered from 0 to num_reserved_pds-1
- If 0 - no resources are reserved. */
-/* -------------- */
- pseudo_bit_t reserved37[0x000c0];
-/* -------------- */
- pseudo_bit_t qpc_entry_sz[0x00010]; /* QPC Entry Size for the device
- For the InfiniHost MT23108 entry size is 256 bytes */
- pseudo_bit_t eec_entry_sz[0x00010]; /* EEC Entry Size for the device
- For the InfiniHost MT23108 entry size is 256 bytes */
-/* -------------- */
- pseudo_bit_t eqpc_entry_sz[0x00010];/* Extended QPC entry size for the device
- For the InfiniHost MT23108 entry size is 32 bytes */
- pseudo_bit_t eeec_entry_sz[0x00010];/* Extended EEC entry size for the device
- For the InfiniHost MT23108 entry size is 32 bytes */
-/* -------------- */
- pseudo_bit_t cqc_entry_sz[0x00010]; /* CQC entry size for the device
- For the InfiniHost MT23108 entry size is 64 bytes */
- pseudo_bit_t eqc_entry_sz[0x00010]; /* EQ context entry size for the device
- For the InfiniHost MT23108 entry size is 64 bytes */
-/* -------------- */
- pseudo_bit_t uar_scratch_entry_sz[0x00010];/* UAR Scratchpad Entry Size
- For the InfiniHost MT23108 entry size is 32 bytes */
- pseudo_bit_t srq_entry_sz[0x00010]; /* SRQ context entry size for the device
- For the InfiniHost MT23108 entry size is 32 bytes */
-/* -------------- */
- pseudo_bit_t reserved38[0x00380];
-/* -------------- */
-};
-
-/* QUERY_ADAPTER Parameters Block */
-
-struct tavorprm_query_adapter_st { /* Little Endian */
- pseudo_bit_t vendor_id[0x00020]; /* Adapter vendor ID */
-/* -------------- */
- pseudo_bit_t device_id[0x00020]; /* Adapter Device ID */
-/* -------------- */
- pseudo_bit_t revision_id[0x00020]; /* Adapter Revision ID */
-/* -------------- */
- pseudo_bit_t reserved0[0x00020];
-/* -------------- */
- pseudo_bit_t reserved1[0x00018];
- pseudo_bit_t intapin[0x00008]; /* Interrupt Signal ID of HCA device pin that is connected to the INTA trace in the HCA board.
- 0..39 and 63 are valid values
- 255 means INTA trace in board is not connected to the HCA device.
- All other values are reserved */
-/* -------------- */
- pseudo_bit_t mode_pci[0x00001]; /* Set when the device is operating in conventional PCI mode (as opposed to PCI-X/PCI-Express). */
- pseudo_bit_t mode_32bit[0x00001]; /* Set when the device is operating in 32 bit mode (the sampled bus width is 32 bit). */
- pseudo_bit_t reserved2[0x0001e];
-/* -------------- */
- pseudo_bit_t reserved3[0x00040];
-/* -------------- */
- struct tavorprm_vsd_st vsd;
-/* -------------- */
-};
-
-/* QUERY_FW Parameters Block */
-
-struct tavorprm_query_fw_st { /* Little Endian */
- pseudo_bit_t fw_rev_major[0x00010]; /* Firmware Revision - Major */
- pseudo_bit_t reserved0[0x00010];
-/* -------------- */
- pseudo_bit_t fw_rev_minor[0x00010]; /* Firmware Revision - Minor */
- pseudo_bit_t fw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */
-/* -------------- */
- pseudo_bit_t cmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */
- pseudo_bit_t reserved1[0x00010];
-/* -------------- */
- pseudo_bit_t log_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */
- pseudo_bit_t reserved2[0x00017];
- pseudo_bit_t dt[0x00001]; /* Debug Trace Support
- 0 - Debug trace is not supported
- 1 - Debug trace is supported */
-/* -------------- */
- pseudo_bit_t cmd_interface_db[0x00001];/* Set if the device accepts commands by means of special doorbells. */
- pseudo_bit_t reserved3[0x0001f];
-/* -------------- */
- pseudo_bit_t reserved4[0x00060];
-/* -------------- */
- pseudo_bit_t fw_base_addr_h[0x00020];/* Physical Address of Firmware Area in DDR Memory [63:32] */
-/* -------------- */
- pseudo_bit_t fw_base_addr_l[0x00020];/* Physical Address of Firmware Area in DDR Memory [31:0] */
-/* -------------- */
- pseudo_bit_t fw_end_addr_h[0x00020];/* End of firmware address in DDR memory [63:32] */
-/* -------------- */
- pseudo_bit_t fw_end_addr_l[0x00020];/* End of firmware address in DDR memory [31:0] */
-/* -------------- */
- pseudo_bit_t error_buf_start_h[0x00020];/* Read Only buffer for catastrofic error reports. */
-/* -------------- */
- pseudo_bit_t error_buf_start_l[0x00020];
-/* -------------- */
- pseudo_bit_t error_buf_size[0x00020];/* Size in words */
-/* -------------- */
- pseudo_bit_t reserved5[0x000a0];
-/* -------------- */
- pseudo_bit_t cmd_db_dw1[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 1 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
- pseudo_bit_t cmd_db_dw0[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 0 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
-/* -------------- */
- pseudo_bit_t cmd_db_dw3[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 3 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
- pseudo_bit_t cmd_db_dw2[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 2 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
-/* -------------- */
- pseudo_bit_t cmd_db_dw5[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 5 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
- pseudo_bit_t cmd_db_dw4[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 4 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
-/* -------------- */
- pseudo_bit_t cmd_db_dw7[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 7 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
- pseudo_bit_t cmd_db_dw6[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 6 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
-/* -------------- */
- pseudo_bit_t cmd_db_addr_base_h[0x00020];/* High bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */
-/* -------------- */
- pseudo_bit_t cmd_db_addr_base_l[0x00020];/* Low bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */
-/* -------------- */
- pseudo_bit_t reserved6[0x004c0];
-/* -------------- */
-};
-
-/* ACCESS_DDR */
-
-struct tavorprm_access_ddr_st { /* Little Endian */
- struct tavorprm_access_ddr_inject_errors_st access_ddr_inject_errors;
-/* -------------- */
- pseudo_bit_t reserved0[0x00080];
-/* -------------- */
-};
-
-/* QUERY_DDR Parameters Block */
-
-struct tavorprm_query_ddr_st { /* Little Endian */
- pseudo_bit_t ddr_start_adr_h[0x00020];/* DDR memory start address [63:32] */
-/* -------------- */
- pseudo_bit_t ddr_start_adr_l[0x00020];/* DDR memory start address [31:0] */
-/* -------------- */
- pseudo_bit_t ddr_end_adr_h[0x00020];/* DDR memory end address [63:32] */
-/* -------------- */
- pseudo_bit_t ddr_end_adr_l[0x00020];/* DDR memory end address [31:0] */
-/* -------------- */
- pseudo_bit_t di[0x00002]; /* Data Integrity Configuration:
- 00 - none
- 01 - Parity
- 10 - ECC Detection Only
- 11 - ECC With Correction */
- pseudo_bit_t ap[0x00002]; /* Auto Precharge Mode
- 00 - No auto precharge
- 01 - Auto precharge per transaction
- 10 - Auto precharge per 64 bytes
- 11 - reserved */
- pseudo_bit_t dh[0x00001]; /* When set, DDR is Hidden and can not be accessed from the PCI bus. */
- pseudo_bit_t reserved0[0x0001b];
-/* -------------- */
- pseudo_bit_t reserved1[0x00160];
-/* -------------- */
- struct tavorprm_dimminfo_st dimm0; /* Logical DIMM 0 Parameters */
-/* -------------- */
- struct tavorprm_dimminfo_st dimm1; /* Logical DIMM 1 Parameters */
-/* -------------- */
- struct tavorprm_dimminfo_st dimm2; /* Logical DIMM 2 Parameters */
-/* -------------- */
- struct tavorprm_dimminfo_st dimm3; /* Logical DIMM 3 Parameters */
-/* -------------- */
- pseudo_bit_t reserved2[0x00200];
-/* -------------- */
-};
-
-/* INIT_HCA & QUERY_HCA Parameters Block */
-
-struct tavorprm_init_hca_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00060];
-/* -------------- */
- pseudo_bit_t reserved1[0x00018];
- pseudo_bit_t hca_core_clock[0x00008];/* Internal Clock Period (in units of 1/16 ns) (QUERY_HCA only) */
-/* -------------- */
- pseudo_bit_t reserved2[0x00008];
- pseudo_bit_t router_qp[0x00010]; /* Upper 16 bit to be used as a QP number for router mode. Low order 8 bits are taken from the TClass field of the incoming packet.
- Valid only if RE bit is set */
- pseudo_bit_t reserved3[0x00007];
- pseudo_bit_t re[0x00001]; /* Router Mode Enable
- If this bit is set, entire packet (including all headers and ICRC) will be considered as a data payload and will be scattered to memory as specified in the descriptor that is posted on the QP matching the TClass field of packet. */
-/* -------------- */
- pseudo_bit_t udp[0x00001]; /* UD Port Check Enable
- 0 - Port field in Address Vector is ignored
- 1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */
- pseudo_bit_t he[0x00001]; /* Host Endianess - Used for Atomic Operations
- 0 - Host is Little Endian
- 1 - Host is Big endian
- */
- pseudo_bit_t ud[0x00001]; /* Force UD address vector protection check. If this bit is set, Passing address vector as immediate data in WQE is suppressed and privileged memory key will be used by hardware to access UD address vector table. */
- pseudo_bit_t reserved4[0x00005];
- pseudo_bit_t responder_exu[0x00004];/* How many execution engines are dedicated to the responder. Legal values are 0x0-0xF. 0 is "auto" */
- pseudo_bit_t reserved5[0x00004];
- pseudo_bit_t wqe_quota[0x0000f]; /* Maximum number of WQEs that are executed prior to preemption of execution unit. 0 - reserved. */
- pseudo_bit_t wqe_quota_en[0x00001]; /* If set - wqe_quota field is used. If cleared - WQE quota is set to "auto" value */
-/* -------------- */
- pseudo_bit_t reserved6[0x00040];
-/* -------------- */
- struct tavorprm_qpcbaseaddr_st qpc_eec_cqc_eqc_rdb_parameters;
-/* -------------- */
- pseudo_bit_t reserved7[0x00080];
-/* -------------- */
- struct tavorprm_udavtable_memory_parameters_st udavtable_memory_parameters;/* Memory Access Parameters for UD Address Vector Table. Used for QPs/EEc that are configured to use protected Address Vectors. */
-/* -------------- */
- pseudo_bit_t reserved8[0x00040];
-/* -------------- */
- struct tavorprm_multicastparam_st multicast_parameters;
-/* -------------- */
- pseudo_bit_t reserved9[0x00080];
-/* -------------- */
- struct tavorprm_tptparams_st tpt_parameters;
-/* -------------- */
- pseudo_bit_t reserved10[0x00080];
-/* -------------- */
- struct tavorprm_uar_params_st uar_parameters;/* UAR Parameters */
-/* -------------- */
- pseudo_bit_t reserved11[0x00600];
-/* -------------- */
-};
-
-/* Event Queue Context Table Entry */
-
-struct tavorprm_eqc_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00008];
- pseudo_bit_t st[0x00002]; /* Event delivery state machine
- 01 - Armed
- 10 - Fired
- 11 - Always_Armed (auto-rearm)
- 00 - Reserved */
- pseudo_bit_t reserved1[0x00007];
- pseudo_bit_t oi[0x00001]; /* Ignore overrun on this EQ if this bit is set */
- pseudo_bit_t tr[0x00001]; /* Translation Required. If set - EQ access undergo address translation. */
- pseudo_bit_t reserved2[0x00005];
- pseudo_bit_t owner[0x00004]; /* 0 - SW ownership
- 1 - HW ownership
- Valid for the QUERY_EQ and HW2SW_EQ commands only */
- pseudo_bit_t status[0x00004]; /* EQ status:
- 0000 - OK
- 1001 - EQ overflow
- 1010 - EQ write failure
- Valid for the QUERY_EQ and HW2SW_EQ commands only */
-/* -------------- */
- pseudo_bit_t start_address_h[0x00020];/* Start Address of Event Queue[63:32].
- Must be aligned on 32-byte boundary */
-/* -------------- */
- pseudo_bit_t start_address_l[0x00020];/* Start Address of Event Queue[31:0].
- Must be aligned on 32-byte boundary */
-/* -------------- */
- pseudo_bit_t usr_page[0x00018];
- pseudo_bit_t log_eq_size[0x00005]; /* Amount of entries in this EQ is 2^log_eq_size.
- Log_eq_size must be bigger than 1 */
- pseudo_bit_t reserved3[0x00003];
-/* -------------- */
- pseudo_bit_t pd[0x00018]; /* PD to be used to access EQ */
- pseudo_bit_t reserved4[0x00008];
-/* -------------- */
- pseudo_bit_t intr[0x00008]; /* Interrupt (message) to be generated to report event to INT layer.
- 00iiiiii - specifies GPIO pin to be asserted (according to INTA given in QUERY_ADAPTER)
- 10jjjjjj - specificies type of interrupt message to be generated (total 64 different messages supported).
-
- If interrupt generation is not required one of the two following options should be set:
- 1. ST must be set on creation to Fired state and not EQ arming doorbell should be performed. In this case hardware will not generate any interrupt.
- 2. intr should be set to 60 decimal
- */
- pseudo_bit_t reserved5[0x00018];
-/* -------------- */
- pseudo_bit_t lost_count[0x00020]; /* Number of events lost due to EQ overrun */
-/* -------------- */
- pseudo_bit_t lkey[0x00020]; /* Memory key (L-Key) to be used to access EQ */
-/* -------------- */
- pseudo_bit_t reserved6[0x00040];
-/* -------------- */
- pseudo_bit_t consumer_indx[0x00020];/* Contains next entry to be read upon polling the event queue.
- Must be initalized to '0 while opening EQ */
-/* -------------- */
- pseudo_bit_t producer_indx[0x00020];/* Contains next entry in EQ to be written by the HCA.
- Must be initalized to '0 while opening EQ. */
-/* -------------- */
- pseudo_bit_t reserved7[0x00080];
-/* -------------- */
-};
-
-/* Memory Translation Table (MTT) Entry */
-
-struct tavorprm_mtt_st { /* Little Endian */
- pseudo_bit_t ptag_h[0x00020]; /* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
-/* -------------- */
- pseudo_bit_t p[0x00001]; /* Present bit. If set, page entry is valid. If cleared, access to this page will generate 'non-present page access fault'. */
- pseudo_bit_t reserved0[0x0000b];
- pseudo_bit_t ptag_l[0x00014]; /* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
-/* -------------- */
-};
-
-/* Memory Protection Table (MPT) Entry */
-
-struct tavorprm_mpt_st { /* Little Endian */
- pseudo_bit_t ver[0x00004]; /* Version. Must be zero for InfiniHost */
- pseudo_bit_t reserved0[0x00004];
- pseudo_bit_t r_w[0x00001]; /* Defines whether this entry is Region (1) or Window (0) */
- pseudo_bit_t pa[0x00001]; /* Physical address. If set, no virtual-to-physical address translation will be performed for this region */
- pseudo_bit_t lr[0x00001]; /* If set - local read access enabled */
- pseudo_bit_t lw[0x00001]; /* If set - local write access enabled */
- pseudo_bit_t rr[0x00001]; /* If set - Remote read access enabled. */
- pseudo_bit_t rw[0x00001]; /* If set - remote write access enabled */
- pseudo_bit_t a[0x00001]; /* If set - Remote Atomic access is enabled */
- pseudo_bit_t eb[0x00001]; /* If set - Bind is enabled. Valid for region entry only. */
- pseudo_bit_t reserved1[0x00001];
- pseudo_bit_t m_io[0x00001]; /* Memory / I/O
- 1 - Memory commands used on the uplink bus
- 0 - I/O commands used on the uplink bus
- Must be 1 for the InfiniHost MT23108. */
- pseudo_bit_t reserved2[0x0000a];
- pseudo_bit_t status[0x00004]; /* Regios/Window Status
- 0xF - not valid (SW ownership)
- else - HW ownership
- Note that an unbound Window is denoted by the reg_wnd_len field equals zero. */
-/* -------------- */
- pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes.
- page_size should be less than 20. */
- pseudo_bit_t reserved3[0x00002];
- pseudo_bit_t reserved4[0x00001];
- pseudo_bit_t reserved5[0x00018];
-/* -------------- */
- pseudo_bit_t mem_key[0x00020]; /* The memory Key. This field is compared to key used to access the region/window. Lower-order bits are restricted (index to the table). */
-/* -------------- */
- pseudo_bit_t pd[0x00018]; /* Protection Domain */
- pseudo_bit_t reserved6[0x00001];
- pseudo_bit_t reserved7[0x00001];
- pseudo_bit_t reserved8[0x00001];
- pseudo_bit_t reserved9[0x00001];
- pseudo_bit_t reserved10[0x00001];
- pseudo_bit_t reserved11[0x00003];
-/* -------------- */
- pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region/window starts */
-/* -------------- */
- pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region/window starts */
-/* -------------- */
- pseudo_bit_t reg_wnd_len_h[0x00020];/* Region/Window Length[63:32] */
-/* -------------- */
- pseudo_bit_t reg_wnd_len_l[0x00020];/* Region/Window Length[31:0] */
-/* -------------- */
- pseudo_bit_t lkey[0x00020]; /* Must be 0 for SW2HW_MPT.
- On QUERY_MPT and HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to. */
-/* -------------- */
- pseudo_bit_t win_cnt[0x00020]; /* Number of windows bound to this region. Valid for regions only.
- The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */
-/* -------------- */
- pseudo_bit_t win_cnt_limit[0x00020];/* The number of windows (limit) that can be bound to this region. If a bind operation is attempted when WIN_CNT == WIN_CNT_LIMIT, the operation will be aborted, a CQE with error will be generated, and the QP will be moved into the error state.
- Zero means no limit.
- Note that for best hardware performance, win_cnt_limit should be set to zero. */
-/* -------------- */
- pseudo_bit_t mtt_seg_adr_h[0x00020];/* Base (first) address of the MTT segment, aligned on segment_size boundary (bits 63:31). */
-/* -------------- */
- pseudo_bit_t reserved12[0x00006];
- pseudo_bit_t mtt_seg_adr_l[0x0001a];/* Base (first) address of the MTT segment, aligned on segment_size boundary (bits 31:6). */
-/* -------------- */
- pseudo_bit_t reserved13[0x00060];
-/* -------------- */
-};
-
-/* Completion Queue Context Table Entry */
-
-struct tavorprm_completion_queue_context_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00008];
- pseudo_bit_t st[0x00004]; /* Event delivery state machine
- 0x0 - DISARMED
- 0x1 - ARMED (Request for Notification)
- 0x4 - ARMED SOLICITED (Request Solicited Notification)
- 0xA - FIRED
- other - reserved */
- pseudo_bit_t reserved1[0x00005];
- pseudo_bit_t oi[0x00001]; /* Ignore overrun of this CQ if this bit is set */
- pseudo_bit_t tr[0x00001]; /* Translation Required
- 1 - accesses to CQ will undergo address translation
- 0 - accesses to CQ will not undergo address translation */
- pseudo_bit_t reserved2[0x00009];
- pseudo_bit_t status[0x00004]; /* CQ status
- 0000 - OK
- 1001 - CQ overflow
- 1010 - CQ write failure
- Valid for the QUERY_CQ and HW2SW_CQ commands only */
-/* -------------- */
- pseudo_bit_t start_address_h[0x00020];/* Start address of CQ[63:32].
- Must be aligned on CQE size (32 bytes) */
-/* -------------- */
- pseudo_bit_t start_address_l[0x00020];/* Start address of CQ[31:0].
- Must be aligned on CQE size (32 bytes) */
-/* -------------- */
- pseudo_bit_t usr_page[0x00018]; /* UAR page this CQ can be accessed through (ringinig CQ doorbells) */
- pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries).
- Maximum CQ size is 128K CQEs (max log_cq_size is 17) */
- pseudo_bit_t reserved3[0x00003];
-/* -------------- */
- pseudo_bit_t e_eqn[0x00008]; /* Event Queue this CQ reports errors to (e.g. CQ overflow)
- Valid values are 0 to 63
- If configured to value other than 0-63, error events will not be reported on the CQ. */
- pseudo_bit_t reserved4[0x00018];
-/* -------------- */
- pseudo_bit_t c_eqn[0x00008]; /* Event Queue this CQ reports completion events to.
- Valid values are 0 to 63
- If configured to value other than 0-63, completion events will not be reported on the CQ. */
- pseudo_bit_t reserved5[0x00018];
-/* -------------- */
- pseudo_bit_t pd[0x00018]; /* Protection Domain to be used to access CQ.
- Must be the same PD of the CQ L_Key. */
- pseudo_bit_t reserved6[0x00008];
-/* -------------- */
- pseudo_bit_t l_key[0x00020]; /* Memory key (L_Key) to be used to access CQ */
-/* -------------- */
- pseudo_bit_t last_notified_indx[0x00020];/* Maintained by HW.
- Valid for QUERY_CQ and HW2SW_CQ commands only. */
-/* -------------- */
- pseudo_bit_t solicit_producer_indx[0x00020];/* Maintained by HW.
- Valid for QUERY_CQ and HW2SW_CQ commands only.
- */
-/* -------------- */
- pseudo_bit_t consumer_indx[0x00020];/* Contains index to the next entry to be read upon poll for completion. The first completion after passing ownership of CQ from software to hardware will be reported to value passed in this field. Only the low log_cq_size bits may be non-zero. */
-/* -------------- */
- pseudo_bit_t producer_indx[0x00020];/* Points to the next entry to be written to by Hardware. CQ overrun is reported if Producer_indx + 1 equals to Consumer_indx.
- Maintained by HW (valid for the QUERY_CQ and HW2SW_CQ commands only) */
-/* -------------- */
- pseudo_bit_t cqn[0x00018]; /* CQ number. Least significant bits are constrained by the position of this CQ in CQC table
- Valid for the QUERY_CQ and HW2SW_CQ commands only */
- pseudo_bit_t reserved7[0x00008];
-/* -------------- */
- pseudo_bit_t reserved8[0x00060];
-/* -------------- */
-};
-
-/* UD Address Vector */
-
-struct tavorprm_ud_address_vector_st { /* Little Endian */
- pseudo_bit_t pd[0x00018]; /* Protection Domain */
- pseudo_bit_t port_number[0x00002]; /* Port number
- 1 - Port 1
- 2 - Port 2
- other - reserved */
- pseudo_bit_t reserved0[0x00006];
-/* -------------- */
- pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */
- pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */
- pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */
- pseudo_bit_t reserved1[0x00008];
-/* -------------- */
- pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */
- pseudo_bit_t max_stat_rate[0x00003];/* Maximum static rate control.
- 0 - 4X injection rate
- 1 - 1X injection rate
- other - reserved
- */
- pseudo_bit_t reserved2[0x00001];
- pseudo_bit_t msg[0x00002]; /* Max Message size, size is 256*2^MSG bytes */
- pseudo_bit_t reserved3[0x00002];
- pseudo_bit_t mgid_index[0x00006]; /* Index to port GID table
- mgid_index = (port_number-1) * 2^log_max_gid + gid_index
- Where:
- 1. log_max_gid is taken from QUERY_DEV_LIM command
- 2. gid_index is the index to the GID table */
- pseudo_bit_t reserved4[0x0000a];
-/* -------------- */
- pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */
- pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */
- pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */
-/* -------------- */
- pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */
-/* -------------- */
- pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */
-/* -------------- */
- pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */
-/* -------------- */
- pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] */
-/* -------------- */
-};
-
-/* GPIO_event_data */
-
-struct tavorprm_gpio_event_data_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00060];
-/* -------------- */
- pseudo_bit_t gpio_event_hi[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */
-/* -------------- */
- pseudo_bit_t gpio_event_lo[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */
-/* -------------- */
- pseudo_bit_t reserved1[0x00020];
-/* -------------- */
-};
-
-/* Event_data Field - QP/EE Events */
-
-struct tavorprm_qp_ee_event_st { /* Little Endian */
- pseudo_bit_t qpn_een[0x00018]; /* QP/EE/SRQ number event is reported for */
- pseudo_bit_t reserved0[0x00008];
-/* -------------- */
- pseudo_bit_t reserved1[0x00020];
-/* -------------- */
- pseudo_bit_t reserved2[0x0001c];
- pseudo_bit_t e_q[0x00001]; /* If set - EEN if cleared - QP in the QPN/EEN field
- Not valid on SRQ events */
- pseudo_bit_t reserved3[0x00003];
-/* -------------- */
- pseudo_bit_t reserved4[0x00060];
-/* -------------- */
-};
-
-/* InfiniHost Type0 Configuration Header */
-
-struct tavorprm_mt23108_type0_st { /* Little Endian */
- pseudo_bit_t vendor_id[0x00010]; /* Hardwired to 0x15B3 */
- pseudo_bit_t device_id[0x00010]; /* hardwired to 23108 */
-/* -------------- */
- pseudo_bit_t command[0x00010]; /* PCI Command Register */
- pseudo_bit_t status[0x00010]; /* PCI Status Register */
-/* -------------- */
- pseudo_bit_t revision_id[0x00008];
- pseudo_bit_t class_code_hca_class_code[0x00018];
-/* -------------- */
- pseudo_bit_t cache_line_size[0x00008];/* Cache Line Size */
- pseudo_bit_t latency_timer[0x00008];
- pseudo_bit_t header_type[0x00008]; /* hardwired to zero */
- pseudo_bit_t bist[0x00008];
-/* -------------- */
- pseudo_bit_t bar0_ctrl[0x00004]; /* hard-wired to '0100 */
- pseudo_bit_t reserved0[0x00010];
- pseudo_bit_t bar0_l[0x0000c]; /* Lower bits of BAR0 (configuration space) */
-/* -------------- */
- pseudo_bit_t bar0_h[0x00020]; /* Upper 32 bits of BAR0 (configuration space) */
-/* -------------- */
- pseudo_bit_t bar1_ctrl[0x00004]; /* Hardwired to '1100 */
- pseudo_bit_t reserved1[0x00010];
- pseudo_bit_t bar1_l[0x0000c]; /* Lower bits of BAR1 */
-/* -------------- */
- pseudo_bit_t bar1_h[0x00020]; /* upper 32 bits of BAR1 (User Access Revion - UAR - space) */
-/* -------------- */
- pseudo_bit_t bar2_ctrl[0x00004]; /* Hardwired to '1100 */
- pseudo_bit_t reserved2[0x00010];
- pseudo_bit_t bar2_l[0x0000c]; /* Lower bits of BAR2 */
-/* -------------- */
- pseudo_bit_t bar2_h[0x00020]; /* Upper 32 bits of BAR2 - DDR (attached memory) BAR */
-/* -------------- */
- pseudo_bit_t cardbus_cis_pointer[0x00020];
-/* -------------- */
- pseudo_bit_t subsystem_vendor_id[0x00010];/* Specified by the device NVMEM configuration */
- pseudo_bit_t subsystem_id[0x00010]; /* Specified by the device NVMEM configuration */
-/* -------------- */
- pseudo_bit_t expansion_rom_enable[0x00001];/* Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
- pseudo_bit_t reserved3[0x0000a];
- pseudo_bit_t expansion_rom_base_address[0x00015];/* Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
-/* -------------- */
- pseudo_bit_t capabilities_pointer[0x00008];/* Specified by the device NVMEM configuration */
- pseudo_bit_t reserved4[0x00018];
-/* -------------- */
- pseudo_bit_t reserved5[0x00020];
-/* -------------- */
- pseudo_bit_t interrupt_line[0x00008];
- pseudo_bit_t interrupt_pin[0x00008];
- pseudo_bit_t min_gnt[0x00008];
- pseudo_bit_t max_latency[0x00008];
-/* -------------- */
- pseudo_bit_t reserved6[0x00100];
-/* -------------- */
- pseudo_bit_t msi_cap_id[0x00008];
- pseudo_bit_t msi_next_cap_ptr[0x00008];
- pseudo_bit_t msi_en[0x00001];
- pseudo_bit_t multiple_msg_cap[0x00003];
- pseudo_bit_t multiple_msg_en[0x00003];
- pseudo_bit_t cap_64_bit_addr[0x00001];
- pseudo_bit_t reserved7[0x00008];
-/* -------------- */
- pseudo_bit_t msg_addr_l[0x00020];
-/* -------------- */
- pseudo_bit_t msg_addr_h[0x00020];
-/* -------------- */
- pseudo_bit_t msg_data[0x00010];
- pseudo_bit_t reserved8[0x00010];
-/* -------------- */
- pseudo_bit_t pcix_cap_id[0x00008];
- pseudo_bit_t pcix_next_cap_ptr[0x00008];
- pseudo_bit_t pcix_command_reg[0x00010];/* PCIX command register */
-/* -------------- */
- pseudo_bit_t pcix_status_reg[0x00020];/* PCIX Status Register */
-/* -------------- */
- pseudo_bit_t reserved9[0x00440];
-/* -------------- */
-};
-
-/* NTU QP Map Table Entry */
-
-struct tavorprm_ntu_qpm_st { /* Little Endian */
- pseudo_bit_t va_h[0x00020]; /* Bits 63:32 of the virtual address to be used in IB request, Number of bits to be actually used depends on the page size (eg. will use all 52 for 4K page, 51 for 8K page etc). */
-/* -------------- */
- pseudo_bit_t wm[0x00002]; /* Amount of data to fill in to the read response buffer prior to delivering read response to uplink
- 00 - forward
- 01 - MTU
- 10 - full message
- 11 - Reserved */
- pseudo_bit_t mtu[0x00002]; /* MTUI of the channel to be used by this page, value is 256*2MU bytes */
- pseudo_bit_t rd_len[0x00003]; /* Length of speculative prefetch for read, value is 16*2RD_Len bytes */
- pseudo_bit_t fence[0x00002];
- pseudo_bit_t reserved0[0x00002];
- pseudo_bit_t err_fence[0x00001]; /* 0,00 - No action in NTU - normal flow
- 0,01 - Reserved (fence bits value of "01" is not defined)
- 0,10 - Enter PCU transaction to Error fifo, NO fence trap to consequent transaction
- 0,11 - Enter PCU transaction to Error fifo, fence trap to consequent transactions
- 1,xx - Enter PCU transaction to Error fifo, mark QRM indication in error fifo. */
- pseudo_bit_t va_l[0x00014]; /* Bits 31:12 of the virtual address to be used in IB request, Number of bits to be actually used depends on the page size (eg. will use all 52 for 4K page, 51 for 8K page etc). */
-/* -------------- */
- pseudo_bit_t rkey[0x00020]; /* RKey to be places for RDMA IB requests message */
-/* -------------- */
- pseudo_bit_t my_qpn[0x00018]; /* Local QO this page is mapped to */
- pseudo_bit_t s[0x00001]; /* Force solicit event bit in the descriptor */
- pseudo_bit_t e[0x00001]; /* Force E-bit in the descriptor */
- pseudo_bit_t s_r[0x00001]; /* S/R# - generate Send as a result of write hit to this page */
- pseudo_bit_t b[0x00001]; /* Breakpoint - ptransfer control to firmware for every cycle that hits this page */
- pseudo_bit_t reserved1[0x00002];
- pseudo_bit_t ce[0x00001]; /* Cache Enable - entry can be cached if this bit is set. */
- pseudo_bit_t v[0x00001]; /* Valid bit - the entry is valid only if this bit is set */
-/* -------------- */
-};
-
-/* Event Data Field - Performance Monitor */
-
-struct tavorprm_performance_monitor_event_st { /* Little Endian */
- struct tavorprm_performance_monitors_st performance_monitor_snapshot;/* Performance monitor snapshot */
-/* -------------- */
- pseudo_bit_t monitor_number[0x00008];/* 0x01 - SQPC
- 0x02 - RQPC
- 0x03 - CQC
- 0x04 - Rkey
- 0x05 - TLB
- 0x06 - port0
- 0x07 - port1 */
- pseudo_bit_t reserved0[0x00018];
-/* -------------- */
- pseudo_bit_t reserved1[0x00040];
-/* -------------- */
-};
-
-/* Event_data Field - Page Faults */
-
-struct tavorprm_page_fault_event_data_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00040];
-/* -------------- */
- pseudo_bit_t s_r[0x00001]; /* Send (1) or Receive (0) queue caused page fault */
- pseudo_bit_t r_l[0x00001]; /* Remote (1) or local (0) access caused fault */
- pseudo_bit_t w_d[0x00001]; /* WQE (1) or data (0) access caused fault */
- pseudo_bit_t wqv[0x00001]; /* Indicates whether message caused fault consumes descriptor (valid for receive queue only). */
- pseudo_bit_t fault_type[0x00004]; /* 0000-0111 - RESERVED
- 1000 - Translation page not present
- 1001 - RESERVED
- 1010 - Page write access violation
- 1011 - 1101 - RESERVED
- 1110 - Unsupported non-present page fault
- 1111 - unsupported write access fault */
- pseudo_bit_t reserved1[0x00018];
-/* -------------- */
- pseudo_bit_t va_h[0x00020]; /* Virtual address that caused access fault[63:32] */
-/* -------------- */
- pseudo_bit_t va_l[0x00020]; /* Virtual address that caused access fault[31:0] */
-/* -------------- */
- pseudo_bit_t mem_key[0x00020]; /* Memory Key used for address translation */
-/* -------------- */
-};
-
-/* Event_data Field - Port State Change */
-
-struct tavorprm_port_state_change_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00040];
-/* -------------- */
- pseudo_bit_t reserved1[0x0001c];
- pseudo_bit_t p[0x00002]; /* Port number (1 or 2) */
- pseudo_bit_t reserved2[0x00002];
-/* -------------- */
- pseudo_bit_t reserved3[0x00060];
-/* -------------- */
-};
-
-/* Event_data Field - Completion Queue Error */
-
-struct tavorprm_completion_queue_error_st { /* Little Endian */
- pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */
- pseudo_bit_t reserved0[0x00008];
-/* -------------- */
- pseudo_bit_t reserved1[0x00020];
-/* -------------- */
- pseudo_bit_t syndrome[0x00008]; /* Error syndrome
- 0x01 - CQ overrun
- 0x02 - CQ access violation error */
- pseudo_bit_t reserved2[0x00018];
-/* -------------- */
- pseudo_bit_t reserved3[0x00060];
-/* -------------- */
-};
-
-/* Event_data Field - Completion Event */
-
-struct tavorprm_completion_event_st { /* Little Endian */
- pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */
- pseudo_bit_t reserved0[0x00008];
-/* -------------- */
- pseudo_bit_t reserved1[0x000a0];
-/* -------------- */
-};
-
-/* Event Queue Entry */
-
-struct tavorprm_event_queue_entry_st { /* Little Endian */
- pseudo_bit_t event_sub_type[0x00008];/* Event Sub Type.
- Defined for events which have sub types, zero elsewhere. */
- pseudo_bit_t reserved0[0x00008];
- pseudo_bit_t event_type[0x00008]; /* Event Type */
- pseudo_bit_t reserved1[0x00008];
-/* -------------- */
- pseudo_bit_t event_data[6][0x00020];/* Delivers auxilary data to handle event. */
-/* -------------- */
- pseudo_bit_t reserved2[0x00007];
- pseudo_bit_t owner[0x00001]; /* Owner of the entry
- 0 SW
- 1 HW */
- pseudo_bit_t reserved3[0x00018];
-/* -------------- */
-};
-
-/* QP/EE State Transitions Command Parameters */
-
-struct tavorprm_qp_ee_state_transitions_st { /* Little Endian */
- pseudo_bit_t opt_param_mask[0x00020];/* This field defines which optional parameters are passed. Each bit specifies whether optional parameter is passed (set) or not (cleared). The optparammask is defined for each QP/EE command. */
-/* -------------- */
- pseudo_bit_t reserved0[0x00020];
-/* -------------- */
- struct tavorprm_queue_pair_ee_context_entry_st qpc_eec_data;/* QPC/EEC data */
-/* -------------- */
- pseudo_bit_t reserved1[0x007c0];
-/* -------------- */
-};
-
-/* Completion Queue Entry Format */
-
-struct tavorprm_completion_queue_entry_st { /* Little Endian */
- pseudo_bit_t my_qpn[0x00018]; /* Indicates the QP for which completion is being reported */
- pseudo_bit_t reserved0[0x00004];
- pseudo_bit_t ver[0x00004]; /* CQE version.
- 0 for InfiniHost */
-/* -------------- */
- pseudo_bit_t my_ee[0x00018]; /* EE context (for RD only).
- Invalid for Bind and Nop operation on RD. */
- pseudo_bit_t reserved1[0x00008];
-/* -------------- */
- pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number. Valid in Responder CQE only for Datagram QP. */
- pseudo_bit_t reserved2[0x00008];
-/* -------------- */
- pseudo_bit_t rlid[0x00010]; /* Remote (source) LID of the message. Valid in Responder of UD QP CQE only. */
- pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits - these are the lowemost LMC bits of the DLID in an incoming UD packet, higher bits of this field, that are not part of the LMC bits are zeroed by HW.
- Valid in responder of UD QP CQE only.
- Invalid if incoming message DLID is the permissive LID or incoming message is multicast. */
- pseudo_bit_t g[0x00001]; /* GRH present indicator. Valid in Responder of UD QP CQE only. */
- pseudo_bit_t reserved3[0x00001];
- pseudo_bit_t reserved4[0x00003];
- pseudo_bit_t sl[0x00004]; /* Service Level of the message. Valid in Responder of UD QP CQE only. */
-/* -------------- */
- pseudo_bit_t immediate_ethertype_pkey_indx_eecredits[0x00020];/* Valid for receive queue completion only.
- If Opcode field indicates that this was send/write with immediate, this field contains immediate field of the packet.
- If completion corresponds to RAW receive queue, bits 15:0 contain Ethertype field of the packet.
- If completion corresponds to GSI receive queue, bits 31:16 contain index in PKey table that matches PKey of the message arrived.
- For CQE of send queue of the reliable connection service, bits [4:0] of this field contain the encoded EEcredits received in last ACK of the message.
- */
-/* -------------- */
- pseudo_bit_t byte_cnt[0x00020]; /* Byte count of data actually transferred (valid for receive queue completions only) */
-/* -------------- */
- pseudo_bit_t wqe_size[0x00006]; /* Size (in 16-byte chunks) of WQE completion is reported for */
- pseudo_bit_t wqe_adr[0x0001a]; /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */
-/* -------------- */
- pseudo_bit_t reserved5[0x00007];
- pseudo_bit_t owner[0x00001]; /* Owner field. Zero value of this field means SW ownership of CQE. */
- pseudo_bit_t reserved6[0x0000d];
- pseudo_bit_t reserved7[0x00001];
- pseudo_bit_t reserved8[0x00001];
- pseudo_bit_t s[0x00001]; /* If set, completion is reported for Send queue, if cleared - receive queue. */
- pseudo_bit_t opcode[0x00008]; /* The opcode of WQE completion is reported for.
- For CQEs corresponding to send completion, NOPCODE field of the WQE is copied to this field.
- For CQEs corresponding to receive completions, opcode field of last packet in the message copied to this field.
- For CQEs corresponding to the receive queue of QPs mapped to QP1, the opcode will be SEND with Immediate (messages are guaranteed to be SEND only)
-
- The following values are reported in case of completion with error:
- 0xFE - For completion with error on Receive Queues
- 0xFF - For completion with error on Send Queues */
-/* -------------- */
-};
-
-/* */
-
-struct tavorprm_ecc_detect_event_data_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00080];
-/* -------------- */
- pseudo_bit_t cause_lsb[0x00001];
- pseudo_bit_t reserved1[0x00002];
- pseudo_bit_t cause_msb[0x00001];
- pseudo_bit_t reserved2[0x00002];
- pseudo_bit_t err_rmw[0x00001];
- pseudo_bit_t err_src_id[0x00003];
- pseudo_bit_t err_da[0x00002];
- pseudo_bit_t err_ba[0x00002];
- pseudo_bit_t reserved3[0x00011];
- pseudo_bit_t overflow[0x00001];
-/* -------------- */
- pseudo_bit_t err_ra[0x00010];
- pseudo_bit_t err_ca[0x00010];
-/* -------------- */
-};
-
-/* MAD_IFC Input Mailbox */
-
-struct tavorprm_mad_ifc_st { /* Little Endian */
- pseudo_bit_t request_mad_packet[64][0x00020];/* Request MAD Packet (256bytes) */
-/* -------------- */
- pseudo_bit_t my_qpn[0x00018]; /* Destination QP number from the received MAD.
- This field is reserved if Mad_extended_info indication in the input modifier is clear. */
- pseudo_bit_t reserved0[0x00008];
-/* -------------- */
- pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number from the received MAD.
- This field is reserved if Mad_extended_info indication in the input modifier is clear. */
- pseudo_bit_t reserved1[0x00008];
-/* -------------- */
- pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD.
- This field is reserved if Mad_extended_info indication in the input modifier is clear. */
- pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits from the received MAD.
- This field is reserved if Mad_extended_info indication in the input modifier is clear. */
- pseudo_bit_t g[0x00001]; /* If set, the GRH field in valid.
- This field is reserved if Mad_extended_info indication in the input modifier is clear. */
- pseudo_bit_t reserved2[0x00004];
- pseudo_bit_t sl[0x00004]; /* Service Level of the received MAD.
- This field is reserved if Mad_extended_info indication in the input modifier is clear. */
-/* -------------- */
- pseudo_bit_t pkey_indx[0x00010]; /* Index in PKey table that matches PKey of the received MAD.
- This field is reserved if Mad_extended_info indication in the input modifier is clear. */
- pseudo_bit_t reserved3[0x00010];
-/* -------------- */
- pseudo_bit_t reserved4[0x00180];
-/* -------------- */
- pseudo_bit_t grh[10][0x00020]; /* The GRH field of the MAD packet that was scattered to the first 40 bytes pointed to by the scatter list.
- Valid if Mad_extended_info bit (in the input modifier) and g bit are set.
- Otherwise this field is reserved. */
-/* -------------- */
- pseudo_bit_t reserved5[0x004c0];
-/* -------------- */
-};
-
-/* Event_data Field - ECC Detection Event */
-
-struct tavorprm_scrubbing_event_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00080];
-/* -------------- */
- pseudo_bit_t cause_lsb[0x00001]; /* data integrity error cause:
- single ECC error in the 64bit lsb data, on the rise edge of the clock */
- pseudo_bit_t reserved1[0x00002];
- pseudo_bit_t cause_msb[0x00001]; /* data integrity error cause:
- single ECC error in the 64bit msb data, on the fall edge of the clock */
- pseudo_bit_t reserved2[0x00002];
- pseudo_bit_t err_rmw[0x00001]; /* transaction type:
- 0 - read
- 1 - read/modify/write */
- pseudo_bit_t err_src_id[0x00003]; /* source of the transaction: 0x4 - PCI, other - internal or IB */
- pseudo_bit_t err_da[0x00002]; /* Error DIMM address */
- pseudo_bit_t err_ba[0x00002]; /* Error bank address */
- pseudo_bit_t reserved3[0x00011];
- pseudo_bit_t overflow[0x00001]; /* Fatal: ECC error FIFO overflow - ECC errors were detected, which may or may not have been corrected by InfiniHost */
-/* -------------- */
- pseudo_bit_t err_ra[0x00010]; /* Error row address */
- pseudo_bit_t err_ca[0x00010]; /* Error column address */
-/* -------------- */
-};
-
-/* PBL */
-
-struct tavorprm_pbl_st { /* Little Endian */
- pseudo_bit_t mtt_0_h[0x00020]; /* First MTT[63:32] */
-/* -------------- */
- pseudo_bit_t mtt_0_l[0x00020]; /* First MTT[31:0] */
-/* -------------- */
- pseudo_bit_t mtt_1_h[0x00020]; /* Second MTT[63:32] */
-/* -------------- */
- pseudo_bit_t mtt_1_l[0x00020]; /* Second MTT[31:0] */
-/* -------------- */
- pseudo_bit_t mtt_2_h[0x00020]; /* Third MTT[63:32] */
-/* -------------- */
- pseudo_bit_t mtt_2_l[0x00020]; /* Third MTT[31:0] */
-/* -------------- */
- pseudo_bit_t mtt_3_h[0x00020]; /* Fourth MTT[63:32] */
-/* -------------- */
- pseudo_bit_t mtt_3_l[0x00020]; /* Fourth MTT[31:0] */
-/* -------------- */
-};
-
-/* Miscellaneous Counters */
-
-struct tavorprm_misc_counters_st { /* Little Endian */
- pseudo_bit_t ddr_scan_cnt[0x00020]; /* Number of times whole of DDR was scanned */
-/* -------------- */
- pseudo_bit_t reserved0[0x007e0];
-/* -------------- */
-};
-
-/* MAD_IFC Opcode Modifier */
-
-struct tavorprm_mad_ifc_opcode_modifier_st { /* Little Endian */
- pseudo_bit_t mkey[0x00001]; /* Enable MKey validation. */
- pseudo_bit_t bkey[0x00001]; /* Enable BKey validation. */
- pseudo_bit_t reserved0[0x0001d];
- pseudo_bit_t mad_extended_info[0x00001];/* Mad_Extended_Info valid bit.
- Requeried for for trap generation when BKey check is enabled. */
-/* -------------- */
-};
-
-/* MAD_IFC Input Modifier */
-
-struct tavorprm_mad_ifc_input_modifier_st { /* Little Endian */
- pseudo_bit_t port_number[0x00008]; /* Port number (1 or 2). */
- pseudo_bit_t reserved0[0x00008];
- pseudo_bit_t rlid[0x00001]; /* Remote (source) LID from the received MAD.
- This field is required for trap generation upon MKey/BKey validation. */
- pseudo_bit_t reserved1[0x0000f];
-/* -------------- */
-};
-
-/* Fast_Registration_Segment */
-
-struct tavorprm_fast_registration_segment_st { /* Little Endian */
- pseudo_bit_t reserved0[0x0001b];
- pseudo_bit_t lr[0x00001]; /* If set - Local Read access will be enabled */
- pseudo_bit_t lw[0x00001]; /* If set - Local Write access will be enabled */
- pseudo_bit_t rr[0x00001]; /* If set - Remote Read access will be enabled */
- pseudo_bit_t rw[0x00001]; /* If set - Remote Write access will be enabled */
- pseudo_bit_t a[0x00001]; /* If set - Remote Atomic access will be enabled */
-/* -------------- */
- pseudo_bit_t pbl_ptr_63_32[0x00020];/* Physical address pointer [63:32] to the physical block list */
-/* -------------- */
- pseudo_bit_t mem_key[0x00020]; /* Memory Key on which the fast registration is executed on. */
-/* -------------- */
- pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes.
- page_size should be less than 20. */
- pseudo_bit_t reserved1[0x00002];
- pseudo_bit_t zb[0x00001]; /* Zero Based Region */
- pseudo_bit_t pbl_ptr_31_8[0x00018]; /* Physical address pointer [31:8] to the physical block list */
-/* -------------- */
- pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region starts */
-/* -------------- */
- pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region starts */
-/* -------------- */
- pseudo_bit_t reg_len_h[0x00020]; /* Region Length[63:32] */
-/* -------------- */
- pseudo_bit_t reg_len_l[0x00020]; /* Region Length[31:0] */
-/* -------------- */
-};
-
-/* 0 */
-
-struct tavorprm_tavor_prm_st { /* Little Endian */
- struct tavorprm_completion_queue_entry_st completion_queue_entry;/* Completion Queue Entry Format */
-/* -------------- */
- pseudo_bit_t reserved0[0x7ff00];
-/* -------------- */
- struct tavorprm_qp_ee_state_transitions_st qp_ee_state_transitions;/* QP/EE State Transitions Command Parameters */
-/* -------------- */
- pseudo_bit_t reserved1[0x7f000];
-/* -------------- */
- struct tavorprm_event_queue_entry_st event_queue_entry;/* Event Queue Entry */
-/* -------------- */
- pseudo_bit_t reserved2[0x7ff00];
-/* -------------- */
- struct tavorprm_completion_event_st completion_event;/* Event_data Field - Completion Event */
-/* -------------- */
- pseudo_bit_t reserved3[0x7ff40];
-/* -------------- */
- struct tavorprm_completion_queue_error_st completion_queue_error;/* Event_data Field - Completion Queue Error */
-/* -------------- */
- pseudo_bit_t reserved4[0x7ff40];
-/* -------------- */
- struct tavorprm_port_state_change_st port_state_change;/* Event_data Field - Port State Change */
-/* -------------- */
- pseudo_bit_t reserved5[0xfff40];
-/* -------------- */
- struct tavorprm_page_fault_event_data_st page_fault_event_data;/* Event_data Field - Page Faults */
-/* -------------- */
- pseudo_bit_t reserved6[0x7ff40];
-/* -------------- */
- struct tavorprm_performance_monitor_event_st performance_monitor_event;/* Event Data Field - Performance Monitor */
-/* -------------- */
- pseudo_bit_t reserved7[0x7ff20];
-/* -------------- */
- struct tavorprm_ntu_qpm_st ntu_qpm; /* NTU QP Map Table Entry */
-/* -------------- */
- pseudo_bit_t reserved8[0x7ff80];
-/* -------------- */
- struct tavorprm_mt23108_type0_st mt23108_type0;/* InfiniHost Type0 Configuration Header */
-/* -------------- */
- pseudo_bit_t reserved9[0x7f800];
-/* -------------- */
- struct tavorprm_qp_ee_event_st qp_ee_event;/* Event_data Field - QP/EE Events */
-/* -------------- */
- pseudo_bit_t reserved10[0x00040];
-/* -------------- */
- struct tavorprm_gpio_event_data_st gpio_event_data;
-/* -------------- */
- pseudo_bit_t reserved11[0x7fe40];
-/* -------------- */
- struct tavorprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */
-/* -------------- */
- pseudo_bit_t reserved12[0x7ff00];
-/* -------------- */
- struct tavorprm_queue_pair_ee_context_entry_st queue_pair_ee_context_entry;/* QP and EE Context Entry */
-/* -------------- */
- pseudo_bit_t reserved13[0x7f800];
-/* -------------- */
- struct tavorprm_address_path_st address_path;/* Address Path */
-/* -------------- */
- pseudo_bit_t reserved14[0x7ff00];
-/* -------------- */
- struct tavorprm_completion_queue_context_st completion_queue_context;/* Completion Queue Context Table Entry */
-/* -------------- */
- pseudo_bit_t reserved15[0x7fe00];
-/* -------------- */
- struct tavorprm_mpt_st mpt; /* Memory Protection Table (MPT) Entry */
-/* -------------- */
- pseudo_bit_t reserved16[0x7fe00];
-/* -------------- */
- struct tavorprm_mtt_st mtt; /* Memory Translation Table (MTT) Entry */
-/* -------------- */
- pseudo_bit_t reserved17[0x7ffc0];
-/* -------------- */
- struct tavorprm_eqc_st eqc; /* Event Queue Context Table Entry */
-/* -------------- */
- pseudo_bit_t reserved18[0x7fe00];
-/* -------------- */
- struct tavorprm_performance_monitors_st performance_monitors;/* Performance Monitors */
-/* -------------- */
- pseudo_bit_t reserved19[0x7ff80];
-/* -------------- */
- struct tavorprm_hca_command_register_st hca_command_register;/* HCA Command Register (HCR) */
-/* -------------- */
- pseudo_bit_t reserved20[0xfff20];
-/* -------------- */
- struct tavorprm_init_hca_st init_hca;/* INIT_HCA & QUERY_HCA Parameters Block */
-/* -------------- */
- pseudo_bit_t reserved21[0x7f000];
-/* -------------- */
- struct tavorprm_qpcbaseaddr_st qpcbaseaddr;/* QPC/EEC/CQC/EQC/RDB Parameters */
-/* -------------- */
- pseudo_bit_t reserved22[0x7fc00];
-/* -------------- */
- struct tavorprm_udavtable_memory_parameters_st udavtable_memory_parameters;/* Memory Access Parameters for UD Address Vector Table */
-/* -------------- */
- pseudo_bit_t reserved23[0x7ffc0];
-/* -------------- */
- struct tavorprm_multicastparam_st multicastparam;/* Multicast Support Parameters */
-/* -------------- */
- pseudo_bit_t reserved24[0x7ff00];
-/* -------------- */
- struct tavorprm_tptparams_st tptparams;/* Translation and Protection Tables Parameters */
-/* -------------- */
- pseudo_bit_t reserved25[0x7ff00];
-/* -------------- */
- struct tavorprm_query_ddr_st query_ddr;/* QUERY_DDR Parameters Block */
-/* -------------- */
- struct tavorprm_access_ddr_st access_ddr;
-/* -------------- */
- pseudo_bit_t reserved26[0x7f700];
-/* -------------- */
- struct tavorprm_dimminfo_st dimminfo;/* Logical DIMM Information */
-/* -------------- */
- pseudo_bit_t reserved27[0x7ff00];
-/* -------------- */
- struct tavorprm_query_fw_st query_fw;/* QUERY_FW Parameters Block */
-/* -------------- */
- pseudo_bit_t reserved28[0x7f800];
-/* -------------- */
- struct tavorprm_query_adapter_st query_adapter;/* QUERY_ADAPTER Parameters Block */
-/* -------------- */
- pseudo_bit_t reserved29[0x7f800];
-/* -------------- */
- struct tavorprm_query_dev_lim_st query_dev_lim;/* Query Device Limitations */
-/* -------------- */
- pseudo_bit_t reserved30[0x7f800];
-/* -------------- */
- struct tavorprm_uar_params_st uar_params;/* UAR Parameters */
-/* -------------- */
- pseudo_bit_t reserved31[0x7ff00];
-/* -------------- */
- struct tavorprm_init_ib_st init_ib; /* INIT_IB Parameters */
-/* -------------- */
- pseudo_bit_t reserved32[0x7f800];
-/* -------------- */
- struct tavorprm_mgm_entry_st mgm_entry;/* Multicast Group Member */
-/* -------------- */
- pseudo_bit_t reserved33[0x7fe00];
-/* -------------- */
- struct tavorprm_set_ib_st set_ib; /* SET_IB Parameters */
-/* -------------- */
- pseudo_bit_t reserved34[0x7fe00];
-/* -------------- */
- struct tavorprm_rd_send_doorbell_st rd_send_doorbell;/* RD-send doorbell */
-/* -------------- */
- pseudo_bit_t reserved35[0x7ff80];
-/* -------------- */
- struct tavorprm_send_doorbell_st send_doorbell;/* Send doorbell */
-/* -------------- */
- pseudo_bit_t reserved36[0x7ffc0];
-/* -------------- */
- struct tavorprm_receive_doorbell_st receive_doorbell;/* Receive doorbell */
-/* -------------- */
- pseudo_bit_t reserved37[0x7ffc0];
-/* -------------- */
- struct tavorprm_cq_cmd_doorbell_st cq_cmd_doorbell;/* CQ Doorbell */
-/* -------------- */
- pseudo_bit_t reserved38[0x7ffc0];
-/* -------------- */
- struct tavorprm_eq_cmd_doorbell_st eq_cmd_doorbell;/* EQ Doorbell */
-/* -------------- */
- pseudo_bit_t reserved39[0x7ffc0];
-/* -------------- */
- struct tavorprm_uar_st uar; /* User Access Region */
-/* -------------- */
- pseudo_bit_t reserved40[0x7c000];
-/* -------------- */
- struct tavorprm_mgmqp_st mgmqp; /* Multicast Group Member QP */
-/* -------------- */
- pseudo_bit_t reserved41[0x7ffe0];
-/* -------------- */
- struct tavorprm_query_debug_msg_st query_debug_msg;/* Query Debug Message */
-/* -------------- */
- pseudo_bit_t reserved42[0x7f800];
-/* -------------- */
- struct tavorprm_sys_en_out_param_st sys_en_out_param;/* SYS_EN Output Parameter */
-/* -------------- */
- pseudo_bit_t reserved43[0x7ffc0];
-/* -------------- */
- struct tavorprm_resize_cq_st resize_cq;/* Resize CQ Input Mailbox */
-/* -------------- */
- pseudo_bit_t reserved44[0x7fe00];
-/* -------------- */
- struct tavorprm_completion_with_error_st completion_with_error;/* Completion with Error CQE */
-/* -------------- */
- pseudo_bit_t reserved45[0x7ff00];
-/* -------------- */
- struct tavorprm_hcr_completion_event_st hcr_completion_event;/* Event_data Field - HCR Completion Event */
-/* -------------- */
- pseudo_bit_t reserved46[0x7ff40];
-/* -------------- */
- struct tavorprm_transport_and_ci_error_counters_st transport_and_ci_error_counters;/* Transport and CI Error Counters */
-/* -------------- */
- pseudo_bit_t reserved47[0x7f000];
-/* -------------- */
- struct tavorprm_performance_counters_st performance_counters;/* Performance Counters */
-/* -------------- */
- pseudo_bit_t reserved48[0x7f800];
-/* -------------- */
- struct tavorprm_query_bar_st query_bar;/* Query BAR */
-/* -------------- */
- pseudo_bit_t reserved49[0x7ffc0];
-/* -------------- */
- struct tavorprm_cfg_schq_st cfg_schq;/* Schedule queues configuration */
-/* -------------- */
- pseudo_bit_t reserved50[0x7f800];
-/* -------------- */
- struct tavorprm_mt23108_configuration_registers_st mt23108_configuration_registers;/* InfiniHost Configuration Registers - Used in Mem-Free mode only */
-/* -------------- */
- pseudo_bit_t reserved51[0x80000];
-/* -------------- */
- pseudo_bit_t reserved52[0x00100];
-/* -------------- */
- pseudo_bit_t reserved53[0x7ff00];
-/* -------------- */
- pseudo_bit_t reserved54[0x00100];
-/* -------------- */
- pseudo_bit_t reserved55[0x7ff00];
-/* -------------- */
- struct tavorprm_srq_context_st srq_context;/* SRQ Context */
-/* -------------- */
- pseudo_bit_t reserved56[0x7ff00];
-/* -------------- */
- struct tavorprm_mod_stat_cfg_st mod_stat_cfg;/* MOD_STAT_CFG */
-/* -------------- */
- pseudo_bit_t reserved57[0x00080];
-/* -------------- */
- pseudo_bit_t reserved58[0x00040];
-/* -------------- */
- pseudo_bit_t reserved59[0x1bff740];
-/* -------------- */
-};
-
-#include "MT23108_PRM_append.h"
-
-#endif /* H_prefix_tavorprm_bits_fixnames_MT23108_PRM_csp_H */
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-
-/***
- *** This file was generated at "Tue Nov 16 17:03:53 2004"
- *** by:
- *** % csp_bf -copyright=/mswg/misc/license-header.txt -bits MT23108_PRM_append.csp
- ***/
-
-#ifndef H_bits_MT23108_PRM_append_csp_H
-#define H_bits_MT23108_PRM_append_csp_H
-
-
-/* Gather entry with inline data */
-
-struct wqe_segment_data_inline_st { /* Little Endian */
- pseudo_bit_t byte_count[0x0000a]; /* Not including padding for 16Byte chunks */
- pseudo_bit_t reserved0[0x00015];
- pseudo_bit_t always1[0x00001];
-/* -------------- */
- pseudo_bit_t data[0x00020]; /* Data may be more this segment size - in 16Byte chunks */
-/* -------------- */
-};
-
-/* Scatter/Gather entry with a pointer */
-
-struct wqe_segment_data_ptr_st { /* Little Endian */
- pseudo_bit_t byte_count[0x0001f];
- pseudo_bit_t always0[0x00001];
-/* -------------- */
- pseudo_bit_t l_key[0x00020];
-/* -------------- */
- pseudo_bit_t local_address_h[0x00020];
-/* -------------- */
- pseudo_bit_t local_address_l[0x00020];
-/* -------------- */
-};
-
-/* */
-
-struct wqe_segment_atomic_st { /* Little Endian */
- pseudo_bit_t swap_add_h[0x00020];
-/* -------------- */
- pseudo_bit_t swap_add_l[0x00020];
-/* -------------- */
- pseudo_bit_t compare_h[0x00020];
-/* -------------- */
- pseudo_bit_t compare_l[0x00020];
-/* -------------- */
-};
-
-/* */
-
-struct wqe_segment_remote_address_st { /* Little Endian */
- pseudo_bit_t remote_virt_addr_h[0x00020];
-/* -------------- */
- pseudo_bit_t remote_virt_addr_l[0x00020];
-/* -------------- */
- pseudo_bit_t rkey[0x00020];
-/* -------------- */
- pseudo_bit_t reserved0[0x00020];
-/* -------------- */
-};
-
-/* Bind memory window segment */
-
-struct wqe_segment_bind_st { /* Little Endian */
- pseudo_bit_t reserved0[0x0001d];
- pseudo_bit_t rr[0x00001]; /* Remote read */
- pseudo_bit_t rw[0x00001]; /* Remote write */
- pseudo_bit_t a[0x00001]; /* atomic */
-/* -------------- */
- pseudo_bit_t reserved1[0x00020];
-/* -------------- */
- pseudo_bit_t new_rkey[0x00020];
-/* -------------- */
- pseudo_bit_t region_lkey[0x00020];
-/* -------------- */
- pseudo_bit_t start_address_h[0x00020];
-/* -------------- */
- pseudo_bit_t start_address_l[0x00020];
-/* -------------- */
- pseudo_bit_t length_h[0x00020];
-/* -------------- */
- pseudo_bit_t length_l[0x00020];
-/* -------------- */
-};
-
-/* */
-
-struct wqe_segment_ud_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00020];
-/* -------------- */
- pseudo_bit_t l_key[0x00020]; /* memory key for UD AV */
-/* -------------- */
- pseudo_bit_t av_address_63_32[0x00020];
-/* -------------- */
- pseudo_bit_t reserved1[0x00005];
- pseudo_bit_t av_address_31_5[0x0001b];
-/* -------------- */
- pseudo_bit_t reserved2[0x00080];
-/* -------------- */
- pseudo_bit_t destination_qp[0x00018];
- pseudo_bit_t reserved3[0x00008];
-/* -------------- */
- pseudo_bit_t q_key[0x00020];
-/* -------------- */
- pseudo_bit_t reserved4[0x00040];
-/* -------------- */
-};
-
-/* */
-
-struct wqe_segment_rd_st { /* Little Endian */
- pseudo_bit_t destination_qp[0x00018];
- pseudo_bit_t reserved0[0x00008];
-/* -------------- */
- pseudo_bit_t q_key[0x00020];
-/* -------------- */
- pseudo_bit_t reserved1[0x00040];
-/* -------------- */
-};
-
-/* */
-
-struct wqe_segment_ctrl_recv_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00002];
- pseudo_bit_t e[0x00001]; /* WQE event */
- pseudo_bit_t c[0x00001]; /* Create CQE (for "requested signalling" QP) */
- pseudo_bit_t reserved1[0x0001c];
-/* -------------- */
- pseudo_bit_t reserved2[0x00020];
-/* -------------- */
-};
-
-/* */
-
-struct wqe_segment_ctrl_mlx_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00002];
- pseudo_bit_t e[0x00001]; /* WQE event */
- pseudo_bit_t c[0x00001]; /* Create CQE (for "requested signalling" QP) */
- pseudo_bit_t reserved1[0x00004];
- pseudo_bit_t sl[0x00004];
- pseudo_bit_t max_statrate[0x00003];
- pseudo_bit_t reserved2[0x00001];
- pseudo_bit_t slr[0x00001]; /* 0= take slid from port. 1= take slid from given headers */
- pseudo_bit_t v15[0x00001]; /* Send packet over VL15 */
- pseudo_bit_t reserved3[0x0000e];
-/* -------------- */
- pseudo_bit_t vcrc[0x00010]; /* Packet's VCRC (if not 0 - otherwise computed by HW) */
- pseudo_bit_t rlid[0x00010]; /* Destination LID (must match given headers) */
-/* -------------- */
-};
-
-/* */
-
-struct wqe_segment_ctrl_send_st { /* Little Endian */
- pseudo_bit_t always1[0x00001];
- pseudo_bit_t s[0x00001]; /* Solicited event */
- pseudo_bit_t e[0x00001]; /* WQE event */
- pseudo_bit_t c[0x00001]; /* Create CQE (for "requested signalling" QP) */
- pseudo_bit_t reserved0[0x0001c];
-/* -------------- */
- pseudo_bit_t immediate[0x00020];
-/* -------------- */
-};
-
-/* */
-
-struct wqe_segment_next_st { /* Little Endian */
- pseudo_bit_t nopcode[0x00005]; /* next opcode */
- pseudo_bit_t reserved0[0x00001];
- pseudo_bit_t nda_31_6[0x0001a]; /* NDA[31:6] */
-/* -------------- */
- pseudo_bit_t nds[0x00006];
- pseudo_bit_t f[0x00001]; /* fence bit */
- pseudo_bit_t dbd[0x00001]; /* doorbell rung */
- pseudo_bit_t nee[0x00018]; /* next EE */
-/* -------------- */
-};
-#endif /* H_bits_MT23108_PRM_append_csp_H */
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-
-/***
- *** This file was generated at "Tue Nov 22 15:21:23 2005"
- *** by:
- *** % csp_bf -copyright=/mswg/misc/license-header.txt -prefix arbelprm_ -bits -fixnames MT25218_PRM.csp
- ***/
-
-#ifndef H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H
-#define H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H
-
-#include "bit_ops.h"
-
-
-/* UD Address Vector */
-
-struct arbelprm_ud_address_vector_st { /* Little Endian */
- pseudo_bit_t pd[0x00018]; /* Protection Domain */
- pseudo_bit_t port_number[0x00002]; /* Port number
- 1 - Port 1
- 2 - Port 2
- other - reserved */
- pseudo_bit_t reserved0[0x00006];
-/* -------------- */
- pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */
- pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */
- pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */
- pseudo_bit_t reserved1[0x00008];
-/* -------------- */
- pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */
- pseudo_bit_t max_stat_rate[0x00003];/* Maximum static rate control.
- 0 - 4X injection rate
- 1 - 1X injection rate
- other - reserved
- */
- pseudo_bit_t reserved2[0x00001];
- pseudo_bit_t msg[0x00002]; /* Max Message size, size is 256*2^MSG bytes */
- pseudo_bit_t reserved3[0x00002];
- pseudo_bit_t mgid_index[0x00006]; /* Index to port GID table
- mgid_index = (port_number-1) * 2^log_max_gid + gid_index
- Where:
- 1. log_max_gid is taken from QUERY_DEV_LIM command
- 2. gid_index is the index to the GID table */
- pseudo_bit_t reserved4[0x0000a];
-/* -------------- */
- pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */
- pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */
- pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */
-/* -------------- */
- pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */
-/* -------------- */
- pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */
-/* -------------- */
- pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */
-/* -------------- */
- pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] if G bit is set. Must be set to 0x2 if G bit is cleared. */
-/* -------------- */
-};
-
-/* Send doorbell */
-
-struct arbelprm_send_doorbell_st { /* Little Endian */
- pseudo_bit_t nopcode[0x00005]; /* Opcode of descriptor to be executed */
- pseudo_bit_t f[0x00001]; /* Fence bit. If set, descriptor is fenced */
- pseudo_bit_t reserved0[0x00002];
- pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation excluding the newly posted WQEs in this doorbell. Should be zero for the first doorbell on the QP */
- pseudo_bit_t wqe_cnt[0x00008]; /* Number of WQEs posted with this doorbell. Must be grater then zero. */
-/* -------------- */
- pseudo_bit_t nds[0x00006]; /* Next descriptor size (in 16-byte chunks) */
- pseudo_bit_t reserved1[0x00002];
- pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */
-/* -------------- */
-};
-
-/* ACCESS_LAM_inject_errors_input_modifier */
-
-struct arbelprm_access_lam_inject_errors_input_modifier_st { /* Little Endian */
- pseudo_bit_t index3[0x00007];
- pseudo_bit_t q3[0x00001];
- pseudo_bit_t index2[0x00007];
- pseudo_bit_t q2[0x00001];
- pseudo_bit_t index1[0x00007];
- pseudo_bit_t q1[0x00001];
- pseudo_bit_t index0[0x00007];
- pseudo_bit_t q0[0x00001];
-/* -------------- */
-};
-
-/* ACCESS_LAM_inject_errors_input_parameter */
-
-struct arbelprm_access_lam_inject_errors_input_parameter_st { /* Little Endian */
- pseudo_bit_t ba[0x00002]; /* Bank Address */
- pseudo_bit_t da[0x00002]; /* Dimm Address */
- pseudo_bit_t reserved0[0x0001c];
-/* -------------- */
- pseudo_bit_t ra[0x00010]; /* Row Address */
- pseudo_bit_t ca[0x00010]; /* Column Address */
-/* -------------- */
-};
-
-/* */
-
-struct arbelprm_recv_wqe_segment_next_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00006];
- pseudo_bit_t nda_31_6[0x0001a]; /* Next WQE address, low 32 bit. WQE address must be aligned to 64-byte boundary (6 LSB are forced ZERO). */
-/* -------------- */
- pseudo_bit_t nds[0x00006]; /* Next WQE size in OctoWords (16 bytes).
- Zero value in NDS field signals end of WQEs? chain.
- */
- pseudo_bit_t reserved1[0x0001a];
-/* -------------- */
-};
-
-/* Send wqe segment data inline */
-
-struct arbelprm_wqe_segment_data_inline_st { /* Little Endian */
- pseudo_bit_t byte_count[0x0000a]; /* Not including padding for 16Byte chunks */
- pseudo_bit_t reserved0[0x00015];
- pseudo_bit_t always1[0x00001];
-/* -------------- */
- pseudo_bit_t data[0x00018]; /* Data may be more this segment size - in 16Byte chunks */
- pseudo_bit_t reserved1[0x00008];
-/* -------------- */
- pseudo_bit_t reserved2[0x00040];
-/* -------------- */
-};
-
-/* Send wqe segment data ptr */
-
-struct arbelprm_wqe_segment_data_ptr_st { /* Little Endian */
- pseudo_bit_t byte_count[0x0001f];
- pseudo_bit_t always0[0x00001];
-/* -------------- */
- pseudo_bit_t l_key[0x00020];
-/* -------------- */
- pseudo_bit_t local_address_h[0x00020];
-/* -------------- */
- pseudo_bit_t local_address_l[0x00020];
-/* -------------- */
-};
-
-/* Send wqe segment rd */
-
-struct arbelprm_local_invalidate_segment_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00040];
-/* -------------- */
- pseudo_bit_t mem_key[0x00018];
- pseudo_bit_t reserved1[0x00008];
-/* -------------- */
- pseudo_bit_t reserved2[0x000a0];
-/* -------------- */
-};
-
-/* Fast_Registration_Segment */
-
-struct arbelprm_fast_registration_segment_st { /* Little Endian */
- pseudo_bit_t reserved0[0x0001b];
- pseudo_bit_t lr[0x00001]; /* If set - Local Read access will be enabled */
- pseudo_bit_t lw[0x00001]; /* If set - Local Write access will be enabled */
- pseudo_bit_t rr[0x00001]; /* If set - Remote Read access will be enabled */
- pseudo_bit_t rw[0x00001]; /* If set - Remote Write access will be enabled */
- pseudo_bit_t a[0x00001]; /* If set - Remote Atomic access will be enabled */
-/* -------------- */
- pseudo_bit_t pbl_ptr_63_32[0x00020];/* Physical address pointer [63:32] to the physical buffer list */
-/* -------------- */
- pseudo_bit_t mem_key[0x00020]; /* Memory Key on which the fast registration is executed on. */
-/* -------------- */
- pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes.
- page_size should be less than 20. */
- pseudo_bit_t reserved1[0x00002];
- pseudo_bit_t zb[0x00001]; /* Zero Based Region */
- pseudo_bit_t pbl_ptr_31_8[0x00018]; /* Physical address pointer [31:8] to the physical buffer list */
-/* -------------- */
- pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region starts */
-/* -------------- */
- pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region starts */
-/* -------------- */
- pseudo_bit_t reg_len_h[0x00020]; /* Region Length[63:32] */
-/* -------------- */
- pseudo_bit_t reg_len_l[0x00020]; /* Region Length[31:0] */
-/* -------------- */
-};
-
-/* Send wqe segment atomic */
-
-struct arbelprm_wqe_segment_atomic_st { /* Little Endian */
- pseudo_bit_t swap_add_h[0x00020];
-/* -------------- */
- pseudo_bit_t swap_add_l[0x00020];
-/* -------------- */
- pseudo_bit_t compare_h[0x00020];
-/* -------------- */
- pseudo_bit_t compare_l[0x00020];
-/* -------------- */
-};
-
-/* Send wqe segment remote address */
-
-struct arbelprm_wqe_segment_remote_address_st { /* Little Endian */
- pseudo_bit_t remote_virt_addr_h[0x00020];
-/* -------------- */
- pseudo_bit_t remote_virt_addr_l[0x00020];
-/* -------------- */
- pseudo_bit_t rkey[0x00020];
-/* -------------- */
- pseudo_bit_t reserved0[0x00020];
-/* -------------- */
-};
-
-/* end wqe segment bind */
-
-struct arbelprm_wqe_segment_bind_st { /* Little Endian */
- pseudo_bit_t reserved0[0x0001d];
- pseudo_bit_t rr[0x00001]; /* If set, Remote Read Enable for bound window. */
- pseudo_bit_t rw[0x00001]; /* If set, Remote Write Enable for bound window.
- */
- pseudo_bit_t a[0x00001]; /* If set, Atomic Enable for bound window. */
-/* -------------- */
- pseudo_bit_t reserved1[0x0001e];
- pseudo_bit_t zb[0x00001]; /* If set, Window is Zero Based. */
- pseudo_bit_t type[0x00001]; /* Window type.
- 0 - Type one window
- 1 - Type two window
- */
-/* -------------- */
- pseudo_bit_t new_rkey[0x00020]; /* The new RKey of window to bind */
-/* -------------- */
- pseudo_bit_t region_lkey[0x00020]; /* Local key of region, which window will be bound to */
-/* -------------- */
- pseudo_bit_t start_address_h[0x00020];
-/* -------------- */
- pseudo_bit_t start_address_l[0x00020];
-/* -------------- */
- pseudo_bit_t length_h[0x00020];
-/* -------------- */
- pseudo_bit_t length_l[0x00020];
-/* -------------- */
-};
-
-/* Send wqe segment ud */
-
-struct arbelprm_wqe_segment_ud_st { /* Little Endian */
- struct arbelprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */
-/* -------------- */
- pseudo_bit_t destination_qp[0x00018];
- pseudo_bit_t reserved0[0x00008];
-/* -------------- */
- pseudo_bit_t q_key[0x00020];
-/* -------------- */
- pseudo_bit_t reserved1[0x00040];
-/* -------------- */
-};
-
-/* Send wqe segment rd */
-
-struct arbelprm_wqe_segment_rd_st { /* Little Endian */
- pseudo_bit_t destination_qp[0x00018];
- pseudo_bit_t reserved0[0x00008];
-/* -------------- */
- pseudo_bit_t q_key[0x00020];
-/* -------------- */
- pseudo_bit_t reserved1[0x00040];
-/* -------------- */
-};
-
-/* Send wqe segment ctrl */
-
-struct arbelprm_wqe_segment_ctrl_send_st { /* Little Endian */
- pseudo_bit_t always1[0x00001];
- pseudo_bit_t s[0x00001]; /* Solicited Event bit. If set, SE (Solicited Event) bit is set in the (last packet of) message. */
- pseudo_bit_t e[0x00001]; /* Event bit. If set, event is generated upon WQE?s completion, if QP is allowed to generate an event. Every WQE with E-bit set generates an event. The C bit must be set on unsignalled QPs if the E bit is set. */
- pseudo_bit_t c[0x00001]; /* Completion Queue bit. Valid for unsignalled QPs only. If set, the CQ is updated upon WQE?s completion */
- pseudo_bit_t ip[0x00001]; /* When set, InfiniHost III Ex will calculate the IP checksum of the IP header that is present immediately after the IPoverIB encapsulation header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first IP header following the IPoverIB encapsulation header. Not Valid for IPv6 packets */
- pseudo_bit_t tcp_udp[0x00001]; /* When set, InfiniHost III Ex will calculate the TCP/UDP checksum of the packet that is present immediately after the IP header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first TCP header following the IP header. This bit may be set only if the entire TCP/UDP segment is present in one IB packet */
- pseudo_bit_t reserved0[0x00001];
- pseudo_bit_t so[0x00001]; /* Strong Ordering - when set, the WQE will be executed only after all previous WQEs have been executed. Can be set for RC WQEs only. This bit must be set in type two BIND, Fast Registration and Local invalidate operations. */
- pseudo_bit_t reserved1[0x00018];
-/* -------------- */
- pseudo_bit_t immediate[0x00020]; /* If the OpCode encodes an operation with Immediate (RDMA-write/SEND), This field will hold the Immediate data to be sent. If the OpCode encodes send and invalidate operations, this field holds the Invalidation key to be inserted into the packet; otherwise, this field is reserved. */
-/* -------------- */
-};
-
-/* Send wqe segment next */
-
-struct arbelprm_wqe_segment_next_st { /* Little Endian */
- pseudo_bit_t nopcode[0x00005]; /* Next Opcode: OpCode to be used in the next WQE. Encodes the type of operation to be executed on the QP:
- ?00000? - NOP. WQE with this opcode creates a completion, but does nothing else
- ?01000? - RDMA-write
- ?01001? - RDMA-Write with Immediate
- ?10000? - RDMA-read
- ?10001? - Atomic Compare & swap
- ?10010? - Atomic Fetch & Add
- ?11000? - Bind memory window
-
- The encoding for the following operations depends on the QP type:
- For RC, UC and RD QP:
- ?01010? - SEND
- ?01011? - SEND with Immediate
-
- For UD QP:
- the encoding depends on the values of bit[31] of the Q_key field in the Datagram Segment (see Table 39, ?Unreliable Datagram Segment Format - Pointers,? on page 101) of
- both the current WQE and the next WQE, as follows:
-
- If the last WQE Q_Key bit[31] is clear and the next WQE Q_key bit[31] is set :
- ?01000? - SEND
- ?01001? - SEND with Immediate
-
- otherwise (if the next WQE Q_key bit[31] is cleared, or the last WQE Q_Key bit[31] is set):
- ?01010? - SEND
- ?01011? - SEND with Immediate
-
- All other opcode values are RESERVED, and will result in invalid operation execution. */
- pseudo_bit_t reserved0[0x00001];
- pseudo_bit_t nda_31_6[0x0001a]; /* Next WQE address, low 32 bit. WQE address must be aligned to 64-byte boundary (6 LSB are forced ZERO). */
-/* -------------- */
- pseudo_bit_t nds[0x00006]; /* Next WQE size in OctoWords (16 bytes).
- Zero value in NDS field signals end of WQEs? chain.
- */
- pseudo_bit_t f[0x00001]; /* Fence bit. If set, next WQE will start execution only after all previous Read/Atomic WQEs complete. */
- pseudo_bit_t always1[0x00001];
- pseudo_bit_t reserved1[0x00018];
-/* -------------- */
-};
-
-/* Address Path */
-
-struct arbelprm_address_path_st { /* Little Endian */
- pseudo_bit_t pkey_index[0x00007]; /* PKey table index */
- pseudo_bit_t reserved0[0x00011];
- pseudo_bit_t port_number[0x00002]; /* Specific port associated with this QP/EE.
- 1 - Port 1
- 2 - Port 2
- other - reserved */
- pseudo_bit_t reserved1[0x00006];
-/* -------------- */
- pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */
- pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */
- pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */
- pseudo_bit_t reserved2[0x00005];
- pseudo_bit_t rnr_retry[0x00003]; /* RNR retry count (see C9-132 in IB spec Vol 1)
- 0-6 - number of retries
- 7 - infinite */
-/* -------------- */
- pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */
- pseudo_bit_t max_stat_rate[0x00003];/* Maximum static rate control.
- 0 - 100% injection rate
- 1 - 25% injection rate
- 2 - 12.5% injection rate
- 3 - 50% injection rate
- other - reserved */
- pseudo_bit_t reserved3[0x00005];
- pseudo_bit_t mgid_index[0x00006]; /* Index to port GID table */
- pseudo_bit_t reserved4[0x00005];
- pseudo_bit_t ack_timeout[0x00005]; /* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details.
- The transport timer is set to 4.096us*2^ack_timeout, if ack_timeout is 0 then transport timer is disabled. */
-/* -------------- */
- pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */
- pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */
- pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */
-/* -------------- */
- pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */
-/* -------------- */
- pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */
-/* -------------- */
- pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */
-/* -------------- */
- pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] */
-/* -------------- */
-};
-
-/* HCA Command Register (HCR) */
-
-struct arbelprm_hca_command_register_st { /* Little Endian */
- pseudo_bit_t in_param_h[0x00020]; /* Input Parameter: parameter[63:32] or pointer[63:32] to input mailbox (see command description) */
-/* -------------- */
- pseudo_bit_t in_param_l[0x00020]; /* Input Parameter: parameter[31:0] or pointer[31:0] to input mailbox (see command description) */
-/* -------------- */
- pseudo_bit_t input_modifier[0x00020];/* Input Parameter Modifier */
-/* -------------- */
- pseudo_bit_t out_param_h[0x00020]; /* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */
-/* -------------- */
- pseudo_bit_t out_param_l[0x00020]; /* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */
-/* -------------- */
- pseudo_bit_t reserved0[0x00010];
- pseudo_bit_t token[0x00010]; /* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */
-/* -------------- */
- pseudo_bit_t opcode[0x0000c]; /* Command opcode */
- pseudo_bit_t opcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */
- pseudo_bit_t reserved1[0x00006];
- pseudo_bit_t e[0x00001]; /* Event Request
- 0 - Don't report event (software will poll the GO bit)
- 1 - Report event to EQ when the command completes */
- pseudo_bit_t go[0x00001]; /* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR)
- Software can write to the HCR only if Go bit is cleared.
- Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */
- pseudo_bit_t status[0x00008]; /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared)
- 0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */
-/* -------------- */
-};
-
-/* CQ Doorbell */
-
-struct arbelprm_cq_cmd_doorbell_st { /* Little Endian */
- pseudo_bit_t cqn[0x00018]; /* CQ number accessed */
- pseudo_bit_t cmd[0x00003]; /* Command to be executed on CQ
- 0x0 - Reserved
- 0x1 - Request notification for next Solicited completion event. CQ_param specifies the current CQ Consumer Counter.
- 0x2 - Request notification for next Solicited or Unsolicited completion event. CQ_param specifies the current CQ Consumer Counter.
- 0x3 - Request notification for multiple completions (Arm-N). CQ_param specifies the value of the CQ Counter that when reached by HW (i.e. HW generates a CQE into this Counter) Event will be generated
- Other - Reserved */
- pseudo_bit_t reserved0[0x00001];
- pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - This field should be incremented upon receiving completion notification of the respective CQ.
- This transition is done by ringing Request notification for next Solicited, Request notification for next Solicited or Unsolicited
- completion or Request notification for multiple completions doorbells after receiving completion notification.
- This field is initialized to Zero */
- pseudo_bit_t reserved1[0x00002];
-/* -------------- */
- pseudo_bit_t cq_param[0x00020]; /* parameter to be used by CQ command */
-/* -------------- */
-};
-
-/* RD-send doorbell */
-
-struct arbelprm_rd_send_doorbell_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00008];
- pseudo_bit_t een[0x00018]; /* End-to-end context number (reliable datagram)
- Must be zero for Nop and Bind operations */
-/* -------------- */
- pseudo_bit_t reserved1[0x00008];
- pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */
-/* -------------- */
- struct arbelprm_send_doorbell_st send_doorbell;/* Send Parameters */
-/* -------------- */
-};
-
-/* Multicast Group Member QP */
-
-struct arbelprm_mgmqp_st { /* Little Endian */
- pseudo_bit_t qpn_i[0x00018]; /* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */
- pseudo_bit_t reserved0[0x00007];
- pseudo_bit_t qi[0x00001]; /* Qi: QPN_i is valid */
-/* -------------- */
-};
-
-/* vsd */
-
-struct arbelprm_vsd_st { /* Little Endian */
- pseudo_bit_t vsd_dw0[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw1[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw2[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw3[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw4[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw5[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw6[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw7[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw8[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw9[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw10[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw11[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw12[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw13[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw14[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw15[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw16[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw17[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw18[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw19[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw20[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw21[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw22[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw23[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw24[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw25[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw26[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw27[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw28[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw29[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw30[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw31[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw32[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw33[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw34[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw35[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw36[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw37[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw38[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw39[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw40[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw41[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw42[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw43[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw44[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw45[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw46[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw47[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw48[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw49[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw50[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw51[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw52[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw53[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw54[0x00020];
-/* -------------- */
- pseudo_bit_t vsd_dw55[0x00020];
-/* -------------- */
-};
-
-/* ACCESS_LAM_inject_errors */
-
-struct arbelprm_access_lam_inject_errors_st { /* Little Endian */
- struct arbelprm_access_lam_inject_errors_input_parameter_st access_lam_inject_errors_input_parameter;
-/* -------------- */
- struct arbelprm_access_lam_inject_errors_input_modifier_st access_lam_inject_errors_input_modifier;
-/* -------------- */
- pseudo_bit_t reserved0[0x00020];
-/* -------------- */
-};
-
-/* Logical DIMM Information */
-
-struct arbelprm_dimminfo_st { /* Little Endian */
- pseudo_bit_t dimmsize[0x00010]; /* Size of DIMM in units of 2^20 Bytes. This value is valid only when DIMMStatus is 0. */
- pseudo_bit_t reserved0[0x00008];
- pseudo_bit_t dimmstatus[0x00001]; /* DIMM Status
- 0 - Enabled
- 1 - Disabled
- */
- pseudo_bit_t dh[0x00001]; /* When set, the DIMM is Hidden and can not be accessed from the PCI bus. */
- pseudo_bit_t wo[0x00001]; /* When set, the DIMM is write only.
- If data integrity is configured (other than none), the DIMM must be
- only targeted by write transactions where the address and size are multiples of 16 bytes. */
- pseudo_bit_t reserved1[0x00005];
-/* -------------- */
- pseudo_bit_t spd[0x00001]; /* 0 - DIMM SPD was read from DIMM
- 1 - DIMM SPD was read from InfiniHost-III-EX NVMEM */
- pseudo_bit_t sladr[0x00003]; /* SPD Slave Address 3 LSBits.
- Valid only if spd bit is 0. */
- pseudo_bit_t sock_num[0x00002]; /* DIMM socket number (for double sided DIMM one of the two numbers will be reported) */
- pseudo_bit_t syn[0x00004]; /* Error syndrome (valid regardless of status value)
- 0 - DIMM has no error
- 1 - SPD error (e.g. checksum error, no response, error while reading)
- 2 - DIMM out of bounds (e.g. DIMM rows number is not between 7 and 14, DIMM type is not 2)
- 3 - DIMM conflict (e.g. mix of registered and unbuffered DIMMs, CAS latency conflict)
- 5 - DIMM size trimmed due to configuration (size exceeds)
- other - Error, reserved
- */
- pseudo_bit_t reserved2[0x00016];
-/* -------------- */
- pseudo_bit_t reserved3[0x00040];
-/* -------------- */
- pseudo_bit_t dimm_start_adr_h[0x00020];/* DIMM memory start address [63:32]. This value is valid only when DIMMStatus is 0. */
-/* -------------- */
- pseudo_bit_t dimm_start_adr_l[0x00020];/* DIMM memory start address [31:0]. This value is valid only when DIMMStatus is 0. */
-/* -------------- */
- pseudo_bit_t reserved4[0x00040];
-/* -------------- */
-};
-
-/* UAR Parameters */
-
-struct arbelprm_uar_params_st { /* Little Endian */
- pseudo_bit_t uar_base_addr_h[0x00020];/* UAR Base (pyhsical) Address [63:32] (QUERY_HCA only) */
-/* -------------- */
- pseudo_bit_t reserved0[0x00014];
- pseudo_bit_t uar_base_addr_l[0x0000c];/* UAR Base (pyhsical) Address [31:20] (QUERY_HCA only) */
-/* -------------- */
- pseudo_bit_t uar_page_sz[0x00008]; /* This field defines the size of each UAR page.
- Size of UAR Page is 4KB*2^UAR_Page_Size */
- pseudo_bit_t log_max_uars[0x00004]; /* Number of UARs supported is 2^log_max_UARs */
- pseudo_bit_t reserved1[0x00004];
- pseudo_bit_t log_uar_entry_sz[0x00006];/* Size of UAR Context entry is 2^log_uar_sz in 4KByte pages */
- pseudo_bit_t reserved2[0x0000a];
-/* -------------- */
- pseudo_bit_t reserved3[0x00020];
-/* -------------- */
- pseudo_bit_t uar_scratch_base_addr_h[0x00020];/* Base address of UAR scratchpad [63:32].
- Number of entries in table is 2^log_max_uars.
- Table must be aligned to its size */
-/* -------------- */
- pseudo_bit_t uar_scratch_base_addr_l[0x00020];/* Base address of UAR scratchpad [31:0].
- Number of entries in table is 2^log_max_uars.
- Table must be aligned to its size. */
-/* -------------- */
- pseudo_bit_t uar_context_base_addr_h[0x00020];/* Base address of UAR Context [63:32].
- Number of entries in table is 2^log_max_uars.
- Table must be aligned to its size. */
-/* -------------- */
- pseudo_bit_t uar_context_base_addr_l[0x00020];/* Base address of UAR Context [31:0].
- Number of entries in table is 2^log_max_uars.
- Table must be aligned to its size. */
-/* -------------- */
-};
-
-/* Translation and Protection Tables Parameters */
-
-struct arbelprm_tptparams_st { /* Little Endian */
- pseudo_bit_t mpt_base_adr_h[0x00020];/* MPT - Memory Protection Table base physical address [63:32].
- Entry size is 64 bytes.
- Table must be aligned to its size.
- Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
-/* -------------- */
- pseudo_bit_t mpt_base_adr_l[0x00020];/* MPT - Memory Protection Table base physical address [31:0].
- Entry size is 64 bytes.
- Table must be aligned to its size.
- Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
-/* -------------- */
- pseudo_bit_t log_mpt_sz[0x00006]; /* Log (base 2) of the number of region/windows entries in the MPT table. */
- pseudo_bit_t reserved0[0x00002];
- pseudo_bit_t pfto[0x00005]; /* Page Fault RNR Timeout -
- The field returned in RNR Naks generated when a page fault is detected.
- It has no effect when on-demand-paging is not used. */
- pseudo_bit_t reserved1[0x00013];
-/* -------------- */
- pseudo_bit_t reserved2[0x00020];
-/* -------------- */
- pseudo_bit_t mtt_base_addr_h[0x00020];/* MTT - Memory Translation table base physical address [63:32].
- Table must be aligned to its size.
- Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
-/* -------------- */
- pseudo_bit_t mtt_base_addr_l[0x00020];/* MTT - Memory Translation table base physical address [31:0].
- Table must be aligned to its size.
- Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
-/* -------------- */
- pseudo_bit_t reserved3[0x00040];
-/* -------------- */
-};
-
-/* Multicast Support Parameters */
-
-struct arbelprm_multicastparam_st { /* Little Endian */
- pseudo_bit_t mc_base_addr_h[0x00020];/* Base Address of the Multicast Table [63:32].
- The base address must be aligned to the entry size.
- Address may be set to 0xFFFFFFFF if multicast is not supported. */
-/* -------------- */
- pseudo_bit_t mc_base_addr_l[0x00020];/* Base Address of the Multicast Table [31:0].
- The base address must be aligned to the entry size.
- Address may be set to 0xFFFFFFFF if multicast is not supported. */
-/* -------------- */
- pseudo_bit_t reserved0[0x00040];
-/* -------------- */
- pseudo_bit_t log_mc_table_entry_sz[0x00010];/* Log2 of the Size of multicast group member (MGM) entry.
- Must be greater than 5 (to allow CTRL and GID sections).
- That implies the number of QPs per MC table entry. */
- pseudo_bit_t reserved1[0x00010];
-/* -------------- */
- pseudo_bit_t mc_table_hash_sz[0x00011];/* Number of entries in multicast DGID hash table (must be power of 2)
- INIT_HCA - the required number of entries
- QUERY_HCA - the actual number of entries assigned by firmware (will be less than or equal to the amount required in INIT_HCA) */
- pseudo_bit_t reserved2[0x0000f];
-/* -------------- */
- pseudo_bit_t log_mc_table_sz[0x00005];/* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */
- pseudo_bit_t reserved3[0x00013];
- pseudo_bit_t mc_hash_fn[0x00003]; /* Multicast hash function
- 0 - Default hash function
- other - reserved */
- pseudo_bit_t reserved4[0x00005];
-/* -------------- */
- pseudo_bit_t reserved5[0x00020];
-/* -------------- */
-};
-
-/* QPC/EEC/CQC/EQC/RDB Parameters */
-
-struct arbelprm_qpcbaseaddr_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00080];
-/* -------------- */
- pseudo_bit_t qpc_base_addr_h[0x00020];/* QPC Base Address [63:32]
- Table must be aligned on its size */
-/* -------------- */
- pseudo_bit_t log_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */
- pseudo_bit_t reserved1[0x00002];
- pseudo_bit_t qpc_base_addr_l[0x00019];/* QPC Base Address [31:7]
- Table must be aligned on its size */
-/* -------------- */
- pseudo_bit_t reserved2[0x00040];
-/* -------------- */
- pseudo_bit_t eec_base_addr_h[0x00020];/* EEC Base Address [63:32]
- Table must be aligned on its size.
- Address may be set to 0xFFFFFFFF if RD is not supported. */
-/* -------------- */
- pseudo_bit_t log_num_of_ee[0x00005];/* Log base 2 of number of supported EEs. */
- pseudo_bit_t reserved3[0x00002];
- pseudo_bit_t eec_base_addr_l[0x00019];/* EEC Base Address [31:7]
- Table must be aligned on its size
- Address may be set to 0xFFFFFFFF if RD is not supported. */
-/* -------------- */
- pseudo_bit_t srqc_base_addr_h[0x00020];/* SRQ Context Base Address [63:32]
- Table must be aligned on its size
- Address may be set to 0xFFFFFFFF if SRQ is not supported. */
-/* -------------- */
- pseudo_bit_t log_num_of_srq[0x00005];/* Log base 2 of number of supported SRQs. */
- pseudo_bit_t srqc_base_addr_l[0x0001b];/* SRQ Context Base Address [31:5]
- Table must be aligned on its size
- Address may be set to 0xFFFFFFFF if SRQ is not supported. */
-/* -------------- */
- pseudo_bit_t cqc_base_addr_h[0x00020];/* CQC Base Address [63:32]
- Table must be aligned on its size */
-/* -------------- */
- pseudo_bit_t log_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */
- pseudo_bit_t reserved4[0x00001];
- pseudo_bit_t cqc_base_addr_l[0x0001a];/* CQC Base Address [31:6]
- Table must be aligned on its size */
-/* -------------- */
- pseudo_bit_t reserved5[0x00040];
-/* -------------- */
- pseudo_bit_t eqpc_base_addr_h[0x00020];/* Extended QPC Base Address [63:32]
- Table has same number of entries as QPC table.
- Table must be aligned to entry size. */
-/* -------------- */
- pseudo_bit_t eqpc_base_addr_l[0x00020];/* Extended QPC Base Address [31:0]
- Table has same number of entries as QPC table.
- Table must be aligned to entry size. */
-/* -------------- */
- pseudo_bit_t reserved6[0x00040];
-/* -------------- */
- pseudo_bit_t eeec_base_addr_h[0x00020];/* Extended EEC Base Address [63:32]
- Table has same number of entries as EEC table.
- Table must be aligned to entry size.
- Address may be set to 0xFFFFFFFF if RD is not supported. */
-/* -------------- */
- pseudo_bit_t eeec_base_addr_l[0x00020];/* Extended EEC Base Address [31:0]
- Table has same number of entries as EEC table.
- Table must be aligned to entry size.
- Address may be set to 0xFFFFFFFF if RD is not supported. */
-/* -------------- */
- pseudo_bit_t reserved7[0x00040];
-/* -------------- */
- pseudo_bit_t eqc_base_addr_h[0x00020];/* EQC Base Address [63:32]
- Address may be set to 0xFFFFFFFF if EQs are not supported.
- Table must be aligned to entry size. */
-/* -------------- */
- pseudo_bit_t log_num_eq[0x00004]; /* Log base 2 of number of supported EQs.
- Must be 6 or less in InfiniHost-III-EX. */
- pseudo_bit_t reserved8[0x00002];
- pseudo_bit_t eqc_base_addr_l[0x0001a];/* EQC Base Address [31:6]
- Address may be set to 0xFFFFFFFF if EQs are not supported.
- Table must be aligned to entry size. */
-/* -------------- */
- pseudo_bit_t reserved9[0x00040];
-/* -------------- */
- pseudo_bit_t rdb_base_addr_h[0x00020];/* Base address of table that holds remote read and remote atomic requests [63:32].
- Address may be set to 0xFFFFFFFF if remote RDMA reads are not supported.
- Please refer to QP and EE chapter for further explanation on RDB allocation. */
-/* -------------- */
- pseudo_bit_t rdb_base_addr_l[0x00020];/* Base address of table that holds remote read and remote atomic requests [31:0].
- Table must be aligned to RDB entry size (32 bytes).
- Address may be set to zero if remote RDMA reads are not supported.
- Please refer to QP and EE chapter for further explanation on RDB allocation. */
-/* -------------- */
- pseudo_bit_t reserved10[0x00040];
-/* -------------- */
-};
-
-/* Header_Log_Register */
-
-struct arbelprm_header_log_register_st { /* Little Endian */
- pseudo_bit_t place_holder[0x00020];
-/* -------------- */
- pseudo_bit_t reserved0[0x00060];
-/* -------------- */
-};
-
-/* Performance Monitors */
-
-struct arbelprm_performance_monitors_st { /* Little Endian */
- pseudo_bit_t e0[0x00001]; /* Enables counting of respective performance counter */
- pseudo_bit_t e1[0x00001]; /* Enables counting of respective performance counter */
- pseudo_bit_t e2[0x00001]; /* Enables counting of respective performance counter */
- pseudo_bit_t reserved0[0x00001];
- pseudo_bit_t r0[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
- pseudo_bit_t r1[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
- pseudo_bit_t r2[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
- pseudo_bit_t reserved1[0x00001];
- pseudo_bit_t i0[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
- pseudo_bit_t i1[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
- pseudo_bit_t i2[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
- pseudo_bit_t reserved2[0x00001];
- pseudo_bit_t f0[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
- pseudo_bit_t f1[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
- pseudo_bit_t f2[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
- pseudo_bit_t reserved3[0x00001];
- pseudo_bit_t ev_cnt1[0x00005]; /* Specifies event to be counted by Event_counter1 See XXX for events' definition. */
- pseudo_bit_t reserved4[0x00003];
- pseudo_bit_t ev_cnt2[0x00005]; /* Specifies event to be counted by Event_counter2 See XXX for events' definition. */
- pseudo_bit_t reserved5[0x00003];
-/* -------------- */
- pseudo_bit_t clock_counter[0x00020];
-/* -------------- */
- pseudo_bit_t event_counter1[0x00020];
-/* -------------- */
- pseudo_bit_t event_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */
-/* -------------- */
-};
-
-/* Receive segment format */
-
-struct arbelprm_wqe_segment_ctrl_recv_st { /* Little Endian */
- struct arbelprm_recv_wqe_segment_next_st wqe_segment_next;
-/* -------------- */
- pseudo_bit_t reserved0[0x00002];
- pseudo_bit_t reserved1[0x00001];
- pseudo_bit_t reserved2[0x00001];
- pseudo_bit_t reserved3[0x0001c];
-/* -------------- */
- pseudo_bit_t reserved4[0x00020];
-/* -------------- */
-};
-
-/* MLX WQE segment format */
-
-struct arbelprm_wqe_segment_ctrl_mlx_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00002];
- pseudo_bit_t e[0x00001]; /* WQE event */
- pseudo_bit_t c[0x00001]; /* Create CQE (for "requested signalling" QP) */
- pseudo_bit_t icrc[0x00002]; /* icrc field detemines what to do with the last dword of the packet: 0 - Calculate ICRC and put it instead of last dword. Last dword must be 0x0. 1,2 - reserved. 3 - Leave last dword as is. Last dword must not be 0x0. */
- pseudo_bit_t reserved1[0x00002];
- pseudo_bit_t sl[0x00004];
- pseudo_bit_t max_statrate[0x00004];
- pseudo_bit_t slr[0x00001]; /* 0= take slid from port. 1= take slid from given headers */
- pseudo_bit_t v15[0x00001]; /* Send packet over VL15 */
- pseudo_bit_t reserved2[0x0000e];
-/* -------------- */
- pseudo_bit_t vcrc[0x00010]; /* Packet's VCRC (if not 0 - otherwise computed by HW) */
- pseudo_bit_t rlid[0x00010]; /* Destination LID (must match given headers) */
-/* -------------- */
- pseudo_bit_t reserved3[0x00040];
-/* -------------- */
-};
-
-/* Send WQE segment format */
-
-struct arbelprm_send_wqe_segment_st { /* Little Endian */
- struct arbelprm_wqe_segment_next_st wqe_segment_next;/* Send wqe segment next */
-/* -------------- */
- struct arbelprm_wqe_segment_ctrl_send_st wqe_segment_ctrl_send;/* Send wqe segment ctrl */
-/* -------------- */
- struct arbelprm_wqe_segment_rd_st wqe_segment_rd;/* Send wqe segment rd */
-/* -------------- */
- struct arbelprm_wqe_segment_ud_st wqe_segment_ud;/* Send wqe segment ud */
-/* -------------- */
- struct arbelprm_wqe_segment_bind_st wqe_segment_bind;/* Send wqe segment bind */
-/* -------------- */
- pseudo_bit_t reserved0[0x00180];
-/* -------------- */
- struct arbelprm_wqe_segment_remote_address_st wqe_segment_remote_address;/* Send wqe segment remote address */
-/* -------------- */
- struct arbelprm_wqe_segment_atomic_st wqe_segment_atomic;/* Send wqe segment atomic */
-/* -------------- */
- struct arbelprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */
-/* -------------- */
- struct arbelprm_local_invalidate_segment_st local_invalidate_segment;/* local invalidate segment */
-/* -------------- */
- struct arbelprm_wqe_segment_data_ptr_st wqe_segment_data_ptr;/* Send wqe segment data ptr */
-/* -------------- */
- struct arbelprm_wqe_segment_data_inline_st wqe_segment_data_inline;/* Send wqe segment data inline */
-/* -------------- */
- pseudo_bit_t reserved1[0x00200];
-/* -------------- */
-};
-
-/* QP and EE Context Entry */
-
-struct arbelprm_queue_pair_ee_context_entry_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00008];
- pseudo_bit_t de[0x00001]; /* Send/Receive Descriptor Event enable - if set, events can be generated upon descriptors' completion on send/receive queue (controlled by E bit in WQE). Invalid in EE context */
- pseudo_bit_t reserved1[0x00002];
- pseudo_bit_t pm_state[0x00002]; /* Path migration state (Migrated, Armed or Rearm)
- 11-Migrated
- 00-Armed
- 01-Rearm
- 10-Reserved
- Should be set to 11 for UD QPs and for QPs which do not support APM */
- pseudo_bit_t reserved2[0x00003];
- pseudo_bit_t st[0x00003]; /* Service type (invalid in EE context):
- 000-Reliable Connection
- 001-Unreliable Connection
- 010-Reliable Datagram
- 011-Unreliable Datagram
- 111-MLX transport (raw bits injection). Used for management QPs and RAW */
- pseudo_bit_t reserved3[0x00009];
- pseudo_bit_t state[0x00004]; /* QP/EE state:
- 0 - RST
- 1 - INIT
- 2 - RTR
- 3 - RTS
- 4 - SQEr
- 5 - SQD (Send Queue Drained)
- 6 - ERR
- 7 - Send Queue Draining
- 8 - Reserved
- 9 - Suspended
- A- F - Reserved
- (Valid for QUERY_QPEE and ERR2RST_QPEE commands only) */
-/* -------------- */
- pseudo_bit_t reserved4[0x00020];
-/* -------------- */
- pseudo_bit_t sched_queue[0x00004]; /* Schedule queue to be used for WQE scheduling to execution. Determines QOS for this QP. */
- pseudo_bit_t rlky[0x00001]; /* When set this QP can use the Reserved L_Key */
- pseudo_bit_t reserved5[0x00003];
- pseudo_bit_t log_sq_stride[0x00003];/* Stride on the send queue. WQ entry is 16*(2^log_SQ_stride) bytes.
- Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */
- pseudo_bit_t log_sq_size[0x00004]; /* Log2 of the Number of WQEs in the Send Queue. */
- pseudo_bit_t reserved6[0x00001];
- pseudo_bit_t log_rq_stride[0x00003];/* Stride on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes.
- Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */
- pseudo_bit_t log_rq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. */
- pseudo_bit_t reserved7[0x00001];
- pseudo_bit_t msg_max[0x00005]; /* Max message size allowed on the QP. Maximum message size is 2^msg_Max.
- Must be equal to MTU for UD and MLX QPs. */
- pseudo_bit_t mtu[0x00003]; /* MTU of the QP (Must be the same for both paths: primary and alternative):
- 0x1 - 256 bytes
- 0x2 - 512
- 0x3 - 1024
- 0x4 - 2048
- other - reserved
-
- Should be configured to 0x4 for UD and MLX QPs. */
-/* -------------- */
- pseudo_bit_t usr_page[0x00018]; /* QP (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */
- pseudo_bit_t reserved8[0x00008];
-/* -------------- */
- pseudo_bit_t local_qpn_een[0x00018];/* Local QP/EE number Lower bits determine position of this record in QPC table, and - thus - constrained
- This field is valid for QUERY and ERR2RST commands only. */
- pseudo_bit_t reserved9[0x00008];
-/* -------------- */
- pseudo_bit_t remote_qpn_een[0x00018];/* Remote QP/EE number */
- pseudo_bit_t reserved10[0x00008];
-/* -------------- */
- pseudo_bit_t reserved11[0x00040];
-/* -------------- */
- struct arbelprm_address_path_st primary_address_path;/* Primary address path for the QP/EE */
-/* -------------- */
- struct arbelprm_address_path_st alternative_address_path;/* Alternate address path for the QP/EE */
-/* -------------- */
- pseudo_bit_t rdd[0x00018]; /* Reliable Datagram Domain */
- pseudo_bit_t reserved12[0x00008];
-/* -------------- */
- pseudo_bit_t pd[0x00018]; /* QP protection domain. Not valid (reserved) in EE context. */
- pseudo_bit_t reserved13[0x00008];
-/* -------------- */
- pseudo_bit_t wqe_base_adr_h[0x00020];/* Bits 63:32 of WQE address for both SQ and RQ.
- Reserved for EE context. */
-/* -------------- */
- pseudo_bit_t wqe_lkey[0x00020]; /* memory key (L-Key) to be used to access WQEs. Not valid (reserved) in EE context. */
-/* -------------- */
- pseudo_bit_t reserved14[0x00003];
- pseudo_bit_t ssc[0x00001]; /* Send Signaled Completion
- 1 - all send WQEs generate CQEs.
- 0 - only send WQEs with C bit set generate completion.
- Not valid (reserved) in EE context. */
- pseudo_bit_t sic[0x00001]; /* If set - Ignore end to end credits on send queue. Not valid (reserved) in EE context. */
- pseudo_bit_t cur_retry_cnt[0x00003];/* Current transport retry counter (QUERY_QPEE only).
- The current transport retry counter can vary from retry_count down to 1, where 1 means that the last retry attempt is currently executing. */
- pseudo_bit_t cur_rnr_retry[0x00003];/* Current RNR retry counter (QUERY_QPEE only).
- The current RNR retry counter can vary from rnr_retry to 1, where 1 means that the last retry attempt is currently executing. */
- pseudo_bit_t fre[0x00001]; /* Fast Registration Work Request Enabled. (Reserved for EE) */
- pseudo_bit_t reserved15[0x00001];
- pseudo_bit_t sae[0x00001]; /* If set - Atomic operations enabled on send queue. Not valid (reserved) in EE context. */
- pseudo_bit_t swe[0x00001]; /* If set - RDMA - write enabled on send queue. Not valid (reserved) in EE context. */
- pseudo_bit_t sre[0x00001]; /* If set - RDMA - read enabled on send queue. Not valid (reserved) in EE context. */
- pseudo_bit_t retry_count[0x00003]; /* Transport timeout Retry count */
- pseudo_bit_t reserved16[0x00002];
- pseudo_bit_t sra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */
- pseudo_bit_t flight_lim[0x00004]; /* Number of outstanding (in-flight) messages on the wire allowed for this send queue.
- Number of outstanding messages is 2^Flight_Lim.
- Use 0xF for unlimited number of outstanding messages. */
- pseudo_bit_t ack_req_freq[0x00004]; /* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */
-/* -------------- */
- pseudo_bit_t reserved17[0x00020];
-/* -------------- */
- pseudo_bit_t next_send_psn[0x00018];/* Next PSN to be sent */
- pseudo_bit_t reserved18[0x00008];
-/* -------------- */
- pseudo_bit_t cqn_snd[0x00018]; /* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */
- pseudo_bit_t reserved19[0x00008];
-/* -------------- */
- pseudo_bit_t reserved20[0x00006];
- pseudo_bit_t snd_wqe_base_adr_l[0x0001a];/* While opening (creating) the WQ, this field should contain the address of first descriptor to be posted. Not valid (reserved) in EE context. */
-/* -------------- */
- pseudo_bit_t snd_db_record_index[0x00020];/* Index in the UAR Context Table Entry.
- HW uses this index as an offset from the UAR Context Table Entry in order to read this SQ doorbell record.
- The entry is obtained via the usr_page field.
- Not valid for EE. */
-/* -------------- */
- pseudo_bit_t last_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */
- pseudo_bit_t reserved21[0x00008];
-/* -------------- */
- pseudo_bit_t ssn[0x00018]; /* Requester Send Sequence Number (QUERY_QPEE only) */
- pseudo_bit_t reserved22[0x00008];
-/* -------------- */
- pseudo_bit_t reserved23[0x00003];
- pseudo_bit_t rsc[0x00001]; /* 1 - all receive WQEs generate CQEs.
- 0 - only receive WQEs with C bit set generate completion.
- Not valid (reserved) in EE context.
- */
- pseudo_bit_t ric[0x00001]; /* Invalid Credits.
- 1 - place "Invalid Credits" to ACKs sent from this queue.
- 0 - ACKs report the actual number of end to end credits on the connection.
- Not valid (reserved) in EE context.
- Must be set to 1 on QPs which are attached to SRQ. */
- pseudo_bit_t reserved24[0x00008];
- pseudo_bit_t rae[0x00001]; /* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */
- pseudo_bit_t rwe[0x00001]; /* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */
- pseudo_bit_t rre[0x00001]; /* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */
- pseudo_bit_t reserved25[0x00005];
- pseudo_bit_t rra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max.
- Must be 0 for EE context. */
- pseudo_bit_t reserved26[0x00008];
-/* -------------- */
- pseudo_bit_t next_rcv_psn[0x00018]; /* Next (expected) PSN on receive */
- pseudo_bit_t min_rnr_nak[0x00005]; /* Minimum RNR NAK timer value (TTTTT field encoding according to the IB spec Vol1 9.7.5.2.8).
- Not valid (reserved) in EE context. */
- pseudo_bit_t reserved27[0x00003];
-/* -------------- */
- pseudo_bit_t reserved28[0x00005];
- pseudo_bit_t ra_buff_indx[0x0001b]; /* Index to outstanding read/atomic buffer.
- This field constructs the address to the RDB for maintaining the incoming RDMA read and atomic requests. */
-/* -------------- */
- pseudo_bit_t cqn_rcv[0x00018]; /* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */
- pseudo_bit_t reserved29[0x00008];
-/* -------------- */
- pseudo_bit_t reserved30[0x00006];
- pseudo_bit_t rcv_wqe_base_adr_l[0x0001a];/* While opening (creating) the WQ, this field should contain the address of first descriptor to be posted. Not valid (reserved) in EE context. */
-/* -------------- */
- pseudo_bit_t rcv_db_record_index[0x00020];/* Index in the UAR Context Table Entry containing the doorbell record for the receive queue.
- HW uses this index as an offset from the UAR Context Table Entry in order to read this RQ doorbell record.
- The entry is obtained via the usr_page field.
- Not valid for EE. */
-/* -------------- */
- pseudo_bit_t q_key[0x00020]; /* Q_Key to be validated against received datagrams.
- On send datagrams, if Q_Key[31] specified in the WQE is set, then this Q_Key will be transmitted in the outgoing message.
- Not valid (reserved) in EE context. */
-/* -------------- */
- pseudo_bit_t srqn[0x00018]; /* SRQN - Shared Receive Queue Number - specifies the SRQ number from which the QP dequeues receive descriptors.
- SRQN is valid only if SRQ bit is set. Not valid (reserved) in EE context. */
- pseudo_bit_t srq[0x00001]; /* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */
- pseudo_bit_t reserved31[0x00007];
-/* -------------- */
- pseudo_bit_t rmsn[0x00018]; /* Responder current message sequence number (QUERY_QPEE only) */
- pseudo_bit_t reserved32[0x00008];
-/* -------------- */
- pseudo_bit_t sq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ.
- Must be 0x0 in SQ initialization.
- (QUERY_QPEE only). */
- pseudo_bit_t rq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the RQ.
- Must be 0x0 in RQ initialization.
- (QUERY_QPEE only). */
-/* -------------- */
- pseudo_bit_t reserved33[0x00040];
-/* -------------- */
-};
-
-/* Clear Interrupt [63:0] */
-
-struct arbelprm_clr_int_st { /* Little Endian */
- pseudo_bit_t clr_int_h[0x00020]; /* Clear Interrupt [63:32]
- Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot.
- This register is write-only. Reading from this register will cause undefined result
- */
-/* -------------- */
- pseudo_bit_t clr_int_l[0x00020]; /* Clear Interrupt [31:0]
- Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot.
- This register is write-only. Reading from this register will cause undefined result */
-/* -------------- */
-};
-
-/* EQ_Arm_DB_Region */
-
-struct arbelprm_eq_arm_db_region_st { /* Little Endian */
- pseudo_bit_t eq_x_arm_h[0x00020]; /* EQ[63:32] X state.
- This register is used to Arm EQs when setting the appropriate bits. */
-/* -------------- */
- pseudo_bit_t eq_x_arm_l[0x00020]; /* EQ[31:0] X state.
- This register is used to Arm EQs when setting the appropriate bits. */
-/* -------------- */
-};
-
-/* EQ Set CI DBs Table */
-
-struct arbelprm_eq_set_ci_table_st { /* Little Endian */
- pseudo_bit_t eq0_set_ci[0x00020]; /* EQ0_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved0[0x00020];
-/* -------------- */
- pseudo_bit_t eq1_set_ci[0x00020]; /* EQ1_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved1[0x00020];
-/* -------------- */
- pseudo_bit_t eq2_set_ci[0x00020]; /* EQ2_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved2[0x00020];
-/* -------------- */
- pseudo_bit_t eq3_set_ci[0x00020]; /* EQ3_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved3[0x00020];
-/* -------------- */
- pseudo_bit_t eq4_set_ci[0x00020]; /* EQ4_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved4[0x00020];
-/* -------------- */
- pseudo_bit_t eq5_set_ci[0x00020]; /* EQ5_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved5[0x00020];
-/* -------------- */
- pseudo_bit_t eq6_set_ci[0x00020]; /* EQ6_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved6[0x00020];
-/* -------------- */
- pseudo_bit_t eq7_set_ci[0x00020]; /* EQ7_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved7[0x00020];
-/* -------------- */
- pseudo_bit_t eq8_set_ci[0x00020]; /* EQ8_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved8[0x00020];
-/* -------------- */
- pseudo_bit_t eq9_set_ci[0x00020]; /* EQ9_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved9[0x00020];
-/* -------------- */
- pseudo_bit_t eq10_set_ci[0x00020]; /* EQ10_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved10[0x00020];
-/* -------------- */
- pseudo_bit_t eq11_set_ci[0x00020]; /* EQ11_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved11[0x00020];
-/* -------------- */
- pseudo_bit_t eq12_set_ci[0x00020]; /* EQ12_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved12[0x00020];
-/* -------------- */
- pseudo_bit_t eq13_set_ci[0x00020]; /* EQ13_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved13[0x00020];
-/* -------------- */
- pseudo_bit_t eq14_set_ci[0x00020]; /* EQ14_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved14[0x00020];
-/* -------------- */
- pseudo_bit_t eq15_set_ci[0x00020]; /* EQ15_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved15[0x00020];
-/* -------------- */
- pseudo_bit_t eq16_set_ci[0x00020]; /* EQ16_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved16[0x00020];
-/* -------------- */
- pseudo_bit_t eq17_set_ci[0x00020]; /* EQ17_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved17[0x00020];
-/* -------------- */
- pseudo_bit_t eq18_set_ci[0x00020]; /* EQ18_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved18[0x00020];
-/* -------------- */
- pseudo_bit_t eq19_set_ci[0x00020]; /* EQ19_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved19[0x00020];
-/* -------------- */
- pseudo_bit_t eq20_set_ci[0x00020]; /* EQ20_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved20[0x00020];
-/* -------------- */
- pseudo_bit_t eq21_set_ci[0x00020]; /* EQ21_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved21[0x00020];
-/* -------------- */
- pseudo_bit_t eq22_set_ci[0x00020]; /* EQ22_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved22[0x00020];
-/* -------------- */
- pseudo_bit_t eq23_set_ci[0x00020]; /* EQ23_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved23[0x00020];
-/* -------------- */
- pseudo_bit_t eq24_set_ci[0x00020]; /* EQ24_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved24[0x00020];
-/* -------------- */
- pseudo_bit_t eq25_set_ci[0x00020]; /* EQ25_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved25[0x00020];
-/* -------------- */
- pseudo_bit_t eq26_set_ci[0x00020]; /* EQ26_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved26[0x00020];
-/* -------------- */
- pseudo_bit_t eq27_set_ci[0x00020]; /* EQ27_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved27[0x00020];
-/* -------------- */
- pseudo_bit_t eq28_set_ci[0x00020]; /* EQ28_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved28[0x00020];
-/* -------------- */
- pseudo_bit_t eq29_set_ci[0x00020]; /* EQ29_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved29[0x00020];
-/* -------------- */
- pseudo_bit_t eq30_set_ci[0x00020]; /* EQ30_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved30[0x00020];
-/* -------------- */
- pseudo_bit_t eq31_set_ci[0x00020]; /* EQ31_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved31[0x00020];
-/* -------------- */
- pseudo_bit_t eq32_set_ci[0x00020]; /* EQ32_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved32[0x00020];
-/* -------------- */
- pseudo_bit_t eq33_set_ci[0x00020]; /* EQ33_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved33[0x00020];
-/* -------------- */
- pseudo_bit_t eq34_set_ci[0x00020]; /* EQ34_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved34[0x00020];
-/* -------------- */
- pseudo_bit_t eq35_set_ci[0x00020]; /* EQ35_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved35[0x00020];
-/* -------------- */
- pseudo_bit_t eq36_set_ci[0x00020]; /* EQ36_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved36[0x00020];
-/* -------------- */
- pseudo_bit_t eq37_set_ci[0x00020]; /* EQ37_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved37[0x00020];
-/* -------------- */
- pseudo_bit_t eq38_set_ci[0x00020]; /* EQ38_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved38[0x00020];
-/* -------------- */
- pseudo_bit_t eq39_set_ci[0x00020]; /* EQ39_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved39[0x00020];
-/* -------------- */
- pseudo_bit_t eq40_set_ci[0x00020]; /* EQ40_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved40[0x00020];
-/* -------------- */
- pseudo_bit_t eq41_set_ci[0x00020]; /* EQ41_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved41[0x00020];
-/* -------------- */
- pseudo_bit_t eq42_set_ci[0x00020]; /* EQ42_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved42[0x00020];
-/* -------------- */
- pseudo_bit_t eq43_set_ci[0x00020]; /* EQ43_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved43[0x00020];
-/* -------------- */
- pseudo_bit_t eq44_set_ci[0x00020]; /* EQ44_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved44[0x00020];
-/* -------------- */
- pseudo_bit_t eq45_set_ci[0x00020]; /* EQ45_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved45[0x00020];
-/* -------------- */
- pseudo_bit_t eq46_set_ci[0x00020]; /* EQ46_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved46[0x00020];
-/* -------------- */
- pseudo_bit_t eq47_set_ci[0x00020]; /* EQ47_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved47[0x00020];
-/* -------------- */
- pseudo_bit_t eq48_set_ci[0x00020]; /* EQ48_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved48[0x00020];
-/* -------------- */
- pseudo_bit_t eq49_set_ci[0x00020]; /* EQ49_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved49[0x00020];
-/* -------------- */
- pseudo_bit_t eq50_set_ci[0x00020]; /* EQ50_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved50[0x00020];
-/* -------------- */
- pseudo_bit_t eq51_set_ci[0x00020]; /* EQ51_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved51[0x00020];
-/* -------------- */
- pseudo_bit_t eq52_set_ci[0x00020]; /* EQ52_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved52[0x00020];
-/* -------------- */
- pseudo_bit_t eq53_set_ci[0x00020]; /* EQ53_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved53[0x00020];
-/* -------------- */
- pseudo_bit_t eq54_set_ci[0x00020]; /* EQ54_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved54[0x00020];
-/* -------------- */
- pseudo_bit_t eq55_set_ci[0x00020]; /* EQ55_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved55[0x00020];
-/* -------------- */
- pseudo_bit_t eq56_set_ci[0x00020]; /* EQ56_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved56[0x00020];
-/* -------------- */
- pseudo_bit_t eq57_set_ci[0x00020]; /* EQ57_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved57[0x00020];
-/* -------------- */
- pseudo_bit_t eq58_set_ci[0x00020]; /* EQ58_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved58[0x00020];
-/* -------------- */
- pseudo_bit_t eq59_set_ci[0x00020]; /* EQ59_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved59[0x00020];
-/* -------------- */
- pseudo_bit_t eq60_set_ci[0x00020]; /* EQ60_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved60[0x00020];
-/* -------------- */
- pseudo_bit_t eq61_set_ci[0x00020]; /* EQ61_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved61[0x00020];
-/* -------------- */
- pseudo_bit_t eq62_set_ci[0x00020]; /* EQ62_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved62[0x00020];
-/* -------------- */
- pseudo_bit_t eq63_set_ci[0x00020]; /* EQ63_Set_CI */
-/* -------------- */
- pseudo_bit_t reserved63[0x00020];
-/* -------------- */
-};
-
-/* InfiniHost-III-EX Configuration Registers */
-
-struct arbelprm_configuration_registers_st { /* Little Endian */
- pseudo_bit_t reserved0[0x403400];
-/* -------------- */
- struct arbelprm_hca_command_register_st hca_command_interface_register;/* HCA Command Register */
-/* -------------- */
- pseudo_bit_t reserved1[0x3fcb20];
-/* -------------- */
-};
-
-/* QP_DB_Record */
-
-struct arbelprm_qp_db_record_st { /* Little Endian */
- pseudo_bit_t counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation. Should be initialized to zero. */
- pseudo_bit_t reserved0[0x00010];
-/* -------------- */
- pseudo_bit_t reserved1[0x00005];
- pseudo_bit_t res[0x00003]; /* 0x3 for SQ
- 0x4 for RQ
- 0x5 for SRQ */
- pseudo_bit_t qp_number[0x00018]; /* QP number */
-/* -------------- */
-};
-
-/* CQ_ARM_DB_Record */
-
-struct arbelprm_cq_arm_db_record_st { /* Little Endian */
- pseudo_bit_t counter[0x00020]; /* CQ counter for the arming request */
-/* -------------- */
- pseudo_bit_t cmd[0x00003]; /* 0x0 - No command
- 0x1 - Request notification for next Solicited completion event. Counter filed specifies the current CQ Consumer Counter.
- 0x2 - Request notification for next Solicited or Unsolicited completion event. Counter filed specifies the current CQ Consumer counter.
- 0x3 - Request notification for multiple completions (Arm-N). Counter filed specifies the value of the CQ Index that when reached by HW (i.e. HW generates a CQE into this Index) Event will be generated
- Other - Reserved */
- pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - See Table 35, "CQ Doorbell Layout" for definition of this filed */
- pseudo_bit_t res[0x00003]; /* Must be 0x2 */
- pseudo_bit_t cq_number[0x00018]; /* CQ number */
-/* -------------- */
-};
-
-/* CQ_CI_DB_Record */
-
-struct arbelprm_cq_ci_db_record_st { /* Little Endian */
- pseudo_bit_t counter[0x00020]; /* CQ counter */
-/* -------------- */
- pseudo_bit_t reserved0[0x00005];
- pseudo_bit_t res[0x00003]; /* Must be 0x1 */
- pseudo_bit_t cq_number[0x00018]; /* CQ number */
-/* -------------- */
-};
-
-/* Virtual_Physical_Mapping */
-
-struct arbelprm_virtual_physical_mapping_st { /* Little Endian */
- pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32]. Valid only for MAP_ICM command. */
-/* -------------- */
- pseudo_bit_t reserved0[0x0000c];
- pseudo_bit_t va_l[0x00014]; /* Virtual Address[31:12]. Valid only for MAP_ICM command. */
-/* -------------- */
- pseudo_bit_t pa_h[0x00020]; /* Physical Address[63:32] */
-/* -------------- */
- pseudo_bit_t log2size[0x00006]; /* Log2 of the size in 4KB pages of the physical and virtual contiguous memory that starts at PA_L/H and VA_L/H */
- pseudo_bit_t reserved1[0x00006];
- pseudo_bit_t pa_l[0x00014]; /* Physical Address[31:12] */
-/* -------------- */
-};
-
-/* MOD_STAT_CFG */
-
-struct arbelprm_mod_stat_cfg_st { /* Little Endian */
- pseudo_bit_t log_max_srqs[0x00005]; /* Log (base 2) of the number of SRQs to allocate (0 if no SRQs are required), valid only if srq bit is set. */
- pseudo_bit_t reserved0[0x00001];
- pseudo_bit_t srq[0x00001]; /* When set SRQs are supported */
- pseudo_bit_t srq_m[0x00001]; /* Modify SRQ parameters */
- pseudo_bit_t reserved1[0x00018];
-/* -------------- */
- pseudo_bit_t reserved2[0x007e0];
-/* -------------- */
-};
-
-/* SRQ Context */
-
-struct arbelprm_srq_context_st { /* Little Endian */
- pseudo_bit_t srqn[0x00018]; /* SRQ number */
- pseudo_bit_t log_srq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue.
- Maximum value is 0x10, i.e. 16M WQEs. */
- pseudo_bit_t state[0x00004]; /* SRQ State:
- 1111 - SW Ownership
- 0000 - HW Ownership
- 0001 - Error
- Valid only on QUERY_SRQ and HW2SW_SRQ commands. */
-/* -------------- */
- pseudo_bit_t l_key[0x00020]; /* memory key (L-Key) to be used to access WQEs. */
-/* -------------- */
- pseudo_bit_t srq_db_record_index[0x00020];/* Index in the UAR Context Table Entry containing the doorbell record for the receive queue.
- HW uses this index as an offset from the UAR Context Table Entry in order to read this SRQ doorbell record.
- The entry is obtained via the usr_page field. */
-/* -------------- */
- pseudo_bit_t usr_page[0x00018]; /* Index (offset) of user page allocated for this SRQ (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */
- pseudo_bit_t reserved0[0x00005];
- pseudo_bit_t log_rq_stride[0x00003];/* Stride (max WQE size) on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. */
-/* -------------- */
- pseudo_bit_t wqe_addr_h[0x00020]; /* Bits 63:32 of WQE address (WQE base address) */
-/* -------------- */
- pseudo_bit_t reserved1[0x00006];
- pseudo_bit_t srq_wqe_base_adr_l[0x0001a];/* While opening (creating) the SRQ, this field should contain the address of first descriptor to be posted. */
-/* -------------- */
- pseudo_bit_t pd[0x00018]; /* SRQ protection domain. */
- pseudo_bit_t reserved2[0x00008];
-/* -------------- */
- pseudo_bit_t wqe_cnt[0x00010]; /* WQE count on the SRQ.
- Valid only on QUERY_SRQ and HW2SW_SRQ commands. */
- pseudo_bit_t lwm[0x00010]; /* Limit Water Mark - if the LWM is not zero, and the wqe_cnt drops below LWM when a WQE is dequeued from the SRQ, then a SRQ limit event is fired and the LWM is set to zero. */
-/* -------------- */
- pseudo_bit_t srq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ.
- Must be 0x0 in SRQ initialization.
- (QUERY_SRQ only). */
- pseudo_bit_t reserved3[0x00010];
-/* -------------- */
- pseudo_bit_t reserved4[0x00060];
-/* -------------- */
-};
-
-/* PBL */
-
-struct arbelprm_pbl_st { /* Little Endian */
- pseudo_bit_t mtt_0_h[0x00020]; /* First MTT[63:32] */
-/* -------------- */
- pseudo_bit_t mtt_0_l[0x00020]; /* First MTT[31:0] */
-/* -------------- */
- pseudo_bit_t mtt_1_h[0x00020]; /* Second MTT[63:32] */
-/* -------------- */
- pseudo_bit_t mtt_1_l[0x00020]; /* Second MTT[31:0] */
-/* -------------- */
- pseudo_bit_t mtt_2_h[0x00020]; /* Third MTT[63:32] */
-/* -------------- */
- pseudo_bit_t mtt_2_l[0x00020]; /* Third MTT[31:0] */
-/* -------------- */
- pseudo_bit_t mtt_3_h[0x00020]; /* Fourth MTT[63:32] */
-/* -------------- */
- pseudo_bit_t mtt_3_l[0x00020]; /* Fourth MTT[31:0] */
-/* -------------- */
-};
-
-/* Performance Counters */
-
-struct arbelprm_performance_counters_st { /* Little Endian */
- pseudo_bit_t sqpc_access_cnt[0x00020];/* SQPC cache access count */
-/* -------------- */
- pseudo_bit_t sqpc_miss_cnt[0x00020];/* SQPC cache miss count */
-/* -------------- */
- pseudo_bit_t reserved0[0x00040];
-/* -------------- */
- pseudo_bit_t rqpc_access_cnt[0x00020];/* RQPC cache access count */
-/* -------------- */
- pseudo_bit_t rqpc_miss_cnt[0x00020];/* RQPC cache miss count */
-/* -------------- */
- pseudo_bit_t reserved1[0x00040];
-/* -------------- */
- pseudo_bit_t cqc_access_cnt[0x00020];/* CQC cache access count */
-/* -------------- */
- pseudo_bit_t cqc_miss_cnt[0x00020]; /* CQC cache miss count */
-/* -------------- */
- pseudo_bit_t reserved2[0x00040];
-/* -------------- */
- pseudo_bit_t tpt_access_cnt[0x00020];/* TPT cache access count */
-/* -------------- */
- pseudo_bit_t mpt_miss_cnt[0x00020]; /* MPT cache miss count */
-/* -------------- */
- pseudo_bit_t mtt_miss_cnt[0x00020]; /* MTT cache miss count */
-/* -------------- */
- pseudo_bit_t reserved3[0x00620];
-/* -------------- */
-};
-
-/* Transport and CI Error Counters */
-
-struct arbelprm_transport_and_ci_error_counters_st { /* Little Endian */
- pseudo_bit_t rq_num_lle[0x00020]; /* Responder - number of local length errors */
-/* -------------- */
- pseudo_bit_t sq_num_lle[0x00020]; /* Requester - number of local length errors */
-/* -------------- */
- pseudo_bit_t rq_num_lqpoe[0x00020]; /* Responder - number local QP operation error */
-/* -------------- */
- pseudo_bit_t sq_num_lqpoe[0x00020]; /* Requester - number local QP operation error */
-/* -------------- */
- pseudo_bit_t rq_num_leeoe[0x00020]; /* Responder - number local EE operation error */
-/* -------------- */
- pseudo_bit_t sq_num_leeoe[0x00020]; /* Requester - number local EE operation error */
-/* -------------- */
- pseudo_bit_t rq_num_lpe[0x00020]; /* Responder - number of local protection errors */
-/* -------------- */
- pseudo_bit_t sq_num_lpe[0x00020]; /* Requester - number of local protection errors */
-/* -------------- */
- pseudo_bit_t rq_num_wrfe[0x00020]; /* Responder - number of CQEs with error.
- Incremented each time a CQE with error is generated */
-/* -------------- */
- pseudo_bit_t sq_num_wrfe[0x00020]; /* Requester - number of CQEs with error.
- Incremented each time a CQE with error is generated */
-/* -------------- */
- pseudo_bit_t reserved0[0x00020];
-/* -------------- */
- pseudo_bit_t sq_num_mwbe[0x00020]; /* Requester - number of memory window bind errors */
-/* -------------- */
- pseudo_bit_t reserved1[0x00020];
-/* -------------- */
- pseudo_bit_t sq_num_bre[0x00020]; /* Requester - number of bad response errors */
-/* -------------- */
- pseudo_bit_t rq_num_lae[0x00020]; /* Responder - number of local access errors */
-/* -------------- */
- pseudo_bit_t reserved2[0x00040];
-/* -------------- */
- pseudo_bit_t sq_num_rire[0x00020]; /* Requester - number of remote invalid request errors
- NAK-Invalid Request on:
- 1. Unsupported OpCode: Responder detected an unsupported OpCode.
- 2. Unexpected OpCode: Responder detected an error in the sequence of OpCodes, such
- as a missing "Last" packet.
- Note: there is no PSN error, thus this does not indicate a dropped packet. */
-/* -------------- */
- pseudo_bit_t rq_num_rire[0x00020]; /* Responder - number of remote invalid request errors.
- NAK may or may not be sent.
- 1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD only):
- Inbound request OpCode was either reserved, or was for a function not supported by this
- QP. (E.g. RDMA or ATOMIC on QP not set up for this).
- 2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic opera-tion.
- 3. Too many RDMA READ or ATOMIC Requests: There were more requests received
- and not ACKed than allowed for the connection.
- 4. Out of Sequence OpCode, current packet is "First" or "Only": The Responder
- detected an error in the sequence of OpCodes; a missing "Last" packet
- 5. Out of Sequence OpCode, current packet is not "First" or "Only": The Responder
- detected an error in the sequence of OpCodes; a missing "First" packet
- 6. Local Length Error: Inbound "Send" request message exceeded the responder.s avail-able
- buffer space.
- 7. Length error: RDMA WRITE request message contained too much or too little pay-load
- data compared to the DMA length advertised in the first or only packet.
- 8. Length error: Payload length was not consistent with the opcode:
- a: 0 byte <= "only" <= PMTU bytes
- b: ("first" or "middle") == PMTU bytes
- c: 1byte <= "last" <= PMTU bytes
- 9. Length error: Inbound message exceeded the size supported by the CA port. */
-/* -------------- */
- pseudo_bit_t sq_num_rae[0x00020]; /* Requester - number of remote access errors.
- NAK-Remote Access Error on:
- R_Key Violation: Responder detected an invalid R_Key while executing an RDMA
- Request. */
-/* -------------- */
- pseudo_bit_t rq_num_rae[0x00020]; /* Responder - number of remote access errors.
- R_Key Violation Responder detected an R_Key violation while executing an RDMA
- request.
- NAK may or may not be sent. */
-/* -------------- */
- pseudo_bit_t sq_num_roe[0x00020]; /* Requester - number of remote operation errors.
- NAK-Remote Operation Error on:
- Remote Operation Error: Responder encountered an error, (local to the responder),
- which prevented it from completing the request. */
-/* -------------- */
- pseudo_bit_t rq_num_roe[0x00020]; /* Responder - number of remote operation errors.
- NAK-Remote Operation Error on:
- 1. Malformed WQE: Responder detected a malformed Receive Queue WQE while pro-cessing
- the packet.
- 2. Remote Operation Error: Responder encountered an error, (local to the responder),
- which prevented it from completing the request. */
-/* -------------- */
- pseudo_bit_t sq_num_tree[0x00020]; /* Requester - number of transport retries exceeded errors */
-/* -------------- */
- pseudo_bit_t reserved3[0x00020];
-/* -------------- */
- pseudo_bit_t sq_num_rree[0x00020]; /* Requester - number of RNR nak retries exceeded errors */
-/* -------------- */
- pseudo_bit_t reserved4[0x00020];
-/* -------------- */
- pseudo_bit_t sq_num_lrdve[0x00020]; /* Requester - number of local RDD violation errors */
-/* -------------- */
- pseudo_bit_t rq_num_rirdre[0x00020];/* Responder - number of remote invalid RD request errors */
-/* -------------- */
- pseudo_bit_t reserved5[0x00040];
-/* -------------- */
- pseudo_bit_t sq_num_rabrte[0x00020];/* Requester - number of remote aborted errors */
-/* -------------- */
- pseudo_bit_t reserved6[0x00020];
-/* -------------- */
- pseudo_bit_t sq_num_ieecne[0x00020];/* Requester - number of invalid EE context number errors */
-/* -------------- */
- pseudo_bit_t reserved7[0x00020];
-/* -------------- */
- pseudo_bit_t sq_num_ieecse[0x00020];/* Requester - invalid EE context state errors */
-/* -------------- */
- pseudo_bit_t reserved8[0x00380];
-/* -------------- */
- pseudo_bit_t rq_num_oos[0x00020]; /* Responder - number of out of sequence requests received */
-/* -------------- */
- pseudo_bit_t sq_num_oos[0x00020]; /* Requester - number of out of sequence Naks received */
-/* -------------- */
- pseudo_bit_t rq_num_mce[0x00020]; /* Responder - number of bad multicast packets received */
-/* -------------- */
- pseudo_bit_t reserved9[0x00020];
-/* -------------- */
- pseudo_bit_t rq_num_rsync[0x00020]; /* Responder - number of RESYNC operations */
-/* -------------- */
- pseudo_bit_t sq_num_rsync[0x00020]; /* Requester - number of RESYNC operations */
-/* -------------- */
- pseudo_bit_t rq_num_udsdprd[0x00020];/* The number of UD packets silently discarded on the receive queue due to lack of receive descriptor. */
-/* -------------- */
- pseudo_bit_t reserved10[0x00020];
-/* -------------- */
- pseudo_bit_t rq_num_ucsdprd[0x00020];/* The number of UC packets silently discarded on the receive queue due to lack of receive descriptor. */
-/* -------------- */
- pseudo_bit_t reserved11[0x003e0];
-/* -------------- */
- pseudo_bit_t num_cqovf[0x00020]; /* Number of CQ overflows */
-/* -------------- */
- pseudo_bit_t num_eqovf[0x00020]; /* Number of EQ overflows */
-/* -------------- */
- pseudo_bit_t num_baddb[0x00020]; /* Number of bad doorbells */
-/* -------------- */
- pseudo_bit_t reserved12[0x002a0];
-/* -------------- */
-};
-
-/* Event_data Field - HCR Completion Event */
-
-struct arbelprm_hcr_completion_event_st { /* Little Endian */
- pseudo_bit_t token[0x00010]; /* HCR Token */
- pseudo_bit_t reserved0[0x00010];
-/* -------------- */
- pseudo_bit_t reserved1[0x00020];
-/* -------------- */
- pseudo_bit_t status[0x00008]; /* HCR Status */
- pseudo_bit_t reserved2[0x00018];
-/* -------------- */
- pseudo_bit_t out_param_h[0x00020]; /* HCR Output Parameter [63:32] */
-/* -------------- */
- pseudo_bit_t out_param_l[0x00020]; /* HCR Output Parameter [31:0] */
-/* -------------- */
- pseudo_bit_t reserved3[0x00020];
-/* -------------- */
-};
-
-/* Completion with Error CQE */
-
-struct arbelprm_completion_with_error_st { /* Little Endian */
- pseudo_bit_t myqpn[0x00018]; /* Indicates the QP for which completion is being reported */
- pseudo_bit_t reserved0[0x00008];
-/* -------------- */
- pseudo_bit_t reserved1[0x00060];
-/* -------------- */
- pseudo_bit_t reserved2[0x00010];
- pseudo_bit_t vendor_code[0x00008];
- pseudo_bit_t syndrome[0x00008]; /* Completion with error syndrome:
- 0x01 - Local Length Error
- 0x02 - Local QP Operation Error
- 0x03 - Local EE Context Operation Error
- 0x04 - Local Protection Error
- 0x05 - Work Request Flushed Error
- 0x06 - Memory Window Bind Error
- 0x10 - Bad Response Error
- 0x11 - Local Access Error
- 0x12 - Remote Invalid Request Error
- 0x13 - Remote Access Error
- 0x14 - Remote Operation Error
- 0x15 - Transport Retry Counter Exceeded
- 0x16 - RNR Retry Counter Exceeded
- 0x20 - Local RDD Violation Error
- 0x21 - Remote Invalid RD Request
- 0x22 - Remote Aborted Error
- 0x23 - Invalid EE Context Number
- 0x24 - Invalid EE Context State
- other - Reserved
- Syndrome is defined according to the IB specification volume 1. For detailed explanation of the syndromes, refer to chapters 10-11 of the IB specification rev 1.1. */
-/* -------------- */
- pseudo_bit_t reserved3[0x00020];
-/* -------------- */
- pseudo_bit_t reserved4[0x00006];
- pseudo_bit_t wqe_addr[0x0001a]; /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */
-/* -------------- */
- pseudo_bit_t reserved5[0x00007];
- pseudo_bit_t owner[0x00001]; /* Owner field. Zero value of this field means SW ownership of CQE. */
- pseudo_bit_t reserved6[0x00010];
- pseudo_bit_t opcode[0x00008]; /* The opcode of WQE completion is reported for.
-
- The following values are reported in case of completion with error:
- 0xFE - For completion with error on Receive Queues
- 0xFF - For completion with error on Send Queues */
-/* -------------- */
-};
-
-/* Resize CQ Input Mailbox */
-
-struct arbelprm_resize_cq_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00020];
-/* -------------- */
- pseudo_bit_t start_addr_h[0x00020]; /* Start address of CQ[63:32].
- Must be aligned on CQE size (32 bytes) */
-/* -------------- */
- pseudo_bit_t start_addr_l[0x00020]; /* Start address of CQ[31:0].
- Must be aligned on CQE size (32 bytes) */
-/* -------------- */
- pseudo_bit_t reserved1[0x00018];
- pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries) */
- pseudo_bit_t reserved2[0x00003];
-/* -------------- */
- pseudo_bit_t reserved3[0x00060];
-/* -------------- */
- pseudo_bit_t l_key[0x00020]; /* Memory key (L_Key) to be used to access CQ */
-/* -------------- */
- pseudo_bit_t reserved4[0x00100];
-/* -------------- */
-};
-
-/* MAD_IFC Input Modifier */
-
-struct arbelprm_mad_ifc_input_modifier_st { /* Little Endian */
- pseudo_bit_t port_number[0x00008]; /* The packet reception port number (1 or 2). */
- pseudo_bit_t mad_extended_info[0x00001];/* Mad_Extended_Info valid bit (MAD_IFC Input Mailbox data from offset 00100h and down). MAD_Extended_Info is read only if this bit is set.
- Required for trap generation when BKey check is enabled and for global routed packets. */
- pseudo_bit_t reserved0[0x00007];
- pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD.
- This field is required for trap generation upon MKey/BKey validation. */
-/* -------------- */
-};
-
-/* MAD_IFC Input Mailbox */
-
-struct arbelprm_mad_ifc_st { /* Little Endian */
- pseudo_bit_t request_mad_packet[64][0x00020];/* Request MAD Packet (256bytes) */
-/* -------------- */
- pseudo_bit_t my_qpn[0x00018]; /* Destination QP number from the received MAD.
- This field is reserved if Mad_extended_info indication in the input modifier is clear. */
- pseudo_bit_t reserved0[0x00008];
-/* -------------- */
- pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number from the received MAD.
- This field is reserved if Mad_extended_info indication in the input modifier is clear. */
- pseudo_bit_t reserved1[0x00008];
-/* -------------- */
- pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD.
- This field is reserved if Mad_extended_info indication in the input modifier is clear. */
- pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits from the received MAD.
- This field is reserved if Mad_extended_info indication in the input modifier is clear. */
- pseudo_bit_t g[0x00001]; /* If set, the GRH field in valid.
- This field is reserved if Mad_extended_info indication in the input modifier is clear. */
- pseudo_bit_t reserved2[0x00004];
- pseudo_bit_t sl[0x00004]; /* Service Level of the received MAD.
- This field is reserved if Mad_extended_info indication in the input modifier is clear. */
-/* -------------- */
- pseudo_bit_t pkey_indx[0x00010]; /* Index in PKey table that matches PKey of the received MAD.
- This field is reserved if Mad_extended_info indication in the input modifier is clear. */
- pseudo_bit_t reserved3[0x00010];
-/* -------------- */
- pseudo_bit_t reserved4[0x00180];
-/* -------------- */
- pseudo_bit_t grh[10][0x00020]; /* The GRH field of the MAD packet that was scattered to the first 40 bytes pointed to by the scatter list.
- Valid if Mad_extended_info bit (in the input modifier) and g bit are set.
- Otherwise this field is reserved. */
-/* -------------- */
- pseudo_bit_t reserved5[0x004c0];
-/* -------------- */
-};
-
-/* Query Debug Message */
-
-struct arbelprm_query_debug_msg_st { /* Little Endian */
- pseudo_bit_t phy_addr_h[0x00020]; /* Translation of the address in firmware area. High 32 bits. */
-/* -------------- */
- pseudo_bit_t v[0x00001]; /* Physical translation is valid */
- pseudo_bit_t reserved0[0x0000b];
- pseudo_bit_t phy_addr_l[0x00014]; /* Translation of the address in firmware area. Low 32 bits. */
-/* -------------- */
- pseudo_bit_t fw_area_base[0x00020]; /* Firmware area base address. The format strings and the trace buffers may be located starting from this address. */
-/* -------------- */
- pseudo_bit_t fw_area_size[0x00020]; /* Firmware area size */
-/* -------------- */
- pseudo_bit_t trc_hdr_sz[0x00020]; /* Trace message header size in dwords. */
-/* -------------- */
- pseudo_bit_t trc_arg_num[0x00020]; /* The number of arguments per trace message. */
-/* -------------- */
- pseudo_bit_t reserved1[0x000c0];
-/* -------------- */
- pseudo_bit_t dbg_msk_h[0x00020]; /* Debug messages mask [63:32] */
-/* -------------- */
- pseudo_bit_t dbg_msk_l[0x00020]; /* Debug messages mask [31:0] */
-/* -------------- */
- pseudo_bit_t reserved2[0x00040];
-/* -------------- */
- pseudo_bit_t buff0_addr[0x00020]; /* Address in firmware area of Trace Buffer 0 */
-/* -------------- */
- pseudo_bit_t buff0_size[0x00020]; /* Size of Trace Buffer 0 */
-/* -------------- */
- pseudo_bit_t buff1_addr[0x00020]; /* Address in firmware area of Trace Buffer 1 */
-/* -------------- */
- pseudo_bit_t buff1_size[0x00020]; /* Size of Trace Buffer 1 */
-/* -------------- */
- pseudo_bit_t buff2_addr[0x00020]; /* Address in firmware area of Trace Buffer 2 */
-/* -------------- */
- pseudo_bit_t buff2_size[0x00020]; /* Size of Trace Buffer 2 */
-/* -------------- */
- pseudo_bit_t buff3_addr[0x00020]; /* Address in firmware area of Trace Buffer 3 */
-/* -------------- */
- pseudo_bit_t buff3_size[0x00020]; /* Size of Trace Buffer 3 */
-/* -------------- */
- pseudo_bit_t buff4_addr[0x00020]; /* Address in firmware area of Trace Buffer 4 */
-/* -------------- */
- pseudo_bit_t buff4_size[0x00020]; /* Size of Trace Buffer 4 */
-/* -------------- */
- pseudo_bit_t buff5_addr[0x00020]; /* Address in firmware area of Trace Buffer 5 */
-/* -------------- */
- pseudo_bit_t buff5_size[0x00020]; /* Size of Trace Buffer 5 */
-/* -------------- */
- pseudo_bit_t buff6_addr[0x00020]; /* Address in firmware area of Trace Buffer 6 */
-/* -------------- */
- pseudo_bit_t buff6_size[0x00020]; /* Size of Trace Buffer 6 */
-/* -------------- */
- pseudo_bit_t buff7_addr[0x00020]; /* Address in firmware area of Trace Buffer 7 */
-/* -------------- */
- pseudo_bit_t buff7_size[0x00020]; /* Size of Trace Buffer 7 */
-/* -------------- */
- pseudo_bit_t reserved3[0x00400];
-/* -------------- */
-};
-
-/* User Access Region */
-
-struct arbelprm_uar_st { /* Little Endian */
- struct arbelprm_rd_send_doorbell_st rd_send_doorbell;/* Reliable Datagram send doorbell */
-/* -------------- */
- struct arbelprm_send_doorbell_st send_doorbell;/* Send doorbell */
-/* -------------- */
- pseudo_bit_t reserved0[0x00040];
-/* -------------- */
- struct arbelprm_cq_cmd_doorbell_st cq_command_doorbell;/* CQ Doorbell */
-/* -------------- */
- pseudo_bit_t reserved1[0x03ec0];
-/* -------------- */
-};
-
-/* Receive doorbell */
-
-struct arbelprm_receive_doorbell_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00008];
- pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted on this queue since its creation. Should be zero for the first doorbell on the QP */
- pseudo_bit_t reserved1[0x00008];
-/* -------------- */
- pseudo_bit_t reserved2[0x00005];
- pseudo_bit_t srq[0x00001]; /* If set, this is a Shared Receive Queue */
- pseudo_bit_t reserved3[0x00002];
- pseudo_bit_t qpn[0x00018]; /* QP number or SRQ number this doorbell is rung on */
-/* -------------- */
-};
-
-/* SET_IB Parameters */
-
-struct arbelprm_set_ib_st { /* Little Endian */
- pseudo_bit_t rqk[0x00001]; /* Reset QKey Violation Counter */
- pseudo_bit_t reserved0[0x00011];
- pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified.
- system_image_guid and sig must be the same for all ports. */
- pseudo_bit_t reserved1[0x0000d];
-/* -------------- */
- pseudo_bit_t capability_mask[0x00020];/* PortInfo Capability Mask */
-/* -------------- */
- pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set
- Must be the same for both ports. */
-/* -------------- */
- pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set
- Must be the same for both ports. */
-/* -------------- */
- pseudo_bit_t reserved2[0x00180];
-/* -------------- */
-};
-
-/* Multicast Group Member */
-
-struct arbelprm_mgm_entry_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00006];
- pseudo_bit_t next_gid_index[0x0001a];/* Index of next Multicast Group Member whose GID maps to same MGID_HASH number.
- The index is into the Multicast Group Table, which is the comprised the MGHT and AMGM tables.
- next_gid_index=0 means end of the chain. */
-/* -------------- */
- pseudo_bit_t reserved1[0x00060];
-/* -------------- */
- pseudo_bit_t mgid_128_96[0x00020]; /* Multicast group GID[128:96] in big endian format.
- Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
-/* -------------- */
- pseudo_bit_t mgid_95_64[0x00020]; /* Multicast group GID[95:64] in big endian format.
- Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
-/* -------------- */
- pseudo_bit_t mgid_63_32[0x00020]; /* Multicast group GID[63:32] in big endian format.
- Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
-/* -------------- */
- pseudo_bit_t mgid_31_0[0x00020]; /* Multicast group GID[31:0] in big endian format.
- Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
-/* -------------- */
- struct arbelprm_mgmqp_st mgmqp_0; /* Multicast Group Member QP */
-/* -------------- */
- struct arbelprm_mgmqp_st mgmqp_1; /* Multicast Group Member QP */
-/* -------------- */
- struct arbelprm_mgmqp_st mgmqp_2; /* Multicast Group Member QP */
-/* -------------- */
- struct arbelprm_mgmqp_st mgmqp_3; /* Multicast Group Member QP */
-/* -------------- */
- struct arbelprm_mgmqp_st mgmqp_4; /* Multicast Group Member QP */
-/* -------------- */
- struct arbelprm_mgmqp_st mgmqp_5; /* Multicast Group Member QP */
-/* -------------- */
- struct arbelprm_mgmqp_st mgmqp_6; /* Multicast Group Member QP */
-/* -------------- */
- struct arbelprm_mgmqp_st mgmqp_7; /* Multicast Group Member QP */
-/* -------------- */
-};
-
-/* INIT_IB Parameters */
-
-struct arbelprm_init_ib_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00004];
- pseudo_bit_t vl_cap[0x00004]; /* Maximum VLs supported on the port, excluding VL15.
- Legal values are 1,2,4 and 8. */
- pseudo_bit_t port_width_cap[0x00004];/* IB Port Width
- 1 - 1x
- 3 - 1x, 4x
- 11 - 1x, 4x or 12x (must not be used in InfiniHost-III-EX MT25208)
- else - Reserved */
- pseudo_bit_t mtu_cap[0x00004]; /* Maximum MTU Supported
- 0x0 - Reserved
- 0x1 - 256
- 0x2 - 512
- 0x3 - 1024
- 0x4 - 2048
- 0x5 - 0xF Reserved */
- pseudo_bit_t g0[0x00001]; /* Set port GUID0 to GUID0 specified */
- pseudo_bit_t ng[0x00001]; /* Set node GUID to node_guid specified.
- node_guid and ng must be the same for all ports. */
- pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified.
- system_image_guid and sig must be the same for all ports. */
- pseudo_bit_t reserved1[0x0000d];
-/* -------------- */
- pseudo_bit_t max_gid[0x00010]; /* Maximum number of GIDs for the port */
- pseudo_bit_t reserved2[0x00010];
-/* -------------- */
- pseudo_bit_t max_pkey[0x00010]; /* Maximum pkeys for the port.
- Must be the same for both ports. */
- pseudo_bit_t reserved3[0x00010];
-/* -------------- */
- pseudo_bit_t reserved4[0x00020];
-/* -------------- */
- pseudo_bit_t guid0_h[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 63:32) */
-/* -------------- */
- pseudo_bit_t guid0_l[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 31:0) */
-/* -------------- */
- pseudo_bit_t node_guid_h[0x00020]; /* Node GUID[63:32], takes effect only if the NG bit is set
- Must be the same for both ports. */
-/* -------------- */
- pseudo_bit_t node_guid_l[0x00020]; /* Node GUID[31:0], takes effect only if the NG bit is set
- Must be the same for both ports. */
-/* -------------- */
- pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set
- Must be the same for both ports. */
-/* -------------- */
- pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set
- Must be the same for both ports. */
-/* -------------- */
- pseudo_bit_t reserved5[0x006c0];
-/* -------------- */
-};
-
-/* Query Device Limitations */
-
-struct arbelprm_query_dev_lim_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00080];
-/* -------------- */
- pseudo_bit_t log_max_qp[0x00005]; /* Log2 of the Maximum number of QPs supported */
- pseudo_bit_t reserved1[0x00003];
- pseudo_bit_t log2_rsvd_qps[0x00004];/* Log (base 2) of the number of QPs reserved for firmware use
- The reserved resources are numbered from 0 to 2^log2_rsvd_qps-1 */
- pseudo_bit_t reserved2[0x00004];
- pseudo_bit_t log_max_qp_sz[0x00008];/* The maximum number of WQEs allowed on the RQ or the SQ is 2^log_max_qp_sz-1 */
- pseudo_bit_t log_max_srq_sz[0x00008];/* The maximum number of WQEs allowed on the SRQ is 2^log_max_srq_sz-1 */
-/* -------------- */
- pseudo_bit_t log_max_ee[0x00005]; /* Log2 of the Maximum number of EE contexts supported */
- pseudo_bit_t reserved3[0x00003];
- pseudo_bit_t log2_rsvd_ees[0x00004];/* Log (base 2) of the number of EECs reserved for firmware use
- The reserved resources are numbered from 0 to 2^log2_rsvd_ees-1 */
- pseudo_bit_t reserved4[0x00004];
- pseudo_bit_t log_max_srqs[0x00005]; /* Log base 2 of the maximum number of SRQs supported, valid only if SRQ bit is set.
- */
- pseudo_bit_t reserved5[0x00007];
- pseudo_bit_t log2_rsvd_srqs[0x00004];/* Log (base 2) of the number of reserved SRQs for firmware use
- The reserved resources are numbered from 0 to 2^log2_rsvd_srqs-1
- This parameter is valid only if the SRQ bit is set. */
-/* -------------- */
- pseudo_bit_t log_max_cq[0x00005]; /* Log2 of the Maximum number of CQs supported */
- pseudo_bit_t reserved6[0x00003];
- pseudo_bit_t log2_rsvd_cqs[0x00004];/* Log (base 2) of the number of CQs reserved for firmware use
- The reserved resources are numbered from 0 to 2^log2_rsrvd_cqs-1 */
- pseudo_bit_t reserved7[0x00004];
- pseudo_bit_t log_max_cq_sz[0x00008];/* Log2 of the Maximum CQEs allowed in a CQ */
- pseudo_bit_t reserved8[0x00008];
-/* -------------- */
- pseudo_bit_t log_max_eq[0x00003]; /* Log2 of the Maximum number of EQs */
- pseudo_bit_t reserved9[0x00005];
- pseudo_bit_t num_rsvd_eqs[0x00004]; /* The number of EQs reserved for firmware use
- The reserved resources are numbered from 0 to num_rsvd_eqs-1
- If 0 - no resources are reserved. */
- pseudo_bit_t reserved10[0x00004];
- pseudo_bit_t log_max_mpts[0x00006]; /* Log (base 2) of the maximum number of MPT entries (the number of Regions/Windows) */
- pseudo_bit_t reserved11[0x00002];
- pseudo_bit_t log_max_eq_sz[0x00008];/* Log2 of the Maximum EQEs allowed in a EQ */
-/* -------------- */
- pseudo_bit_t log_max_mtts[0x00006]; /* Log2 of the Maximum number of MTT entries */
- pseudo_bit_t reserved12[0x00002];
- pseudo_bit_t log2_rsvd_mrws[0x00004];/* Log (base 2) of the number of MPTs reserved for firmware use
- The reserved resources are numbered from 0 to 2^log2_rsvd_mrws-1 */
- pseudo_bit_t reserved13[0x00004];
- pseudo_bit_t log_max_mrw_sz[0x00008];/* Log2 of the Maximum Size of Memory Region/Window */
- pseudo_bit_t reserved14[0x00004];
- pseudo_bit_t log2_rsvd_mtts[0x00004];/* Log (base 2) of the number of MTT entries reserved for firmware use
- The reserved resources are numbered from 0 to 2^log2_rsvd_mtts-1
- */
-/* -------------- */
- pseudo_bit_t reserved15[0x00020];
-/* -------------- */
- pseudo_bit_t log_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */
- pseudo_bit_t reserved16[0x0000a];
- pseudo_bit_t log_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */
- pseudo_bit_t reserved17[0x0000a];
-/* -------------- */
- pseudo_bit_t log_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */
- pseudo_bit_t reserved18[0x00016];
- pseudo_bit_t log2_rsvd_rdbs[0x00004];/* Log (base 2) of the number of RDB entries reserved for firmware use
- The reserved resources are numbered from 0 to 2^log2_rsvd_rdbs-1 */
-/* -------------- */
- pseudo_bit_t rsz_srq[0x00001]; /* Ability to modify the maximum number of WRs per SRQ. */
- pseudo_bit_t reserved19[0x0001f];
-/* -------------- */
- pseudo_bit_t num_ports[0x00004]; /* Number of IB ports. */
- pseudo_bit_t max_vl[0x00004]; /* Maximum VLs supported on each port, excluding VL15 */
- pseudo_bit_t max_port_width[0x00004];/* IB Port Width
- 1 - 1x
- 3 - 1x, 4x
- 11 - 1x, 4x or 12x
- else - Reserved */
- pseudo_bit_t max_mtu[0x00004]; /* Maximum MTU Supported
- 0x0 - Reserved
- 0x1 - 256
- 0x2 - 512
- 0x3 - 1024
- 0x4 - 2048
- 0x5 - 0xF Reserved */
- pseudo_bit_t local_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb.
- The delay value in microseconds is computed using 4.096us * 2^(local_ca_ack_delay). */
- pseudo_bit_t reserved20[0x0000b];
-/* -------------- */
- pseudo_bit_t log_max_gid[0x00004]; /* Log2 of the maximum number of GIDs per port */
- pseudo_bit_t reserved21[0x0001c];
-/* -------------- */
- pseudo_bit_t log_max_pkey[0x00004]; /* Log2 of the max PKey Table Size (per IB port) */
- pseudo_bit_t reserved22[0x0000c];
- pseudo_bit_t stat_rate_support[0x00010];/* bit mask of stat rate supported
- bit 0 - full bw
- bit 1 - 1/4 bw
- bit 2 - 1/8 bw
- bit 3 - 1/2 bw; */
-/* -------------- */
- pseudo_bit_t reserved23[0x00020];
-/* -------------- */
- pseudo_bit_t rc[0x00001]; /* RC Transport supported */
- pseudo_bit_t uc[0x00001]; /* UC Transport Supported */
- pseudo_bit_t ud[0x00001]; /* UD Transport Supported */
- pseudo_bit_t rd[0x00001]; /* RD Transport Supported */
- pseudo_bit_t raw_ipv6[0x00001]; /* Raw IPv6 Transport Supported */
- pseudo_bit_t raw_ether[0x00001]; /* Raw Ethertype Transport Supported */
- pseudo_bit_t srq[0x00001]; /* SRQ is supported
- */
- pseudo_bit_t ipo_ib_checksum[0x00001];/* IP over IB checksum is supported */
- pseudo_bit_t pkv[0x00001]; /* PKey Violation Counter Supported */
- pseudo_bit_t qkv[0x00001]; /* QKey Violation Coutner Supported */
- pseudo_bit_t reserved24[0x00006];
- pseudo_bit_t mw[0x00001]; /* Memory windows supported */
- pseudo_bit_t apm[0x00001]; /* Automatic Path Migration Supported */
- pseudo_bit_t atm[0x00001]; /* Atomic operations supported (atomicity is guaranteed between QPs on this HCA) */
- pseudo_bit_t rm[0x00001]; /* Raw Multicast Supported */
- pseudo_bit_t avp[0x00001]; /* Address Vector Port checking supported */
- pseudo_bit_t udm[0x00001]; /* UD Multicast Supported */
- pseudo_bit_t reserved25[0x00002];
- pseudo_bit_t pg[0x00001]; /* Paging on demand supported */
- pseudo_bit_t r[0x00001]; /* Router mode supported */
- pseudo_bit_t reserved26[0x00006];
-/* -------------- */
- pseudo_bit_t log_pg_sz[0x00008]; /* Minimum system page size supported (log2).
- For proper operation it must be less than or equal the hosting platform (CPU) minimum page size. */
- pseudo_bit_t reserved27[0x00008];
- pseudo_bit_t uar_sz[0x00006]; /* UAR Area Size = 1MB * 2^uar_sz */
- pseudo_bit_t reserved28[0x00006];
- pseudo_bit_t num_rsvd_uars[0x00004];/* The number of UARs reserved for firmware use
- The reserved resources are numbered from 0 to num_reserved_uars-1
- Note that UAR number num_reserved_uars is always for the kernel. */
-/* -------------- */
- pseudo_bit_t reserved29[0x00020];
-/* -------------- */
- pseudo_bit_t max_desc_sz_sq[0x00010];/* Max descriptor size in bytes for the send queue */
- pseudo_bit_t max_sg_sq[0x00008]; /* The maximum S/G list elements in a SQ WQE (max_desc_sz/16 - 3) */
- pseudo_bit_t reserved30[0x00008];
-/* -------------- */
- pseudo_bit_t max_desc_sz_rq[0x00010];/* Max descriptor size in bytes for the receive queue */
- pseudo_bit_t max_sg_rq[0x00008]; /* The maximum S/G list elements in a RQ WQE (max_desc_sz/16 - 3) */
- pseudo_bit_t reserved31[0x00008];
-/* -------------- */
- pseudo_bit_t reserved32[0x00040];
-/* -------------- */
- pseudo_bit_t log_max_mcg[0x00008]; /* Log2 of the maximum number of multicast groups */
- pseudo_bit_t num_rsvd_mcgs[0x00004];/* The number of MGMs reserved for firmware use in the MGHT.
- The reserved resources are numbered from 0 to num_reserved_mcgs-1
- If 0 - no resources are reserved. */
- pseudo_bit_t reserved33[0x00004];
- pseudo_bit_t log_max_qp_mcg[0x00008];/* Log2 of the maximum number of QPs per multicast group */
- pseudo_bit_t reserved34[0x00008];
-/* -------------- */
- pseudo_bit_t log_max_rdds[0x00006]; /* Log2 of the maximum number of RDDs */
- pseudo_bit_t reserved35[0x00006];
- pseudo_bit_t num_rsvd_rdds[0x00004];/* The number of RDDs reserved for firmware use
- The reserved resources are numbered from 0 to num_reserved_rdds-1.
- If 0 - no resources are reserved. */
- pseudo_bit_t log_max_pd[0x00006]; /* Log2 of the maximum number of PDs */
- pseudo_bit_t reserved36[0x00006];
- pseudo_bit_t num_rsvd_pds[0x00004]; /* The number of PDs reserved for firmware use
- The reserved resources are numbered from 0 to num_reserved_pds-1
- If 0 - no resources are reserved. */
-/* -------------- */
- pseudo_bit_t reserved37[0x000c0];
-/* -------------- */
- pseudo_bit_t qpc_entry_sz[0x00010]; /* QPC Entry Size for the device
- For the InfiniHost-III-EX MT25208 entry size is 256 bytes */
- pseudo_bit_t eec_entry_sz[0x00010]; /* EEC Entry Size for the device
- For the InfiniHost-III-EX MT25208 entry size is 256 bytes */
-/* -------------- */
- pseudo_bit_t eqpc_entry_sz[0x00010];/* Extended QPC entry size for the device
- For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
- pseudo_bit_t eeec_entry_sz[0x00010];/* Extended EEC entry size for the device
- For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
-/* -------------- */
- pseudo_bit_t cqc_entry_sz[0x00010]; /* CQC entry size for the device
- For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
- pseudo_bit_t eqc_entry_sz[0x00010]; /* EQ context entry size for the device
- For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
-/* -------------- */
- pseudo_bit_t uar_scratch_entry_sz[0x00010];/* UAR Scratchpad Entry Size
- For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
- pseudo_bit_t srq_entry_sz[0x00010]; /* SRQ context entry size for the device
- For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
-/* -------------- */
- pseudo_bit_t mpt_entry_sz[0x00010]; /* MPT entry size in Bytes for the device.
- For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
- pseudo_bit_t mtt_entry_sz[0x00010]; /* MTT entry size in Bytes for the device.
- For the InfiniHost-III-EX MT25208 entry size is 8 bytes */
-/* -------------- */
- pseudo_bit_t bmme[0x00001]; /* Base Memory Management Extension Support */
- pseudo_bit_t win_type[0x00001]; /* Bound Type 2 Memory Window Association mechanism:
- 0 - Type 2A - QP Number Association; or
- 1 - Type 2B - QP Number and PD Association. */
- pseudo_bit_t mps[0x00001]; /* Ability of this HCA to support multiple page sizes per Memory Region. */
- pseudo_bit_t bl[0x00001]; /* Ability of this HCA to support Block List Physical Buffer Lists. (The device does not supports Block List) */
- pseudo_bit_t zb[0x00001]; /* Zero Based region/windows supported */
- pseudo_bit_t lif[0x00001]; /* Ability of this HCA to support Local Invalidate Fencing. */
- pseudo_bit_t reserved38[0x00002];
- pseudo_bit_t log_pbl_sz[0x00006]; /* Log2 of the Maximum Physical Buffer List size in Bytes supported by this HCA when invoking the Allocate L_Key verb.
- */
- pseudo_bit_t reserved39[0x00012];
-/* -------------- */
- pseudo_bit_t resd_lkey[0x00020]; /* The value of the reserved Lkey for Base Memory Management Extension */
-/* -------------- */
- pseudo_bit_t lamr[0x00001]; /* When set the device requires local attached memory in order to operate.
- When set, ICM pages, Firmware Area and ICM auxiliary pages must be allocated in the local attached memory. */
- pseudo_bit_t reserved40[0x0001f];
-/* -------------- */
- pseudo_bit_t max_icm_size_h[0x00020];/* Bits [63:32] of maximum ICM size InfiniHost III Ex support in bytes. */
-/* -------------- */
- pseudo_bit_t max_icm_size_l[0x00020];/* Bits [31:0] of maximum ICM size InfiniHost III Ex support in bytes. */
-/* -------------- */
- pseudo_bit_t reserved41[0x002c0];
-/* -------------- */
-};
-
-/* QUERY_ADAPTER Parameters Block */
-
-struct arbelprm_query_adapter_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00080];
-/* -------------- */
- pseudo_bit_t reserved1[0x00018];
- pseudo_bit_t intapin[0x00008]; /* Driver should set this field to INTR value in the event queue in order to get Express interrupt messages. */
-/* -------------- */
- pseudo_bit_t reserved2[0x00060];
-/* -------------- */
- struct arbelprm_vsd_st vsd;
-/* -------------- */
-};
-
-/* QUERY_FW Parameters Block */
-
-struct arbelprm_query_fw_st { /* Little Endian */
- pseudo_bit_t fw_rev_major[0x00010]; /* Firmware Revision - Major */
- pseudo_bit_t fw_pages[0x00010]; /* Amount of physical memory to be allocated for FW usage is in 4KByte pages. */
-/* -------------- */
- pseudo_bit_t fw_rev_minor[0x00010]; /* Firmware Revision - Minor */
- pseudo_bit_t fw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */
-/* -------------- */
- pseudo_bit_t cmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */
- pseudo_bit_t reserved0[0x0000e];
- pseudo_bit_t wqe_h_mode[0x00001]; /* Hermon mode. If '1', then WQE and AV format is the advanced format */
- pseudo_bit_t zb_wq_cq[0x00001]; /* If '1', then ZB mode of WQ and CQ are enabled (i.e. real Memfree PRM is supported) */
-/* -------------- */
- pseudo_bit_t log_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */
- pseudo_bit_t reserved1[0x00017];
- pseudo_bit_t dt[0x00001]; /* Debug Trace Support
- 0 - Debug trace is not supported
- 1 - Debug trace is supported */
-/* -------------- */
- pseudo_bit_t cmd_interface_db[0x00001];/* Set if the device accepts commands by means of special doorbells */
- pseudo_bit_t reserved2[0x0001f];
-/* -------------- */
- pseudo_bit_t reserved3[0x00060];
-/* -------------- */
- pseudo_bit_t clr_int_base_addr_h[0x00020];/* Bits [63:32] of Clear interrupt register physical address.
- Points to 64 bit register. */
-/* -------------- */
- pseudo_bit_t clr_int_base_addr_l[0x00020];/* Bits [31:0] of Clear interrupt register physical address.
- Points to 64 bit register. */
-/* -------------- */
- pseudo_bit_t reserved4[0x00040];
-/* -------------- */
- pseudo_bit_t error_buf_start_h[0x00020];/* Read Only buffer for catastrophic error reports (physical address) */
-/* -------------- */
- pseudo_bit_t error_buf_start_l[0x00020];/* Read Only buffer for catastrophic error reports (physical address) */
-/* -------------- */
- pseudo_bit_t error_buf_size[0x00020];/* Size in words */
-/* -------------- */
- pseudo_bit_t reserved5[0x00020];
-/* -------------- */
- pseudo_bit_t eq_arm_base_addr_h[0x00020];/* Bits [63:32] of EQ Arm DBs physical address.
- Points to 64 bit register.
- Setting bit x in the offset, arms EQ number x.
- */
-/* -------------- */
- pseudo_bit_t eq_arm_base_addr_l[0x00020];/* Bits [31:0] of EQ Arm DBs physical address.
- Points to 64 bit register.
- Setting bit x in the offset, arms EQ number x. */
-/* -------------- */
- pseudo_bit_t eq_set_ci_base_addr_h[0x00020];/* Bits [63:32] of EQ Set CI DBs Table physical address.
- Points to a the EQ Set CI DBs Table base address. */
-/* -------------- */
- pseudo_bit_t eq_set_ci_base_addr_l[0x00020];/* Bits [31:0] of EQ Set CI DBs Table physical address.
- Points to a the EQ Set CI DBs Table base address. */
-/* -------------- */
- pseudo_bit_t cmd_db_dw1[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 1 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
- pseudo_bit_t cmd_db_dw0[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 0 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
-/* -------------- */
- pseudo_bit_t cmd_db_dw3[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 3 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
- pseudo_bit_t cmd_db_dw2[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 2 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
-/* -------------- */
- pseudo_bit_t cmd_db_dw5[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 5 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
- pseudo_bit_t cmd_db_dw4[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 4 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
-/* -------------- */
- pseudo_bit_t cmd_db_dw7[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 7 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
- pseudo_bit_t cmd_db_dw6[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 6 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
-/* -------------- */
- pseudo_bit_t cmd_db_addr_base_h[0x00020];/* High bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */
-/* -------------- */
- pseudo_bit_t cmd_db_addr_base_l[0x00020];/* Low bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */
-/* -------------- */
- pseudo_bit_t reserved6[0x004c0];
-/* -------------- */
-};
-
-/* ACCESS_LAM */
-
-struct arbelprm_access_lam_st { /* Little Endian */
- struct arbelprm_access_lam_inject_errors_st access_lam_inject_errors;
-/* -------------- */
- pseudo_bit_t reserved0[0x00080];
-/* -------------- */
-};
-
-/* ENABLE_LAM Parameters Block */
-
-struct arbelprm_enable_lam_st { /* Little Endian */
- pseudo_bit_t lam_start_adr_h[0x00020];/* LAM start address [63:32] */
-/* -------------- */
- pseudo_bit_t lam_start_adr_l[0x00020];/* LAM start address [31:0] */
-/* -------------- */
- pseudo_bit_t lam_end_adr_h[0x00020];/* LAM end address [63:32] */
-/* -------------- */
- pseudo_bit_t lam_end_adr_l[0x00020];/* LAM end address [31:0] */
-/* -------------- */
- pseudo_bit_t di[0x00002]; /* Data Integrity Configuration:
- 00 - none
- 01 - Parity
- 10 - ECC Detection Only
- 11 - ECC With Correction */
- pseudo_bit_t ap[0x00002]; /* Auto Precharge Mode
- 00 - No auto precharge
- 01 - Auto precharge per transaction
- 10 - Auto precharge per 64 bytes
- 11 - reserved */
- pseudo_bit_t dh[0x00001]; /* When set, LAM is Hidden and can not be accessed directly from the PCI bus. */
- pseudo_bit_t reserved0[0x0001b];
-/* -------------- */
- pseudo_bit_t reserved1[0x00160];
-/* -------------- */
- struct arbelprm_dimminfo_st dimm0; /* Logical DIMM 0 Parameters */
-/* -------------- */
- struct arbelprm_dimminfo_st dimm1; /* Logical DIMM 1 Parameters */
-/* -------------- */
- pseudo_bit_t reserved2[0x00400];
-/* -------------- */
-};
-
-/* Memory Access Parameters for UD Address Vector Table */
-
-struct arbelprm_udavtable_memory_parameters_st { /* Little Endian */
- pseudo_bit_t l_key[0x00020]; /* L_Key used to access TPT */
-/* -------------- */
- pseudo_bit_t pd[0x00018]; /* PD used by TPT for matching against PD of region entry being accessed. */
- pseudo_bit_t reserved0[0x00005];
- pseudo_bit_t xlation_en[0x00001]; /* When cleared, address is physical address and no translation will be done. When set, address is virtual. */
- pseudo_bit_t reserved1[0x00002];
-/* -------------- */
-};
-
-/* INIT_HCA & QUERY_HCA Parameters Block */
-
-struct arbelprm_init_hca_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00060];
-/* -------------- */
- pseudo_bit_t reserved1[0x00010];
- pseudo_bit_t time_stamp_granularity[0x00008];/* This field controls the granularity in which CQE Timestamp counter is incremented.
- The TimeStampGranularity units is 1/4 of a microseconds. (e.g is TimeStampGranularity is configured to 0x2, CQE Timestamp will be incremented every one microsecond)
- When sets to Zero, timestamp reporting in the CQE is disabled.
- This feature is currently not supported.
- */
- pseudo_bit_t hca_core_clock[0x00008];/* Internal Clock Period (in units of 1/16 ns) (QUERY_HCA only) */
-/* -------------- */
- pseudo_bit_t reserved2[0x00008];
- pseudo_bit_t router_qp[0x00010]; /* Upper 16 bit to be used as a QP number for router mode. Low order 8 bits are taken from the TClass field of the incoming packet.
- Valid only if RE bit is set */
- pseudo_bit_t reserved3[0x00007];
- pseudo_bit_t re[0x00001]; /* Router Mode Enable
- If this bit is set, entire packet (including all headers and ICRC) will be considered as a data payload and will be scattered to memory as specified in the descriptor that is posted on the QP matching the TClass field of packet. */
-/* -------------- */
- pseudo_bit_t udp[0x00001]; /* UD Port Check Enable
- 0 - Port field in Address Vector is ignored
- 1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */
- pseudo_bit_t he[0x00001]; /* Host Endianess - Used for Atomic Operations
- 0 - Host is Little Endian
- 1 - Host is Big endian
- */
- pseudo_bit_t reserved4[0x00001];
- pseudo_bit_t ce[0x00001]; /* Checksum Enabled - when Set IPoverIB checksum generation & checking is enabled */
- pseudo_bit_t sph[0x00001]; /* 0 - SW calculates TCP/UDP Pseudo-Header checksum and inserts it into the TCP/UDP checksum field when sending a packet
- 1 - HW calculates TCP/UDP Pseudo-Header checksum when sending a packet
- */
- pseudo_bit_t rph[0x00001]; /* 0 - Not HW calculation of TCP/UDP Pseudo-Header checksum are done when receiving a packet
- 1 - HW calculates TCP/UDP Pseudo-Header checksum when receiving a packet
- */
- pseudo_bit_t reserved5[0x00002];
- pseudo_bit_t responder_exu[0x00004];/* Indicate the relation between the execution enegines allocation dedicated for responder versus the engines dedicated for reqvester .
- responder_exu/16 = (number of responder exu engines)/(total number of engines)
- Legal values are 0x0-0xF. 0 is "auto".
-
- */
- pseudo_bit_t reserved6[0x00004];
- pseudo_bit_t wqe_quota[0x0000f]; /* Maximum number of WQEs that are executed prior to preemption of execution unit. 0 - reserved. */
- pseudo_bit_t wqe_quota_en[0x00001]; /* If set - wqe_quota field is used. If cleared - WQE quota is set to "auto" value */
-/* -------------- */
- pseudo_bit_t reserved7[0x00040];
-/* -------------- */
- struct arbelprm_qpcbaseaddr_st qpc_eec_cqc_eqc_rdb_parameters;
-/* -------------- */
- pseudo_bit_t reserved8[0x00100];
-/* -------------- */
- struct arbelprm_multicastparam_st multicast_parameters;
-/* -------------- */
- pseudo_bit_t reserved9[0x00080];
-/* -------------- */
- struct arbelprm_tptparams_st tpt_parameters;
-/* -------------- */
- pseudo_bit_t reserved10[0x00080];
-/* -------------- */
- struct arbelprm_uar_params_st uar_parameters;/* UAR Parameters */
-/* -------------- */
- pseudo_bit_t reserved11[0x00600];
-/* -------------- */
-};
-
-/* Event Queue Context Table Entry */
-
-struct arbelprm_eqc_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00008];
- pseudo_bit_t st[0x00004]; /* Event delivery state machine
- 0x9 - Armed
- 0xA - Fired
- 0xB - Always_Armed (auto-rearm)
- other - reserved */
- pseudo_bit_t reserved1[0x00005];
- pseudo_bit_t oi[0x00001]; /* Oerrun ignore.
- If set, HW will not check EQ full condition when writing new EQEs. */
- pseudo_bit_t tr[0x00001]; /* Translation Required. If set - EQ access undergo address translation. */
- pseudo_bit_t reserved2[0x00005];
- pseudo_bit_t owner[0x00004]; /* 0 - SW ownership
- 1 - HW ownership
- Valid for the QUERY_EQ and HW2SW_EQ commands only */
- pseudo_bit_t status[0x00004]; /* EQ status:
- 0000 - OK
- 1010 - EQ write failure
- Valid for the QUERY_EQ and HW2SW_EQ commands only */
-/* -------------- */
- pseudo_bit_t start_address_h[0x00020];/* Start Address of Event Queue[63:32]. */
-/* -------------- */
- pseudo_bit_t start_address_l[0x00020];/* Start Address of Event Queue[31:0].
- Must be aligned on 32-byte boundary */
-/* -------------- */
- pseudo_bit_t reserved3[0x00018];
- pseudo_bit_t log_eq_size[0x00005]; /* Amount of entries in this EQ is 2^log_eq_size.
- Log_eq_size must be bigger than 1.
- Maximum EQ size is 2^17 EQEs (max Log_eq_size is 17). */
- pseudo_bit_t reserved4[0x00003];
-/* -------------- */
- pseudo_bit_t reserved5[0x00020];
-/* -------------- */
- pseudo_bit_t intr[0x00008]; /* Interrupt (message) to be generated to report event to INT layer.
- 00iiiiii - set to INTA given in QUERY_ADAPTER in order to generate INTA messages on Express.
- 10jjjjjj - specificies type of interrupt message to be generated (total 64 different messages supported).
- All other values are reserved and should not be used.
-
- If interrupt generation is not required, ST field must be set upon creation to Fired state. No EQ arming doorbell should be performed. In this case hardware will not generate any interrupt. */
- pseudo_bit_t reserved6[0x00018];
-/* -------------- */
- pseudo_bit_t pd[0x00018]; /* PD to be used to access EQ */
- pseudo_bit_t reserved7[0x00008];
-/* -------------- */
- pseudo_bit_t lkey[0x00020]; /* Memory key (L-Key) to be used to access EQ */
-/* -------------- */
- pseudo_bit_t reserved8[0x00040];
-/* -------------- */
- pseudo_bit_t consumer_indx[0x00020];/* Contains next entry to be read upon polling the event queue.
- Must be initalized to zero while opening EQ */
-/* -------------- */
- pseudo_bit_t producer_indx[0x00020];/* Contains next entry in EQ to be written by the HCA.
- Must be initalized to zero while opening EQ. */
-/* -------------- */
- pseudo_bit_t reserved9[0x00080];
-/* -------------- */
-};
-
-/* Memory Translation Table (MTT) Entry */
-
-struct arbelprm_mtt_st { /* Little Endian */
- pseudo_bit_t ptag_h[0x00020]; /* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
-/* -------------- */
- pseudo_bit_t p[0x00001]; /* Present bit. If set, page entry is valid. If cleared, access to this page will generate non-present page access fault. */
- pseudo_bit_t reserved0[0x0000b];
- pseudo_bit_t ptag_l[0x00014]; /* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
-/* -------------- */
-};
-
-/* Memory Protection Table (MPT) Entry */
-
-struct arbelprm_mpt_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00008];
- pseudo_bit_t r_w[0x00001]; /* Defines whether this entry is Region (1) or Window (0) */
- pseudo_bit_t pa[0x00001]; /* Physical address. If set, no virtual-to-physical address translation will be performed for this region */
- pseudo_bit_t lr[0x00001]; /* If set - local read access enabled */
- pseudo_bit_t lw[0x00001]; /* If set - local write access enabled */
- pseudo_bit_t rr[0x00001]; /* If set - remote read access enabled. */
- pseudo_bit_t rw[0x00001]; /* If set - remote write access enabled */
- pseudo_bit_t a[0x00001]; /* If set - remote Atomic access is enabled */
- pseudo_bit_t eb[0x00001]; /* If set - Bind is enabled. Valid for region entry only. */
- pseudo_bit_t reserved1[0x0000c];
- pseudo_bit_t status[0x00004]; /* Region/Window Status
- 0xF - not valid (SW ownership)
- 0x3 - FREE state
- else - HW ownership
- Unbound Type I windows are doneted reg_wnd_len field equals zero.
- Unbound Type II windows are donated by Status=FREE. */
-/* -------------- */
- pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes.
- page_size should be less than 20. */
- pseudo_bit_t reserved2[0x00002];
- pseudo_bit_t type[0x00001]; /* Applicable for windows only, must be zero for regions
- 0 - Type one window
- 1 - Type two window */
- pseudo_bit_t qpn[0x00018]; /* QP number this MW is attached to. Valid for type2 memory windows and on QUERY_MPT only */
-/* -------------- */
- pseudo_bit_t mem_key[0x00020]; /* The memory Key. The field holds the mem_key field in the following semantics: {key[7:0],key[31:8]}.
- */
-/* -------------- */
- pseudo_bit_t pd[0x00018]; /* Protection Domain */
- pseudo_bit_t reserved3[0x00001];
- pseudo_bit_t ei[0x00001]; /* Enable Invalidation - When set, Local/Remote invalidation can be executed on this window/region.
- Must be set for type2 windows and non-shared physical memory regions.
- Must be clear for regions that are used to access Work Queues, Completion Queues and Event Queues */
- pseudo_bit_t zb[0x00001]; /* When set, this region is Zero Based Region */
- pseudo_bit_t fre[0x00001]; /* When set, Fast Registration Operations can be executed on this region */
- pseudo_bit_t rae[0x00001]; /* When set, remote access can be enabled on this region.
- Used when executing Fast Registration Work Request to validate that remote access rights can be granted to this MPT.
- If the bit is cleared, Fast Registration Work Request requesting remote access rights will fail.
- */
- pseudo_bit_t reserved4[0x00003];
-/* -------------- */
- pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region/window starts */
-/* -------------- */
- pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region/window starts */
-/* -------------- */
- pseudo_bit_t reg_wnd_len_h[0x00020];/* Region/Window Length[63:32] */
-/* -------------- */
- pseudo_bit_t reg_wnd_len_l[0x00020];/* Region/Window Length[31:0] */
-/* -------------- */
- pseudo_bit_t lkey[0x00020]; /* Must be 0 for SW2HW_MPT.
- On QUERY_MPT and HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to.
- The field holds the lkey field in the following semantics: {key[7:0],key[31:8]}. */
-/* -------------- */
- pseudo_bit_t win_cnt[0x00020]; /* Number of windows bound to this region. Valid for regions only.
- The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */
-/* -------------- */
- pseudo_bit_t reserved5[0x00020];
-/* -------------- */
- pseudo_bit_t mtt_adr_h[0x00006]; /* Base (first) address of the MTT relative to MTT base in the ICM */
- pseudo_bit_t reserved6[0x0001a];
-/* -------------- */
- pseudo_bit_t reserved7[0x00003];
- pseudo_bit_t mtt_adr_l[0x0001d]; /* Base (first) address of the MTT relative to MTT base address in the ICM. Must be aligned on 8 bytes. */
-/* -------------- */
- pseudo_bit_t mtt_sz[0x00020]; /* Number of MTT entries allocated for this MR.
- When Fast Registration Operations can not be executed on this region (FRE bit is zero) this field is reserved.
- When Fast Registration Operation is enabled (FRE bit is set) this field indicates the number of MTTs allocated for this MR. If mtt_sz value is zero, there is no limit for the numbers of MTTs and the HCA does not check this field when executing fast register WQE. */
-/* -------------- */
- pseudo_bit_t reserved8[0x00040];
-/* -------------- */
-};
-
-/* Completion Queue Context Table Entry */
-
-struct arbelprm_completion_queue_context_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00008];
- pseudo_bit_t st[0x00004]; /* Event delivery state machine
- 0x0 - reserved
- 0x9 - ARMED (Request for Notification)
- 0x6 - ARMED SOLICITED (Request Solicited Notification)
- 0xA - FIRED
- other - reserved
-
- Must be 0x0 in CQ initialization.
- Valid for the QUERY_CQ and HW2SW_CQ commands only. */
- pseudo_bit_t reserved1[0x00005];
- pseudo_bit_t oi[0x00001]; /* When set, overrun ignore is enabled.
- When set, Updates of CQ consumer counter (poll for completion) or Request completion notifications (Arm CQ) doorbells should not be rang on that CQ. */
- pseudo_bit_t reserved2[0x0000a];
- pseudo_bit_t status[0x00004]; /* CQ status
- 0000 - OK
- 1001 - CQ overflow
- 1010 - CQ write failure
- Valid for the QUERY_CQ and HW2SW_CQ commands only */
-/* -------------- */
- pseudo_bit_t start_address_h[0x00020];/* Start address of CQ[63:32].
- Must be aligned on CQE size (32 bytes) */
-/* -------------- */
- pseudo_bit_t start_address_l[0x00020];/* Start address of CQ[31:0].
- Must be aligned on CQE size (32 bytes) */
-/* -------------- */
- pseudo_bit_t usr_page[0x00018]; /* UAR page this CQ can be accessed through (ringinig CQ doorbells) */
- pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries).
- Maximum CQ size is 2^17 CQEs (max log_cq_size is 17) */
- pseudo_bit_t reserved3[0x00003];
-/* -------------- */
- pseudo_bit_t reserved4[0x00020];
-/* -------------- */
- pseudo_bit_t c_eqn[0x00008]; /* Event Queue this CQ reports completion events to.
- Valid values are 0 to 63
- If configured to value other than 0-63, completion events will not be reported on the CQ. */
- pseudo_bit_t reserved5[0x00018];
-/* -------------- */
- pseudo_bit_t pd[0x00018]; /* Protection Domain to be used to access CQ.
- Must be the same PD of the CQ L_Key. */
- pseudo_bit_t reserved6[0x00008];
-/* -------------- */
- pseudo_bit_t l_key[0x00020]; /* Memory key (L_Key) to be used to access CQ */
-/* -------------- */
- pseudo_bit_t last_notified_indx[0x00020];/* Maintained by HW.
- Valid for QUERY_CQ and HW2SW_CQ commands only. */
-/* -------------- */
- pseudo_bit_t solicit_producer_indx[0x00020];/* Maintained by HW.
- Valid for QUERY_CQ and HW2SW_CQ commands only.
- */
-/* -------------- */
- pseudo_bit_t consumer_counter[0x00020];/* Consumer counter is a 32bits counter that is incremented for each CQE pooled from the CQ.
- Must be 0x0 in CQ initialization.
- Valid for the QUERY_CQ and HW2SW_CQ commands only. */
-/* -------------- */
- pseudo_bit_t producer_counter[0x00020];/* Producer counter is a 32bits counter that is incremented for each CQE that is written by the HW to the CQ.
- CQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a CQE needs to be added..
- Maintained by HW (valid for the QUERY_CQ and HW2SW_CQ commands only) */
-/* -------------- */
- pseudo_bit_t cqn[0x00018]; /* CQ number. Least significant bits are constrained by the position of this CQ in CQC table
- Valid for the QUERY_CQ and HW2SW_CQ commands only */
- pseudo_bit_t reserved7[0x00008];
-/* -------------- */
- pseudo_bit_t cq_ci_db_record[0x00020];/* Index in the UAR Context Table Entry.
- HW uses this index as an offset from the UAR Context Table Entry in order to read this CQ Consumer Counter doorbell record.
- This value can be retrieved from the HW in the QUERY_CQ command. */
-/* -------------- */
- pseudo_bit_t cq_state_db_record[0x00020];/* Index in the UAR Context Table Entry.
- HW uses this index as an offset from the UAR Context Table Entry in order to read this CQ state doorbell record.
- This value can be retrieved from the HW in the QUERY_CQ command. */
-/* -------------- */
- pseudo_bit_t reserved8[0x00020];
-/* -------------- */
-};
-
-/* GPIO_event_data */
-
-struct arbelprm_gpio_event_data_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00060];
-/* -------------- */
- pseudo_bit_t gpio_event_hi[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */
-/* -------------- */
- pseudo_bit_t gpio_event_lo[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */
-/* -------------- */
- pseudo_bit_t reserved1[0x00020];
-/* -------------- */
-};
-
-/* Event_data Field - QP/EE Events */
-
-struct arbelprm_qp_ee_event_st { /* Little Endian */
- pseudo_bit_t qpn_een[0x00018]; /* QP/EE/SRQ number event is reported for */
- pseudo_bit_t reserved0[0x00008];
-/* -------------- */
- pseudo_bit_t reserved1[0x00020];
-/* -------------- */
- pseudo_bit_t reserved2[0x0001c];
- pseudo_bit_t e_q[0x00001]; /* If set - EEN if cleared - QP in the QPN/EEN field
- Not valid on SRQ events */
- pseudo_bit_t reserved3[0x00003];
-/* -------------- */
- pseudo_bit_t reserved4[0x00060];
-/* -------------- */
-};
-
-/* InfiniHost-III-EX Type0 Configuration Header */
-
-struct arbelprm_mt25208_type0_st { /* Little Endian */
- pseudo_bit_t vendor_id[0x00010]; /* Hardwired to 0x15B3 */
- pseudo_bit_t device_id[0x00010]; /* 25208 (decimal) - InfiniHost-III compatible mode
- 25218 (decimal) - InfiniHost-III EX mode (the mode described in this manual)
- 25209 (decimal) - Flash burner mode - see Flash burning application note for further details on this mode
- */
-/* -------------- */
- pseudo_bit_t command[0x00010]; /* PCI Command Register */
- pseudo_bit_t status[0x00010]; /* PCI Status Register */
-/* -------------- */
- pseudo_bit_t revision_id[0x00008];
- pseudo_bit_t class_code_hca_class_code[0x00018];
-/* -------------- */
- pseudo_bit_t cache_line_size[0x00008];/* Cache Line Size */
- pseudo_bit_t latency_timer[0x00008];
- pseudo_bit_t header_type[0x00008]; /* hardwired to zero */
- pseudo_bit_t bist[0x00008];
-/* -------------- */
- pseudo_bit_t bar0_ctrl[0x00004]; /* hard-wired to 0100 */
- pseudo_bit_t reserved0[0x00010];
- pseudo_bit_t bar0_l[0x0000c]; /* Lower bits of BAR0 (Device Configuration Space) */
-/* -------------- */
- pseudo_bit_t bar0_h[0x00020]; /* Upper 32 bits of BAR0 (Device Configuration Space) */
-/* -------------- */
- pseudo_bit_t bar1_ctrl[0x00004]; /* Hardwired to 1100 */
- pseudo_bit_t reserved1[0x00010];
- pseudo_bit_t bar1_l[0x0000c]; /* Lower bits of BAR1 (User Access Region - UAR - space) */
-/* -------------- */
- pseudo_bit_t bar1_h[0x00020]; /* upper 32 bits of BAR1 (User Access Region - UAR - space) */
-/* -------------- */
- pseudo_bit_t bar2_ctrl[0x00004]; /* Hardwired to 1100 */
- pseudo_bit_t reserved2[0x00010];
- pseudo_bit_t bar2_l[0x0000c]; /* Lower bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */
-/* -------------- */
- pseudo_bit_t bar2_h[0x00020]; /* Upper 32 bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */
-/* -------------- */
- pseudo_bit_t cardbus_cis_pointer[0x00020];
-/* -------------- */
- pseudo_bit_t subsystem_vendor_id[0x00010];/* Specified by the device NVMEM configuration */
- pseudo_bit_t subsystem_id[0x00010]; /* Specified by the device NVMEM configuration */
-/* -------------- */
- pseudo_bit_t expansion_rom_enable[0x00001];/* Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
- pseudo_bit_t reserved3[0x0000a];
- pseudo_bit_t expansion_rom_base_address[0x00015];/* Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
-/* -------------- */
- pseudo_bit_t capabilities_pointer[0x00008];/* Specified by the device NVMEM configuration */
- pseudo_bit_t reserved4[0x00018];
-/* -------------- */
- pseudo_bit_t reserved5[0x00020];
-/* -------------- */
- pseudo_bit_t interrupt_line[0x00008];
- pseudo_bit_t interrupt_pin[0x00008];
- pseudo_bit_t min_gnt[0x00008];
- pseudo_bit_t max_latency[0x00008];
-/* -------------- */
- pseudo_bit_t reserved6[0x00100];
-/* -------------- */
- pseudo_bit_t msi_cap_id[0x00008];
- pseudo_bit_t msi_next_cap_ptr[0x00008];
- pseudo_bit_t msi_en[0x00001];
- pseudo_bit_t multiple_msg_cap[0x00003];
- pseudo_bit_t multiple_msg_en[0x00003];
- pseudo_bit_t cap_64_bit_addr[0x00001];
- pseudo_bit_t reserved7[0x00008];
-/* -------------- */
- pseudo_bit_t msg_addr_l[0x00020];
-/* -------------- */
- pseudo_bit_t msg_addr_h[0x00020];
-/* -------------- */
- pseudo_bit_t msg_data[0x00010];
- pseudo_bit_t reserved8[0x00010];
-/* -------------- */
- pseudo_bit_t reserved9[0x00080];
-/* -------------- */
- pseudo_bit_t pm_cap_id[0x00008]; /* Power management capability ID - 01h */
- pseudo_bit_t pm_next_cap_ptr[0x00008];
- pseudo_bit_t pm_cap[0x00010]; /* [2:0] Version - 02h
- [3] PME clock - 0h
- [4] RsvP
- [5] Device specific initialization - 0h
- [8:6] AUX current - 0h
- [9] D1 support - 0h
- [10] D2 support - 0h
- [15:11] PME support - 0h */
-/* -------------- */
- pseudo_bit_t pm_status_control[0x00010];/* [14:13] - Data scale - 0h */
- pseudo_bit_t pm_control_status_brdg_ext[0x00008];
- pseudo_bit_t data[0x00008];
-/* -------------- */
- pseudo_bit_t reserved10[0x00040];
-/* -------------- */
- pseudo_bit_t vpd_cap_id[0x00008]; /* 03h */
- pseudo_bit_t vpd_next_cap_id[0x00008];
- pseudo_bit_t vpd_address[0x0000f];
- pseudo_bit_t f[0x00001];
-/* -------------- */
- pseudo_bit_t vpd_data[0x00020];
-/* -------------- */
- pseudo_bit_t reserved11[0x00040];
-/* -------------- */
- pseudo_bit_t pciex_cap_id[0x00008]; /* PCI-Express capability ID - 10h */
- pseudo_bit_t pciex_next_cap_ptr[0x00008];
- pseudo_bit_t pciex_cap[0x00010]; /* [3:0] Capability version - 1h
- [7:4] Device/Port Type - 0h
- [8] Slot implemented - 0h
- [13:9] Interrupt message number
- */
-/* -------------- */
- pseudo_bit_t device_cap[0x00020]; /* [2:0] Max_Payload_Size supported - 2h
- [4:3] Phantom Function supported - 0h
- [5] Extended Tag Filed supported - 0h
- [8:6] Endpoint L0s Acceptable Latency - TBD
- [11:9] Endpoint L1 Acceptable Latency - TBD
- [12] Attention Button Present - configured through InfiniBurn
- [13] Attention Indicator Present - configured through InfiniBurn
- [14] Power Indicator Present - configured through InfiniBurn
- [25:18] Captured Slot Power Limit Value
- [27:26] Captured Slot Power Limit Scale */
-/* -------------- */
- pseudo_bit_t device_control[0x00010];
- pseudo_bit_t device_status[0x00010];
-/* -------------- */
- pseudo_bit_t link_cap[0x00020]; /* [3:0] Maximum Link Speed - 1h
- [9:4] Maximum Link Width - 8h
- [11:10] Active State Power Management Support - 3h
- [14:12] L0s Exit Latency - TBD
- [17:15] L1 Exit Latency - TBD
- [31:24] Port Number - 0h */
-/* -------------- */
- pseudo_bit_t link_control[0x00010];
- pseudo_bit_t link_status[0x00010]; /* [3:0] Link Speed - 1h
- [9:4] Negotiated Link Width
- [12] Slot clock configuration - 1h */
-/* -------------- */
- pseudo_bit_t reserved12[0x00260];
-/* -------------- */
- pseudo_bit_t advanced_error_reporting_cap_id[0x00010];/* 0001h. */
- pseudo_bit_t capability_version[0x00004];/* 1h */
- pseudo_bit_t next_capability_offset[0x0000c];/* 0h */
-/* -------------- */
- pseudo_bit_t uncorrectable_error_status_register[0x00020];/* 0 Training Error Status
- 4 Data Link Protocol Error Status
- 12 Poisoned TLP Status
- 13 Flow Control Protocol Error Status
- 14 Completion Timeout Status
- 15 Completer Abort Status
- 16 Unexpected Completion Status
- 17 Receiver Overflow Status
- 18 Malformed TLP Status
- 19 ECRC Error Status
- 20 Unsupported Request Error Status */
-/* -------------- */
- pseudo_bit_t uncorrectable_error_mask_register[0x00020];/* 0 Training Error Mask
- 4 Data Link Protocol Error Mask
- 12 Poisoned TLP Mask
- 13 Flow Control Protocol Error Mask
- 14 Completion Timeout Mask
- 15 Completer Abort Mask
- 16 Unexpected Completion Mask
- 17 Receiver Overflow Mask
- 18 Malformed TLP Mask
- 19 ECRC Error Mask
- 20 Unsupported Request Error Mask */
-/* -------------- */
- pseudo_bit_t uncorrectable_severity_mask_register[0x00020];/* 0 Training Error Severity
- 4 Data Link Protocol Error Severity
- 12 Poisoned TLP Severity
- 13 Flow Control Protocol Error Severity
- 14 Completion Timeout Severity
- 15 Completer Abort Severity
- 16 Unexpected Completion Severity
- 17 Receiver Overflow Severity
- 18 Malformed TLP Severity
- 19 ECRC Error Severity
- 20 Unsupported Request Error Severity */
-/* -------------- */
- pseudo_bit_t correctable_error_status_register[0x00020];/* 0 Receiver Error Status
- 6 Bad TLP Status
- 7 Bad DLLP Status
- 8 REPLAY_NUM Rollover Status
- 12 Replay Timer Timeout Status */
-/* -------------- */
- pseudo_bit_t correctable_error_mask_register[0x00020];/* 0 Receiver Error Mask
- 6 Bad TLP Mask
- 7 Bad DLLP Mask
- 8 REPLAY_NUM Rollover Mask
- 12 Replay Timer Timeout Mask */
-/* -------------- */
- pseudo_bit_t advance_error_capabilities_and_control_register[0x00020];
-/* -------------- */
- struct arbelprm_header_log_register_st header_log_register;
-/* -------------- */
- pseudo_bit_t reserved13[0x006a0];
-/* -------------- */
-};
-
-/* Event Data Field - Performance Monitor */
-
-struct arbelprm_performance_monitor_event_st { /* Little Endian */
- struct arbelprm_performance_monitors_st performance_monitor_snapshot;/* Performance monitor snapshot */
-/* -------------- */
- pseudo_bit_t monitor_number[0x00008];/* 0x01 - SQPC
- 0x02 - RQPC
- 0x03 - CQC
- 0x04 - Rkey
- 0x05 - TLB
- 0x06 - port0
- 0x07 - port1 */
- pseudo_bit_t reserved0[0x00018];
-/* -------------- */
- pseudo_bit_t reserved1[0x00040];
-/* -------------- */
-};
-
-/* Event_data Field - Page Faults */
-
-struct arbelprm_page_fault_event_data_st { /* Little Endian */
- pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32] this page fault is reported on */
-/* -------------- */
- pseudo_bit_t va_l[0x00020]; /* Virtual Address[63:32] this page fault is reported on */
-/* -------------- */
- pseudo_bit_t mem_key[0x00020]; /* Memory Key this page fault is reported on */
-/* -------------- */
- pseudo_bit_t qp[0x00018]; /* QP this page fault is reported on */
- pseudo_bit_t reserved0[0x00003];
- pseudo_bit_t a[0x00001]; /* If set the memory access that caused the page fault was atomic */
- pseudo_bit_t lw[0x00001]; /* If set the memory access that caused the page fault was local write */
- pseudo_bit_t lr[0x00001]; /* If set the memory access that caused the page fault was local read */
- pseudo_bit_t rw[0x00001]; /* If set the memory access that caused the page fault was remote write */
- pseudo_bit_t rr[0x00001]; /* If set the memory access that caused the page fault was remote read */
-/* -------------- */
- pseudo_bit_t pd[0x00018]; /* PD this page fault is reported on */
- pseudo_bit_t reserved1[0x00008];
-/* -------------- */
- pseudo_bit_t prefetch_len[0x00020]; /* Indicates how many subsequent pages in the same memory region/window will be accessed by the following transaction after this page fault is resolved. measured in bytes. SW can use this information in order to page-in the subsequent pages if they are not present. */
-/* -------------- */
-};
-
-/* WQE segments format */
-
-struct arbelprm_wqe_segment_st { /* Little Endian */
- struct arbelprm_send_wqe_segment_st send_wqe_segment;/* Send WQE segment format */
-/* -------------- */
- pseudo_bit_t reserved0[0x00280];
-/* -------------- */
- struct arbelprm_wqe_segment_ctrl_mlx_st mlx_wqe_segment_ctrl;/* MLX WQE segment format */
-/* -------------- */
- pseudo_bit_t reserved1[0x00100];
-/* -------------- */
- struct arbelprm_wqe_segment_ctrl_recv_st recv_wqe_segment_ctrl;/* Receive segment format */
-/* -------------- */
- pseudo_bit_t reserved2[0x00080];
-/* -------------- */
-};
-
-/* Event_data Field - Port State Change */
-
-struct arbelprm_port_state_change_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00040];
-/* -------------- */
- pseudo_bit_t reserved1[0x0001c];
- pseudo_bit_t p[0x00002]; /* Port number (1 or 2) */
- pseudo_bit_t reserved2[0x00002];
-/* -------------- */
- pseudo_bit_t reserved3[0x00060];
-/* -------------- */
-};
-
-/* Event_data Field - Completion Queue Error */
-
-struct arbelprm_completion_queue_error_st { /* Little Endian */
- pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */
- pseudo_bit_t reserved0[0x00008];
-/* -------------- */
- pseudo_bit_t reserved1[0x00020];
-/* -------------- */
- pseudo_bit_t syndrome[0x00008]; /* Error syndrome
- 0x01 - CQ overrun
- 0x02 - CQ access violation error */
- pseudo_bit_t reserved2[0x00018];
-/* -------------- */
- pseudo_bit_t reserved3[0x00060];
-/* -------------- */
-};
-
-/* Event_data Field - Completion Event */
-
-struct arbelprm_completion_event_st { /* Little Endian */
- pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */
- pseudo_bit_t reserved0[0x00008];
-/* -------------- */
- pseudo_bit_t reserved1[0x000a0];
-/* -------------- */
-};
-
-/* Event Queue Entry */
-
-struct arbelprm_event_queue_entry_st { /* Little Endian */
- pseudo_bit_t event_sub_type[0x00008];/* Event Sub Type.
- Defined for events which have sub types, zero elsewhere. */
- pseudo_bit_t reserved0[0x00008];
- pseudo_bit_t event_type[0x00008]; /* Event Type */
- pseudo_bit_t reserved1[0x00008];
-/* -------------- */
- pseudo_bit_t event_data[6][0x00020];/* Delivers auxilary data to handle event. */
-/* -------------- */
- pseudo_bit_t reserved2[0x00007];
- pseudo_bit_t owner[0x00001]; /* Owner of the entry
- 0 SW
- 1 HW */
- pseudo_bit_t reserved3[0x00018];
-/* -------------- */
-};
-
-/* QP/EE State Transitions Command Parameters */
-
-struct arbelprm_qp_ee_state_transitions_st { /* Little Endian */
- pseudo_bit_t opt_param_mask[0x00020];/* This field defines which optional parameters are passed. Each bit specifies whether optional parameter is passed (set) or not (cleared). The optparammask is defined for each QP/EE command. */
-/* -------------- */
- pseudo_bit_t reserved0[0x00020];
-/* -------------- */
- struct arbelprm_queue_pair_ee_context_entry_st qpc_eec_data;/* QPC/EEC data */
-/* -------------- */
- pseudo_bit_t reserved1[0x009c0];
-/* -------------- */
-};
-
-/* Completion Queue Entry Format */
-
-struct arbelprm_completion_queue_entry_st { /* Little Endian */
- pseudo_bit_t my_qpn[0x00018]; /* Indicates the QP for which completion is being reported */
- pseudo_bit_t reserved0[0x00004];
- pseudo_bit_t ver[0x00004]; /* CQE version.
- 0 for InfiniHost-III-EX */
-/* -------------- */
- pseudo_bit_t my_ee[0x00018]; /* EE context (for RD only).
- Invalid for Bind and Nop operation on RD.
- For non RD services this filed reports the CQE timestamp. The Timestamp is a free running counter that is incremented every TimeStampGranularity tick. The counter rolls-over when it reaches saturation. TimeStampGranularity is configured in the INIT_HCA command. This feature is currently not supported.
- */
- pseudo_bit_t checksum_15_8[0x00008];/* Checksum[15:8] - See IPoverIB checksum offloading chapter */
-/* -------------- */
- pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number. Valid in Responder CQE only for Datagram QP. */
- pseudo_bit_t checksum_7_0[0x00008]; /* Checksum[7:0] - See IPoverIB checksum offloading chapter */
-/* -------------- */
- pseudo_bit_t rlid[0x00010]; /* Remote (source) LID of the message. Valid in Responder of UD QP CQE only. */
- pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits - these are the lowemost LMC bits of the DLID in an incoming UD packet, higher bits of this field, that are not part of the LMC bits are zeroed by HW.
- Valid in responder of UD QP CQE only.
- Invalid if incoming message DLID is the permissive LID or incoming message is multicast. */
- pseudo_bit_t g[0x00001]; /* GRH present indicator. Valid in Responder of UD QP CQE only. */
- pseudo_bit_t ipok[0x00001]; /* IP OK - See IPoverIB checksum offloading chapter */
- pseudo_bit_t reserved1[0x00003];
- pseudo_bit_t sl[0x00004]; /* Service Level of the message. Valid in Responder of UD QP CQE only. */
-/* -------------- */
- pseudo_bit_t immediate_ethertype_pkey_indx_eecredits[0x00020];/* Valid for receive queue completion only.
- If Opcode field indicates that this was send/write with immediate, this field contains immediate field of the packet.
- If completion corresponds to RAW receive queue, bits 15:0 contain Ethertype field of the packet.
- If completion corresponds to GSI receive queue, bits 31:16 contain index in PKey table that matches PKey of the message arrived.
- If Opcode field indicates that this was send and invalidate, this field contains the key that was invalidated.
- For CQE of send queue of the reliable connection service (but send and invalide), bits [4:0] of this field contain the encoded EEcredits received in last ACK of the message. */
-/* -------------- */
- pseudo_bit_t byte_cnt[0x00020]; /* Byte count of data actually transferred (valid for receive queue completions only) */
-/* -------------- */
- pseudo_bit_t reserved2[0x00006];
- pseudo_bit_t wqe_adr[0x0001a]; /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */
-/* -------------- */
- pseudo_bit_t reserved3[0x00007];
- pseudo_bit_t owner[0x00001]; /* Owner field. Zero value of this field means SW ownership of CQE. */
- pseudo_bit_t reserved4[0x0000f];
- pseudo_bit_t s[0x00001]; /* If set, completion is reported for Send queue, if cleared - receive queue. */
- pseudo_bit_t opcode[0x00008]; /* The opcode of WQE completion is reported for.
- For CQEs corresponding to send completion, NOPCODE field of the WQE is copied to this field.
- For CQEs corresponding to receive completions, opcode field of last packet in the message copied to this field.
- For CQEs corresponding to the receive queue of QPs mapped to QP1, the opcode will be SEND with Immediate (messages are guaranteed to be SEND only)
-
- The following values are reported in case of completion with error:
- 0xFE - For completion with error on Receive Queues
- 0xFF - For completion with error on Send Queues */
-/* -------------- */
-};
-
-/* */
-
-struct arbelprm_ecc_detect_event_data_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00080];
-/* -------------- */
- pseudo_bit_t cause_lsb[0x00001];
- pseudo_bit_t reserved1[0x00002];
- pseudo_bit_t cause_msb[0x00001];
- pseudo_bit_t reserved2[0x00002];
- pseudo_bit_t err_rmw[0x00001];
- pseudo_bit_t err_src_id[0x00003];
- pseudo_bit_t err_da[0x00002];
- pseudo_bit_t err_ba[0x00002];
- pseudo_bit_t reserved3[0x00011];
- pseudo_bit_t overflow[0x00001];
-/* -------------- */
- pseudo_bit_t err_ra[0x00010];
- pseudo_bit_t err_ca[0x00010];
-/* -------------- */
-};
-
-/* Event_data Field - ECC Detection Event */
-
-struct arbelprm_scrubbing_event_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00080];
-/* -------------- */
- pseudo_bit_t cause_lsb[0x00001]; /* data integrity error cause:
- single ECC error in the 64bit lsb data, on the rise edge of the clock */
- pseudo_bit_t reserved1[0x00002];
- pseudo_bit_t cause_msb[0x00001]; /* data integrity error cause:
- single ECC error in the 64bit msb data, on the fall edge of the clock */
- pseudo_bit_t reserved2[0x00002];
- pseudo_bit_t err_rmw[0x00001]; /* transaction type:
- 0 - read
- 1 - read/modify/write */
- pseudo_bit_t err_src_id[0x00003]; /* source of the transaction: 0x4 - PCI, other - internal or IB */
- pseudo_bit_t err_da[0x00002]; /* Error DIMM address */
- pseudo_bit_t err_ba[0x00002]; /* Error bank address */
- pseudo_bit_t reserved3[0x00011];
- pseudo_bit_t overflow[0x00001]; /* Fatal: ECC error FIFO overflow - ECC errors were detected, which may or may not have been corrected by InfiniHost-III-EX */
-/* -------------- */
- pseudo_bit_t err_ra[0x00010]; /* Error row address */
- pseudo_bit_t err_ca[0x00010]; /* Error column address */
-/* -------------- */
-};
-
-/* Miscellaneous Counters */
-
-struct arbelprm_misc_counters_st { /* Little Endian */
- pseudo_bit_t ddr_scan_cnt[0x00020]; /* Number of times whole of LAM was scanned */
-/* -------------- */
- pseudo_bit_t reserved0[0x007e0];
-/* -------------- */
-};
-
-/* LAM_EN Output Parameter */
-
-struct arbelprm_lam_en_out_param_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00040];
-/* -------------- */
-};
-
-/* Extended_Completion_Queue_Entry */
-
-struct arbelprm_extended_completion_queue_entry_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00020];
-/* -------------- */
-};
-
-/* */
-
-struct arbelprm_eq_cmd_doorbell_st { /* Little Endian */
- pseudo_bit_t reserved0[0x00020];
-/* -------------- */
-};
-
-/* 0 */
-
-struct arbelprm_arbel_prm_st { /* Little Endian */
- struct arbelprm_completion_queue_entry_st completion_queue_entry;/* Completion Queue Entry Format */
-/* -------------- */
- pseudo_bit_t reserved0[0x7ff00];
-/* -------------- */
- struct arbelprm_qp_ee_state_transitions_st qp_ee_state_transitions;/* QP/EE State Transitions Command Parameters */
-/* -------------- */
- pseudo_bit_t reserved1[0x7f000];
-/* -------------- */
- struct arbelprm_event_queue_entry_st event_queue_entry;/* Event Queue Entry */
-/* -------------- */
- pseudo_bit_t reserved2[0x7ff00];
-/* -------------- */
- struct arbelprm_completion_event_st completion_event;/* Event_data Field - Completion Event */
-/* -------------- */
- pseudo_bit_t reserved3[0x7ff40];
-/* -------------- */
- struct arbelprm_completion_queue_error_st completion_queue_error;/* Event_data Field - Completion Queue Error */
-/* -------------- */
- pseudo_bit_t reserved4[0x7ff40];
-/* -------------- */
- struct arbelprm_port_state_change_st port_state_change;/* Event_data Field - Port State Change */
-/* -------------- */
- pseudo_bit_t reserved5[0x7ff40];
-/* -------------- */
- struct arbelprm_wqe_segment_st wqe_segment;/* WQE segments format */
-/* -------------- */
- pseudo_bit_t reserved6[0x7f000];
-/* -------------- */
- struct arbelprm_page_fault_event_data_st page_fault_event_data;/* Event_data Field - Page Faults */
-/* -------------- */
- pseudo_bit_t reserved7[0x7ff40];
-/* -------------- */
- struct arbelprm_performance_monitor_event_st performance_monitor_event;/* Event Data Field - Performance Monitor */
-/* -------------- */
- pseudo_bit_t reserved8[0xfff20];
-/* -------------- */
- struct arbelprm_mt25208_type0_st mt25208_type0;/* InfiniHost-III-EX Type0 Configuration Header */
-/* -------------- */
- pseudo_bit_t reserved9[0x7f000];
-/* -------------- */
- struct arbelprm_qp_ee_event_st qp_ee_event;/* Event_data Field - QP/EE Events */
-/* -------------- */
- pseudo_bit_t reserved10[0x00040];
-/* -------------- */
- struct arbelprm_gpio_event_data_st gpio_event_data;
-/* -------------- */
- pseudo_bit_t reserved11[0x7fe40];
-/* -------------- */
- struct arbelprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */
-/* -------------- */
- pseudo_bit_t reserved12[0x7ff00];
-/* -------------- */
- struct arbelprm_queue_pair_ee_context_entry_st queue_pair_ee_context_entry;/* QP and EE Context Entry */
-/* -------------- */
- pseudo_bit_t reserved13[0x7fa00];
-/* -------------- */
- struct arbelprm_address_path_st address_path;/* Address Path */
-/* -------------- */
- pseudo_bit_t reserved14[0x7ff00];
-/* -------------- */
- struct arbelprm_completion_queue_context_st completion_queue_context;/* Completion Queue Context Table Entry */
-/* -------------- */
- pseudo_bit_t reserved15[0x7fe00];
-/* -------------- */
- struct arbelprm_mpt_st mpt; /* Memory Protection Table (MPT) Entry */
-/* -------------- */
- pseudo_bit_t reserved16[0x7fe00];
-/* -------------- */
- struct arbelprm_mtt_st mtt; /* Memory Translation Table (MTT) Entry */
-/* -------------- */
- pseudo_bit_t reserved17[0x7ffc0];
-/* -------------- */
- struct arbelprm_eqc_st eqc; /* Event Queue Context Table Entry */
-/* -------------- */
- pseudo_bit_t reserved18[0x7fe00];
-/* -------------- */
- struct arbelprm_performance_monitors_st performance_monitors;/* Performance Monitors */
-/* -------------- */
- pseudo_bit_t reserved19[0x7ff80];
-/* -------------- */
- struct arbelprm_hca_command_register_st hca_command_register;/* HCA Command Register (HCR) */
-/* -------------- */
- pseudo_bit_t reserved20[0xfff20];
-/* -------------- */
- struct arbelprm_init_hca_st init_hca;/* INIT_HCA & QUERY_HCA Parameters Block */
-/* -------------- */
- pseudo_bit_t reserved21[0x7f000];
-/* -------------- */
- struct arbelprm_qpcbaseaddr_st qpcbaseaddr;/* QPC/EEC/CQC/EQC/RDB Parameters */
-/* -------------- */
- pseudo_bit_t reserved22[0x7fc00];
-/* -------------- */
- struct arbelprm_udavtable_memory_parameters_st udavtable_memory_parameters;/* Memory Access Parameters for UD Address Vector Table */
-/* -------------- */
- pseudo_bit_t reserved23[0x7ffc0];
-/* -------------- */
- struct arbelprm_multicastparam_st multicastparam;/* Multicast Support Parameters */
-/* -------------- */
- pseudo_bit_t reserved24[0x7ff00];
-/* -------------- */
- struct arbelprm_tptparams_st tptparams;/* Translation and Protection Tables Parameters */
-/* -------------- */
- pseudo_bit_t reserved25[0x7ff00];
-/* -------------- */
- struct arbelprm_enable_lam_st enable_lam;/* ENABLE_LAM Parameters Block */
-/* -------------- */
- struct arbelprm_access_lam_st access_lam;
-/* -------------- */
- pseudo_bit_t reserved26[0x7f700];
-/* -------------- */
- struct arbelprm_dimminfo_st dimminfo;/* Logical DIMM Information */
-/* -------------- */
- pseudo_bit_t reserved27[0x7ff00];
-/* -------------- */
- struct arbelprm_query_fw_st query_fw;/* QUERY_FW Parameters Block */
-/* -------------- */
- pseudo_bit_t reserved28[0x7f800];
-/* -------------- */
- struct arbelprm_query_adapter_st query_adapter;/* QUERY_ADAPTER Parameters Block */
-/* -------------- */
- pseudo_bit_t reserved29[0x7f800];
-/* -------------- */
- struct arbelprm_query_dev_lim_st query_dev_lim;/* Query Device Limitations */
-/* -------------- */
- pseudo_bit_t reserved30[0x7f800];
-/* -------------- */
- struct arbelprm_uar_params_st uar_params;/* UAR Parameters */
-/* -------------- */
- pseudo_bit_t reserved31[0x7ff00];
-/* -------------- */
- struct arbelprm_init_ib_st init_ib; /* INIT_IB Parameters */
-/* -------------- */
- pseudo_bit_t reserved32[0x7f800];
-/* -------------- */
- struct arbelprm_mgm_entry_st mgm_entry;/* Multicast Group Member */
-/* -------------- */
- pseudo_bit_t reserved33[0x7fe00];
-/* -------------- */
- struct arbelprm_set_ib_st set_ib; /* SET_IB Parameters */
-/* -------------- */
- pseudo_bit_t reserved34[0x7fe00];
-/* -------------- */
- struct arbelprm_rd_send_doorbell_st rd_send_doorbell;/* RD-send doorbell */
-/* -------------- */
- pseudo_bit_t reserved35[0x7ff80];
-/* -------------- */
- struct arbelprm_send_doorbell_st send_doorbell;/* Send doorbell */
-/* -------------- */
- pseudo_bit_t reserved36[0x7ffc0];
-/* -------------- */
- struct arbelprm_receive_doorbell_st receive_doorbell;/* Receive doorbell */
-/* -------------- */
- pseudo_bit_t reserved37[0x7ffc0];
-/* -------------- */
- struct arbelprm_cq_cmd_doorbell_st cq_cmd_doorbell;/* CQ Doorbell */
-/* -------------- */
- pseudo_bit_t reserved38[0xfffc0];
-/* -------------- */
- struct arbelprm_uar_st uar; /* User Access Region */
-/* -------------- */
- pseudo_bit_t reserved39[0x7c000];
-/* -------------- */
- struct arbelprm_mgmqp_st mgmqp; /* Multicast Group Member QP */
-/* -------------- */
- pseudo_bit_t reserved40[0x7ffe0];
-/* -------------- */
- struct arbelprm_query_debug_msg_st query_debug_msg;/* Query Debug Message */
-/* -------------- */
- pseudo_bit_t reserved41[0x7f800];
-/* -------------- */
- struct arbelprm_mad_ifc_st mad_ifc; /* MAD_IFC Input Mailbox */
-/* -------------- */
- pseudo_bit_t reserved42[0x00900];
-/* -------------- */
- struct arbelprm_mad_ifc_input_modifier_st mad_ifc_input_modifier;/* MAD_IFC Input Modifier */
-/* -------------- */
- pseudo_bit_t reserved43[0x7e6e0];
-/* -------------- */
- struct arbelprm_resize_cq_st resize_cq;/* Resize CQ Input Mailbox */
-/* -------------- */
- pseudo_bit_t reserved44[0x7fe00];
-/* -------------- */
- struct arbelprm_completion_with_error_st completion_with_error;/* Completion with Error CQE */
-/* -------------- */
- pseudo_bit_t reserved45[0x7ff00];
-/* -------------- */
- struct arbelprm_hcr_completion_event_st hcr_completion_event;/* Event_data Field - HCR Completion Event */
-/* -------------- */
- pseudo_bit_t reserved46[0x7ff40];
-/* -------------- */
- struct arbelprm_transport_and_ci_error_counters_st transport_and_ci_error_counters;/* Transport and CI Error Counters */
-/* -------------- */
- pseudo_bit_t reserved47[0x7f000];
-/* -------------- */
- struct arbelprm_performance_counters_st performance_counters;/* Performance Counters */
-/* -------------- */
- pseudo_bit_t reserved48[0x9ff800];
-/* -------------- */
- struct arbelprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */
-/* -------------- */
- pseudo_bit_t reserved49[0x7ff00];
-/* -------------- */
- struct arbelprm_pbl_st pbl; /* Physical Buffer List */
-/* -------------- */
- pseudo_bit_t reserved50[0x7ff00];
-/* -------------- */
- struct arbelprm_srq_context_st srq_context;/* SRQ Context */
-/* -------------- */
- pseudo_bit_t reserved51[0x7fe80];
-/* -------------- */
- struct arbelprm_mod_stat_cfg_st mod_stat_cfg;/* MOD_STAT_CFG */
-/* -------------- */
- pseudo_bit_t reserved52[0x7f800];
-/* -------------- */
- struct arbelprm_virtual_physical_mapping_st virtual_physical_mapping;/* Virtual and Physical Mapping */
-/* -------------- */
- pseudo_bit_t reserved53[0x7ff80];
-/* -------------- */
- struct arbelprm_cq_ci_db_record_st cq_ci_db_record;/* CQ_CI_DB_Record */
-/* -------------- */
- pseudo_bit_t reserved54[0x7ffc0];
-/* -------------- */
- struct arbelprm_cq_arm_db_record_st cq_arm_db_record;/* CQ_ARM_DB_Record */
-/* -------------- */
- pseudo_bit_t reserved55[0x7ffc0];
-/* -------------- */
- struct arbelprm_qp_db_record_st qp_db_record;/* QP_DB_Record */
-/* -------------- */
- pseudo_bit_t reserved56[0x1fffc0];
-/* -------------- */
- struct arbelprm_configuration_registers_st configuration_registers;/* InfiniHost III EX Configuration Registers */
-/* -------------- */
- struct arbelprm_eq_set_ci_table_st eq_set_ci_table;/* EQ Set CI DBs Table */
-/* -------------- */
- pseudo_bit_t reserved57[0x01000];
-/* -------------- */
- struct arbelprm_eq_arm_db_region_st eq_arm_db_region;/* EQ Arm Doorbell Region */
-/* -------------- */
- pseudo_bit_t reserved58[0x00fc0];
-/* -------------- */
- struct arbelprm_clr_int_st clr_int; /* Clear Interrupt Register */
-/* -------------- */
- pseudo_bit_t reserved59[0xffcfc0];
-/* -------------- */
-};
-#endif /* H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H */
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-
-#ifndef __bit_ops_h__
-#define __bit_ops_h__
-
-typedef unsigned long MT_offset_t;
-typedef unsigned long MT_size_t;
-typedef unsigned char pseudo_bit_t;
-struct addr_64_st {
- __u32 addr_l;
- __u32 addr_h;
-};
-
-#define MT_BIT_OFFSET(object_struct,reg_path) \
- ((MT_offset_t) &( ((struct object_struct *)(0))-> reg_path ))
-
-#define MT_BIT_SIZE(object_struct,reg_path) \
- ((MT_size_t) sizeof( ((struct object_struct *)(0))-> reg_path ))
-
-#define MT_BIT_OFFSET_SIZE(object_struct,reg_path) \
- MT_BIT_OFFSET(object_struct,reg_path),MT_BIT_SIZE(object_struct,reg_path)
-
-#define MT_BYTE_OFFSET(object_struct,reg_path) \
- ((MT_offset_t) (MT_BIT_OFFSET(object_struct,reg_path)/8))
-
-#define MT_BYTE_SIZE(object_struct,reg_path) \
- ((MT_size_t) MT_BIT_SIZE(object_struct,reg_path)/8)
-
-#define MT_BYTE_OFFSET_SIZE(object_struct,reg_path) \
- MT_BYTE_OFFSET(object_struct,reg_path),MT_BYTE_SIZE(object_struct,reg_path)
-
-#define MT_STRUCT_SIZE(object_struct) (sizeof(struct object_struct) >> 3)
-
-/*****************************************************************************************
- * Bit manipulation macros
- *****************************************************************************************/
-
-/* MASK generate a bit mask S bits width */
-#define MASK32(S) ( ((__u32) ~0L) >> (32-(S)) )
-
-/*
- * BITS generate a bit mask with bits O+S..O set (assumes 32 bit integer).
- * numbering bits as following: 31........................76543210
- */
-#define BITS32(O,S) ( MASK32(S) << (O) )
-
-/*
- * MT_EXTRACT32 macro extracts S bits from (__u32)W with offset O
- * and shifts them O places to the right (right justifies the field extracted).
- */
-#define MT_EXTRACT32(W,O,S) ( ((W)>>(O)) & MASK32(S) )
-
-/*
- * MT_INSERT32 macro inserts S bits with offset O from field F into word W (__u32)
- */
-#define MT_INSERT32(W,F,O,S) ((W)= ( ( (W) & (~BITS32(O,S)) ) | (((F) & MASK32(S))<<(O)) ))
-
-/*
- * MT_EXTRACT_ARRAY32 macro is similar to EXTRACT but works on an array of (__u32),
- * thus offset may be larger than 32 (but not size).
- */
-#define MT_EXTRACT_ARRAY32(A,O,S) MT_EXTRACT32(((__u32*)A)[O >> 5],(O & MASK32(5)),S)
-
-/*
- * MT_INSERT_ARRAY32 macro is similar to INSERT but works on an array of (__u32),
- * thus offset may be larger than 32 (but not size).
- */
-#define MT_INSERT_ARRAY32(A,F,O,S) MT_INSERT32(((__u32*)A)[O >> 5],F,(O & MASK32(5)),S)
-
-#define INS_FLD(src, a, st, fld) MT_INSERT_ARRAY32(a, src, MT_BIT_OFFSET(st, fld), MT_BIT_SIZE(st, fld))
-
-#define EX_FLD(a, st, fld) MT_EXTRACT_ARRAY32(a, MT_BIT_OFFSET(st, fld), MT_BIT_SIZE(st, fld))
-
-/* return the address of the dword holding the field
-
- buf = pointer to buffer where to place the value
- st = struct describing the buffer
- fld = field in the struct where to insert the value */
-
-#define FLD_DW_ADDR(buf, st, fld) ((__u32 *)((__u32 *)(buf)+(((__u32)(&(((struct st *)(0))->fld))) >> 5)))
-
-/*
- val = value to insert
- buf = pointer to buffer where to place the value
- st = struct describing the buffer
- fld = field in the struct where to insert the value */
-
-#define INS_FLD_TO_BE(val, buf, st, fld) \
- do { \
- *FLD_DW_ADDR(buf, st, fld) = be32_to_cpu(*FLD_DW_ADDR(buf, st, fld)); \
- INS_FLD(val, buf, st, fld); \
- *FLD_DW_ADDR(buf, st, fld) = cpu_to_be32(*FLD_DW_ADDR(buf, st, fld)); \
- } \
- while(0)
-
-#define EX_FLD_FROM_BE(buf, st, fld, type) \
-({ \
- type field; \
- \
- *FLD_DW_ADDR(buf, st, fld) = be32_to_cpu(*FLD_DW_ADDR(buf, st, fld)); \
- field= EX_FLD(buf, st, fld); \
- *FLD_DW_ADDR(buf, st, fld) = cpu_to_be32(*FLD_DW_ADDR(buf, st, fld)); \
- \
- field; \
-})
-
-#endif /* __bit_ops_h__ */
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-
-#ifndef __cmdif_h_
-#define __cmdif_h_
-
-#include "ib_mad.h"
-
-static int cmd_init_hca(__u32 * inprm, __u32 in_prm_size);
-static int cmd_close_hca(int panic);
-static int cmd_sw2hw_eq(__u32 inprm_sz);
-static int cmd_hw2sw_eq(__u8 eqn);
-static int cmd_map_eq(__u8 eqn, __u32 mask, int map);
-static int cmd_sw2hw_mpt(__u32 * lkey, __u32 in_key, __u32 * inprm,
- __u32 inprm_sz);
-static int cmd_hw2sw_mpt(__u32 key);
-static int cmd_init_ib(__u32 port, __u32 * inprm, __u32 inprm_sz);
-static int cmd_close_ib(__u32 port);
-static int cmd_sw2hw_cq(__u32 cqn, __u32 * inprm, __u32 inprm_sz);
-static int cmd_hw2sw_cq(__u32 cqn);
-static int cmd_rst2init_qpee(__u32 qpn, __u32 * inprm, __u32 inprm_sz);
-static int cmd_init2rtr_qpee(__u32 qpn, __u32 * inprm, __u32 inprm_sz);
-static int cmd_rtr2rts_qpee(__u32 qpn, __u32 * inprm, __u32 inprm_sz);
-static int cmd_2rst_qpee(__u32 qpn);
-static int cmd_2err_qpee(__u32 qpn);
-static int cmd_post_doorbell(void *inprm, __u32 offset);
-static int cmd_mad_ifc(void *inprm, struct ib_mad_st *mad, __u8 port);
-static int cmd_write_mgm( /*struct mg_member_layout_st */ void *mg,
- __u16 index);
-static int cmd_mgid_hash(__u8 * gid, __u16 * mgid_hash_p);
-
-#endif /* __cmdif_h_ */
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-
-#include "cmdif.h"
-#include "cmdif_comm.h"
-#include "cmdif_priv.h"
-
-static int cmdif_is_free(int *is_free)
-{
- int rc;
- __u32 result;
-
- rc = gw_read_cr(HCR_OFFSET_GO, &result);
- if (rc) {
- eprintf("");
- return rc;
- }
- *is_free = (result & 0x800000) == 0;
-
- return 0;
-}
-
-static void edit_hcr(command_fields_t * cmd_prms, __u32 * buf)
-{
- unsigned int i;
-
- switch (cmd_prms->in_trans) {
- case TRANS_NA:
- /* note! since these are zeroes I do not bother to deal with endianess */
- buf[0] = 0;
- buf[1] = 0;
- break;
-
- case TRANS_IMMEDIATE:
- buf[0] = cmd_prms->in_param[0];
- buf[1] = cmd_prms->in_param[1];
- break;
-
- case TRANS_MAILBOX:
- buf[0] = 0;
- buf[1] = virt_to_bus(cmd_prms->in_param);
-
- for (i = 0; i < cmd_prms->in_param_size; i += 4)
- cmd_prms->in_param[i >> 2] =
- cpu_to_be32(cmd_prms->in_param[i >> 2]);
- break;
- }
-
- buf[2] = cmd_prms->input_modifier;
-
- switch (cmd_prms->out_trans) {
- case TRANS_NA:
- /* note! since these are zeroes I do not bother to deal with endianess */
- buf[3] = 0;
- buf[4] = 0;
- break;
-
- case TRANS_IMMEDIATE:
- break;
- case TRANS_MAILBOX:
- buf[3] = 0;
- buf[4] = virt_to_bus(cmd_prms->out_param);
- break;
- }
-
- buf[5] = 0; /* token is always 0 */
- buf[6] = cmd_prms->opcode | /* opcode */
- 0x800000 | /* go bit */
- ((cmd_prms->opcode_modifier & 0xf) << 12); /* opcode modifier
-*/ }
-
-static int wait_cmdif_free(void)
-{
- int ret, is_free;
- unsigned int i, relax_time = 1, max_time = 5000;
-
- /* wait until go bit is free */
- for (i = 0; i < max_time; i += relax_time) {
- ret = cmdif_is_free(&is_free);
- if (ret)
- return ret;
- if (is_free)
- break;
- mdelay(relax_time);
- }
- if (i >= max_time)
- return -1;
- return 0;
-}
-
-static XHH_cmd_status_t cmd_invoke(command_fields_t * cmd_prms)
-{
- int ret, is_free, i;
- __u32 hcr[7], data;
- __u8 status;
-
- /* check if go bit is free */
- ret = cmdif_is_free(&is_free);
- if (ret) {
- eprintf("");
- return -1;
- }
-
- __asm__ __volatile__("":::"memory");
- /* it must be free */
- if (!is_free) {
- eprintf("");
- return -1;
- }
- __asm__ __volatile__("":::"memory");
- edit_hcr(cmd_prms, hcr);
- __asm__ __volatile__("":::"memory");
-
- for (i = 0; i < 7; ++i) {
- ret = gw_write_cr(HCR_BASE + i * 4, hcr[i]);
- if (ret) {
- eprintf("");
- return -1;
- }
- }
-
- __asm__ __volatile__("":::"memory");
- /* wait for completion */
- ret = wait_cmdif_free();
- if (ret) {
- eprintf("");
- return -1;
- }
-
- __asm__ __volatile__("":::"memory");
- ret = gw_read_cr(HCR_OFFSET_STATUS, &data);
- if (ret) {
- eprintf("");
- return -1;
- }
-
- status = data >> 24;
-
- if (status) {
- tprintf("status=0x%x", status);
- return status;
- }
-
- if (cmd_prms->out_trans == TRANS_MAILBOX)
- be_to_cpu_buf(cmd_prms->out_param, cmd_prms->out_param_size);
- else if (cmd_prms->out_trans == TRANS_IMMEDIATE) {
- if (gw_read_cr(HCR_OFFSET_OUTPRM_H, &cmd_prms->out_param[0]))
- return -1;
- if (gw_read_cr(HCR_OFFSET_OUTPRM_L, &cmd_prms->out_param[1]))
- return -1;
- }
-
- return 0;
-}
-
-/*************************************************
- commands
-*************************************************/
-
-/*
- * cmd_close_hca
- */
-static int cmd_close_hca(int panic)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.opcode = XDEV_CMD_CLOSE_HCA;
- cmd_desc.opcode_modifier= panic;
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_init_hca
- */
-static int cmd_init_hca(__u32 * inprm, __u32 in_prm_size)
-{
- int rc;
-
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.in_trans = TRANS_MAILBOX;
- cmd_desc.opcode = XDEV_CMD_INIT_HCA;
- cmd_desc.in_param = inprm;
- cmd_desc.in_param_size = in_prm_size;
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_sw2hw_eq
- */
-static int cmd_sw2hw_eq(__u32 inprm_sz)
-{
- int rc;
- command_fields_t cmd_desc;
- void *inprm;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
-
- inprm = get_inprm_buf();
- cmd_desc.in_trans = TRANS_MAILBOX;
- cmd_desc.opcode = XDEV_CMD_SW2HW_EQ;
- cmd_desc.in_param = inprm;
- cmd_desc.in_param_size = inprm_sz;
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_hw2sw_eq
- */
-static int cmd_hw2sw_eq(__u8 eqn)
-{
- int rc;
- command_fields_t cmd_desc;
- void *outprm;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
-
- outprm = get_outprm_buf();
- cmd_desc.opcode = XDEV_CMD_HW2SW_EQ;
- cmd_desc.input_modifier = eqn;
- cmd_desc.out_trans = TRANS_MAILBOX;
- cmd_desc.out_param = outprm;
- cmd_desc.out_param_size = 0x40;
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_map_eq
- */
-static int cmd_map_eq(__u8 eqn, __u32 mask, int map)
-{
- int rc;
- command_fields_t cmd_desc;
- __u32 *inprm;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
-
- inprm = get_inprm_buf();
-
- inprm[1] = mask;
- inprm[0] = 0;
-
- cmd_desc.opcode = XDEV_CMD_MAP_EQ;
- cmd_desc.in_trans = TRANS_IMMEDIATE;
- cmd_desc.in_param = inprm;
- cmd_desc.input_modifier = ((map ? 0 : 1) << 31) | eqn;
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_sw2hw_mpt
- */
-static int cmd_sw2hw_mpt(__u32 * lkey, __u32 in_key, __u32 * inprm,
- __u32 inprm_sz)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.in_trans = TRANS_MAILBOX;
- cmd_desc.opcode = XDEV_CMD_SW2HW_MPT;
- cmd_desc.input_modifier = in_key & MKEY_IDX_MASK; /* only one MR for the whole driver */
- cmd_desc.in_param = inprm;
- cmd_desc.in_param_size = inprm_sz;
-
- rc = cmd_invoke(&cmd_desc);
- if (!rc)
- *lkey = in_key;
-
- return rc;
-}
-
-/*
- * cmd_hw2sw_mpt
- */
-static int cmd_hw2sw_mpt(__u32 key)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.opcode = XDEV_CMD_HW2SW_MPT;
- cmd_desc.input_modifier = key & MKEY_IDX_MASK;
- cmd_desc.opcode_modifier = 1;
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_init_ib
- */
-static int cmd_init_ib(__u32 port, __u32 * inprm, __u32 inprm_sz)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.opcode = XDEV_CMD_INIT_IB;
- cmd_desc.input_modifier = port;
- cmd_desc.in_trans = TRANS_MAILBOX;
- cmd_desc.in_param = inprm;
- cmd_desc.in_param_size = inprm_sz;
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_close_ib
- */
-static int cmd_close_ib(__u32 port)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.opcode = XDEV_CMD_CLOSE_IB;
- cmd_desc.input_modifier = port;
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_sw2hw_cq
- */
-static int cmd_sw2hw_cq(__u32 cqn, __u32 * inprm, __u32 inprm_sz)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.opcode = XDEV_CMD_SW2HW_CQ;
- cmd_desc.in_trans = TRANS_MAILBOX;
- cmd_desc.in_param = inprm;
- cmd_desc.in_param_size = inprm_sz;
- cmd_desc.input_modifier = cqn;
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_hw2sw_cq
- */
-static int cmd_hw2sw_cq(__u32 cqn)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.opcode = XDEV_CMD_HW2SW_CQ;
- cmd_desc.input_modifier = cqn;
- cmd_desc.out_trans = TRANS_MAILBOX;
- cmd_desc.out_param = get_outprm_buf();
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_rst2init_qpee
- */
-static int cmd_rst2init_qpee(__u32 qpn, __u32 * inprm, __u32 inprm_sz)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.opcode = XDEV_CMD_RST2INIT_QPEE;
- cmd_desc.in_trans = TRANS_MAILBOX;
- cmd_desc.in_param = inprm;
- cmd_desc.in_param_size = inprm_sz;
- cmd_desc.input_modifier = qpn;
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_init2rtr_qpee
- */
-static int cmd_init2rtr_qpee(__u32 qpn, __u32 * inprm, __u32 inprm_sz)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.opcode = XDEV_CMD_INIT2RTR_QPEE;
- cmd_desc.in_trans = TRANS_MAILBOX;
- cmd_desc.in_param = inprm;
- cmd_desc.in_param_size = inprm_sz;
- cmd_desc.input_modifier = qpn;;
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_rtr2rts_qpee
- */
-static int cmd_rtr2rts_qpee(__u32 qpn, __u32 * inprm, __u32 inprm_sz)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.opcode = XDEV_CMD_RTR2RTS_QPEE;
- cmd_desc.in_trans = TRANS_MAILBOX;
- cmd_desc.in_param = inprm;
- cmd_desc.in_param_size = inprm_sz;
- cmd_desc.input_modifier = qpn;
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_2rst_qpee
- */
-static int cmd_2rst_qpee(__u32 qpn)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.opcode = XDEV_CMD_ERR2RST_QPEE;
- cmd_desc.opcode_modifier = 0;
- cmd_desc.input_modifier = qpn;
- cmd_desc.out_trans = TRANS_MAILBOX;
- cmd_desc.out_param = get_outprm_buf();
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_2err_qpee
- */
-static int cmd_2err_qpee(__u32 qpn)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.opcode = XDEV_CMD_2ERR_QPEE;
- cmd_desc.input_modifier = qpn;
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_post_doorbell
- */
-static int cmd_post_doorbell(void *inprm, __u32 offset)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.opcode = XDEV_CMD_POST_DOORBELL;
- cmd_desc.in_trans = TRANS_IMMEDIATE;
- cmd_desc.in_param = inprm;
- cmd_desc.input_modifier = offset;
- if (0) {
- rc = cmd_invoke(&cmd_desc);
- } else {
- dev_post_dbell(inprm, offset);
- rc = 0;
- }
-
- return rc;
-}
-
-static int cmd_mad_ifc(void *inprm, struct ib_mad_st *mad, __u8 port)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.opcode = XDEV_CMD_MAD_IFC;
- cmd_desc.opcode_modifier = 1; /* no mkey/bkey validation */
- cmd_desc.input_modifier = port;
- cmd_desc.in_trans = TRANS_MAILBOX;
- cmd_desc.in_param_size = 256;
- cmd_desc.in_param = (__u32 *) inprm;
- cmd_desc.out_trans = TRANS_MAILBOX;
- cmd_desc.out_param = (__u32 *) mad;
- cmd_desc.out_param_size = 256;
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-static int cmd_mgid_hash(__u8 * gid, __u16 * mgid_hash_p)
-{
- int rc;
- command_fields_t cmd_desc;
- __u16 result[2];
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
-
- cmd_desc.opcode = XDEV_CMD_MGID_HASH;
- cmd_desc.in_trans = TRANS_MAILBOX;
- cmd_desc.in_param = (__u32 *) gid;
- cmd_desc.in_param_size = 16;
- cmd_desc.out_trans = TRANS_IMMEDIATE;
-
- rc = cmd_invoke(&cmd_desc);
- if (!rc) {
- rc = gw_read_cr(HCR_BASE + 16, (__u32 *) result);
- if (!rc) {
- *mgid_hash_p = result[0];
- }
- }
-
- return rc;
-}
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-
-#ifndef __cmdif_comm_h__
-#define __cmdif_comm_h__
-
- /* initialization and general commands */
-#define XDEV_CMD_INIT_HCA 0x7
-#define XDEV_CMD_CLOSE_HCA 0x8
-#define XDEV_CMD_INIT_IB 0x9
-#define XDEV_CMD_CLOSE_IB 0xa
-
- /* TPT commands */
-#define XDEV_CMD_SW2HW_MPT 0xd
-#define XDEV_CMD_HW2SW_MPT 0xf
-
- /* EQ commands */
-#define XDEV_CMD_MAP_EQ 0x12
-#define XDEV_CMD_SW2HW_EQ 0x13
-#define XDEV_CMD_HW2SW_EQ 0x14
-
- /* CQ commands */
-#define XDEV_CMD_SW2HW_CQ 0x16
-#define XDEV_CMD_HW2SW_CQ 0x17
-
- /* QP/EE commands */
-#define XDEV_CMD_RST2INIT_QPEE 0x19
-#define XDEV_CMD_INIT2RTR_QPEE 0x1a
-#define XDEV_CMD_RTR2RTS_QPEE 0x1b
-#define XDEV_CMD_2ERR_QPEE 0x1e
-#define XDEV_CMD_ERR2RST_QPEE 0x21
-
- /* special QPs and management commands */
-#define XDEV_CMD_MAD_IFC 0x24
-
- /* multicast commands */
-#define XDEV_CMD_READ_MGM 0x25
-#define XDEV_CMD_MGID_HASH 0x27
-
-#define XDEV_CMD_POST_DOORBELL 0x41
-
-#endif /* __cmdif_comm_h__ */
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-#include "cmdif.h"
-#include "cmdif_priv.h"
-#include "mt23108.h"
-
-/*
- * cmd_sys_en
- */
-static int cmd_sys_en(void)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.opcode = TAVOR_CMD_SYS_EN;
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_sys_dis
- */
-static int cmd_sys_dis(void)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.in_trans = TRANS_NA;
- cmd_desc.out_trans = TRANS_NA;
- cmd_desc.opcode = TAVOR_CMD_SYS_DIS;
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_query_dev_lim
- */
-static int cmd_query_dev_lim(struct dev_lim_st *dev_lim_p)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
-
- cmd_desc.opcode = TAVOR_CMD_QUERY_DEV_LIM;
- cmd_desc.out_trans = TRANS_MAILBOX;
- cmd_desc.out_param = get_outprm_buf();
- cmd_desc.out_param_size = MT_STRUCT_SIZE(tavorprm_query_dev_lim_st);
-
- rc = cmd_invoke(&cmd_desc);
- if (!rc) {
- dev_lim_p->log2_rsvd_qps =
- EX_FLD(cmd_desc.out_param, tavorprm_query_dev_lim_st,
- log2_rsvd_qps);
- dev_lim_p->qpc_entry_sz =
- EX_FLD(cmd_desc.out_param, tavorprm_query_dev_lim_st,
- qpc_entry_sz);
-
- dev_lim_p->log2_rsvd_srqs =
- EX_FLD(cmd_desc.out_param, tavorprm_query_dev_lim_st,
- log2_rsvd_srqs);
- dev_lim_p->srq_entry_sz =
- EX_FLD(cmd_desc.out_param, tavorprm_query_dev_lim_st,
- srq_entry_sz);
-
- dev_lim_p->log2_rsvd_ees =
- EX_FLD(cmd_desc.out_param, tavorprm_query_dev_lim_st,
- log2_rsvd_ees);
- dev_lim_p->eec_entry_sz =
- EX_FLD(cmd_desc.out_param, tavorprm_query_dev_lim_st,
- eec_entry_sz);
-
- dev_lim_p->log2_rsvd_cqs =
- EX_FLD(cmd_desc.out_param, tavorprm_query_dev_lim_st,
- log2_rsvd_cqs);
- dev_lim_p->cqc_entry_sz =
- EX_FLD(cmd_desc.out_param, tavorprm_query_dev_lim_st,
- cqc_entry_sz);
-
- dev_lim_p->log2_rsvd_mtts =
- EX_FLD(cmd_desc.out_param, tavorprm_query_dev_lim_st,
- log2_rsvd_mtts);
- dev_lim_p->mtt_entry_sz = 64; /* segment size is set to zero in init_hca */
-
- dev_lim_p->log2_rsvd_mrws =
- EX_FLD(cmd_desc.out_param, tavorprm_query_dev_lim_st,
- log2_rsvd_mrws);
- dev_lim_p->mpt_entry_sz = MT_STRUCT_SIZE(tavorprm_mpt_st);
-
- dev_lim_p->eqc_entry_sz =
- EX_FLD(cmd_desc.out_param, tavorprm_query_dev_lim_st,
- eqc_entry_sz);
- }
-
- return rc;
-}
-
-/*
- * cmd_write_mgm
- */
-static int cmd_write_mgm(void *mg, __u16 index)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.opcode = TAVOR_CMD_WRITE_MGM;
- cmd_desc.in_trans = TRANS_MAILBOX;
- cmd_desc.in_param_size = MT_STRUCT_SIZE(tavorprm_mgm_entry_st);
- cmd_desc.in_param = (__u32 *) mg;
- cmd_desc.input_modifier = index;
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_mod_stat_cfg
- */
-static int cmd_mod_stat_cfg(void *cfg)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.opcode = TAVOR_CMD_MOD_STAT_CFG;
- cmd_desc.in_trans = TRANS_MAILBOX;
- cmd_desc.in_param_size = MT_STRUCT_SIZE(tavorprm_mod_stat_cfg_st);
- cmd_desc.in_param = (__u32 *) cfg;
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-
-/*
- * cmd_query_fw
- */
-static int cmd_query_fw(struct query_fw_st *qfw)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
-
- cmd_desc.opcode = TAVOR_CMD_QUERY_FW;
- cmd_desc.out_trans = TRANS_MAILBOX;
- cmd_desc.out_param = get_outprm_buf();
- cmd_desc.out_param_size = MT_STRUCT_SIZE(tavorprm_query_fw_st);
-
- rc = cmd_invoke(&cmd_desc);
- if (!rc) {
- qfw->fw_rev_major =
- EX_FLD(cmd_desc.out_param, tavorprm_query_fw_st, fw_rev_major);
- qfw->fw_rev_minor =
- EX_FLD(cmd_desc.out_param, tavorprm_query_fw_st, fw_rev_minor);
- qfw->fw_rev_subminor =
- EX_FLD(cmd_desc.out_param, tavorprm_query_fw_st, fw_rev_subminor);
-
- qfw->error_buf_start_h =
- EX_FLD(cmd_desc.out_param, tavorprm_query_fw_st, error_buf_start_h);
- qfw->error_buf_start_l =
- EX_FLD(cmd_desc.out_param, tavorprm_query_fw_st, error_buf_start_l);
- qfw->error_buf_size =
- EX_FLD(cmd_desc.out_param, tavorprm_query_fw_st, error_buf_size);
- }
-
- return rc;
-}
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-#include "cmdif.h"
-#include "cmdif_priv.h"
-#include "mt25218.h"
-
-/*
- * cmd_sys_dis
- */
-static int cmd_sys_dis(void)
-{
- return 0;
-}
-
-/*
- * cmd_write_mgm
- */
-static int cmd_write_mgm(void *mg, __u16 index)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.opcode = MEMFREE_CMD_WRITE_MGM;
- cmd_desc.in_trans = TRANS_MAILBOX;
- cmd_desc.in_param_size = MT_STRUCT_SIZE(arbelprm_mgm_entry_st);
- cmd_desc.in_param = (__u32 *) mg;
- cmd_desc.input_modifier = index;
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_mod_stat_cfg
- */
-static int cmd_mod_stat_cfg(void)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
- cmd_desc.opcode = MEMFREE_CMD_MOD_STAT_CFG;
- cmd_desc.in_trans = TRANS_MAILBOX;
- cmd_desc.in_param_size = MT_STRUCT_SIZE(arbelprm_mod_stat_cfg_st);
- cmd_desc.in_param = get_inprm_buf();
- memset(cmd_desc.in_param, 0, cmd_desc.in_param_size);
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_query_fw
- */
-static int cmd_query_fw(struct query_fw_st *qfw)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
-
- cmd_desc.opcode = MEMFREE_CMD_QUERY_FW;
- cmd_desc.out_trans = TRANS_MAILBOX;
- cmd_desc.out_param = get_outprm_buf();
- cmd_desc.out_param_size = MT_STRUCT_SIZE(arbelprm_query_fw_st);
-
- rc = cmd_invoke(&cmd_desc);
- if (!rc) {
- qfw->fw_rev_major =
- EX_FLD(cmd_desc.out_param, arbelprm_query_fw_st, fw_rev_major);
- qfw->fw_rev_minor =
- EX_FLD(cmd_desc.out_param, arbelprm_query_fw_st, fw_rev_minor);
- qfw->fw_rev_subminor =
- EX_FLD(cmd_desc.out_param, arbelprm_query_fw_st, fw_rev_subminor);
-
- qfw->error_buf_start_h =
- EX_FLD(cmd_desc.out_param, arbelprm_query_fw_st, error_buf_start_h);
- qfw->error_buf_start_l =
- EX_FLD(cmd_desc.out_param, arbelprm_query_fw_st, error_buf_start_l);
- qfw->error_buf_size =
- EX_FLD(cmd_desc.out_param, arbelprm_query_fw_st, error_buf_size);
-
- qfw->fw_pages =
- EX_FLD(cmd_desc.out_param, arbelprm_query_fw_st, fw_pages);
- qfw->eq_ci_table.addr_h =
- EX_FLD(cmd_desc.out_param, arbelprm_query_fw_st,
- eq_set_ci_base_addr_h);
- qfw->eq_ci_table.addr_l =
- EX_FLD(cmd_desc.out_param, arbelprm_query_fw_st,
- eq_set_ci_base_addr_l);
- qfw->clear_int_addr.addr_h =
- EX_FLD(cmd_desc.out_param, arbelprm_query_fw_st,
- clr_int_base_addr_h);
- qfw->clear_int_addr.addr_l =
- EX_FLD(cmd_desc.out_param, arbelprm_query_fw_st,
- clr_int_base_addr_l);
- }
-
- return rc;
-}
-
-/*
- * cmd_query_adapter
- */
-static int cmd_query_adapter(struct query_adapter_st *qa)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
-
- cmd_desc.opcode = MEMFREE_CMD_QUERY_ADAPTER;
- cmd_desc.out_trans = TRANS_MAILBOX;
- cmd_desc.out_param = get_outprm_buf();
- cmd_desc.out_param_size = MT_STRUCT_SIZE(arbelprm_query_adapter_st);
-
- rc = cmd_invoke(&cmd_desc);
- if (!rc) {
- qa->intapin =
- EX_FLD(cmd_desc.out_param, arbelprm_query_adapter_st,
- intapin);
- }
-
- return rc;
-}
-
-/*
- * cmd_enable_lam
- */
-static int cmd_enable_lam(void)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
-
- cmd_desc.opcode = MEMFREE_CMD_ENABLE_LAM;
- cmd_desc.opcode_modifier = 1; /* zero locally attached memory */
- cmd_desc.input_modifier = 0; /* disable fast refresh */
- cmd_desc.out_trans = TRANS_MAILBOX;
- cmd_desc.out_param = get_outprm_buf();
- cmd_desc.out_param_size = MT_STRUCT_SIZE(arbelprm_enable_lam_st);
-
- rc = cmd_invoke(&cmd_desc);
- if (rc) {
- }
-
- return rc;
-}
-
-/*
- * cmd_map_fa
- */
-static int cmd_map_fa(struct map_icm_st *map_fa_p)
-{
- int rc;
- command_fields_t cmd_desc;
- unsigned int in_param_size, i;
- unsigned long off;
-
- if (map_fa_p->num_vpm > MAX_VPM_PER_CALL) {
- return -1;
- }
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
-
- cmd_desc.opcode = MEMFREE_CMD_MAP_FA;
- cmd_desc.input_modifier = map_fa_p->num_vpm;
- cmd_desc.in_trans = TRANS_MAILBOX;
- cmd_desc.in_param = get_inprm_buf();
- in_param_size =
- MT_STRUCT_SIZE(arbelprm_virtual_physical_mapping_st) *
- map_fa_p->num_vpm;
- cmd_desc.in_param_size = in_param_size;
- memset(cmd_desc.in_param, 0, in_param_size);
-
- for (i = 0; i < map_fa_p->num_vpm; ++i) {
- off = (unsigned long)(cmd_desc.in_param) +
- MT_STRUCT_SIZE(arbelprm_virtual_physical_mapping_st) * i;
- INS_FLD(map_fa_p->vpm_arr[i].va_h, off,
- arbelprm_virtual_physical_mapping_st, va_h);
- INS_FLD(map_fa_p->vpm_arr[i].va_l >> 12, off,
- arbelprm_virtual_physical_mapping_st, va_l);
- INS_FLD(map_fa_p->vpm_arr[i].pa_h, off,
- arbelprm_virtual_physical_mapping_st, pa_h);
- INS_FLD(map_fa_p->vpm_arr[i].pa_l >> 12, off,
- arbelprm_virtual_physical_mapping_st, pa_l);
- INS_FLD(map_fa_p->vpm_arr[i].log2_size, off,
- arbelprm_virtual_physical_mapping_st, log2size);
- }
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_unmap_fa
- */
-static int cmd_unmap_fa(void)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
-
- cmd_desc.opcode = MEMFREE_CMD_UNMAP_FA;
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_run_fw
- */
-static int cmd_run_fw(void)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
-
- cmd_desc.opcode = MEMFREE_CMD_RUN_FW;
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_set_icm_size
- */
-static int cmd_set_icm_size(__u32 icm_size, __u32 * aux_pages_p)
-{
- int rc;
- command_fields_t cmd_desc;
- __u32 iprm[2], oprm[2];
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
-
- cmd_desc.opcode = MEMFREE_CMD_SET_ICM_SIZE;
-
- iprm[1] = icm_size;
- iprm[0] = 0;
- cmd_desc.in_trans = TRANS_IMMEDIATE;
- cmd_desc.in_param = iprm;
- cmd_desc.out_trans = TRANS_IMMEDIATE;
- cmd_desc.out_param = oprm;
- rc = cmd_invoke(&cmd_desc);
- if (!rc) {
- if (oprm[0]) {
- /* too many pages required */
- return -1;
- }
- *aux_pages_p = oprm[1];
- }
-
- return rc;
-}
-
-/*
- * cmd_map_icm_aux
- */
-static int cmd_map_icm_aux(struct map_icm_st *map_icm_aux_p)
-{
- int rc;
- command_fields_t cmd_desc;
- unsigned int in_param_size, i;
- unsigned long off;
-
- if (map_icm_aux_p->num_vpm > MAX_VPM_PER_CALL) {
- return -1;
- }
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
-
- cmd_desc.opcode = MEMFREE_CMD_MAP_ICM_AUX;
- cmd_desc.input_modifier = map_icm_aux_p->num_vpm;
- cmd_desc.in_trans = TRANS_MAILBOX;
- cmd_desc.in_param = get_inprm_buf();
- in_param_size =
- MT_STRUCT_SIZE(arbelprm_virtual_physical_mapping_st) *
- map_icm_aux_p->num_vpm;
- cmd_desc.in_param_size = in_param_size;
- memset(cmd_desc.in_param, 0, in_param_size);
-
- for (i = 0; i < map_icm_aux_p->num_vpm; ++i) {
- off = (unsigned long)(cmd_desc.in_param) +
- MT_STRUCT_SIZE(arbelprm_virtual_physical_mapping_st) * i;
- INS_FLD(map_icm_aux_p->vpm_arr[i].va_h, off,
- arbelprm_virtual_physical_mapping_st, va_h);
- INS_FLD(map_icm_aux_p->vpm_arr[i].va_l >> 12, off,
- arbelprm_virtual_physical_mapping_st, va_l);
- INS_FLD(map_icm_aux_p->vpm_arr[i].pa_h, off,
- arbelprm_virtual_physical_mapping_st, pa_h);
- INS_FLD(map_icm_aux_p->vpm_arr[i].pa_l >> 12, off,
- arbelprm_virtual_physical_mapping_st, pa_l);
- INS_FLD(map_icm_aux_p->vpm_arr[i].log2_size, off,
- arbelprm_virtual_physical_mapping_st, log2size);
- }
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_map_icm
- */
-static int cmd_map_icm(struct map_icm_st *map_icm_p)
-{
- int rc;
- command_fields_t cmd_desc;
- unsigned int in_param_size, i;
- unsigned long off;
-
- if (map_icm_p->num_vpm > MAX_VPM_PER_CALL) {
- return -1;
- }
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
-
- cmd_desc.opcode = MEMFREE_CMD_MAP_ICM;
- cmd_desc.input_modifier = map_icm_p->num_vpm;
- cmd_desc.in_trans = TRANS_MAILBOX;
- cmd_desc.in_param = get_inprm_buf();
- in_param_size =
- MT_STRUCT_SIZE(arbelprm_virtual_physical_mapping_st) *
- map_icm_p->num_vpm;
- cmd_desc.in_param_size = in_param_size;
- memset(cmd_desc.in_param, 0, in_param_size);
-
- for (i = 0; i < map_icm_p->num_vpm; ++i) {
- off = (unsigned long)(cmd_desc.in_param) +
- MT_STRUCT_SIZE(arbelprm_virtual_physical_mapping_st) * i;
- INS_FLD(map_icm_p->vpm_arr[i].va_h, off,
- arbelprm_virtual_physical_mapping_st, va_h);
- INS_FLD(map_icm_p->vpm_arr[i].va_l >> 12, off,
- arbelprm_virtual_physical_mapping_st, va_l);
- INS_FLD(map_icm_p->vpm_arr[i].pa_h, off,
- arbelprm_virtual_physical_mapping_st, pa_h);
- INS_FLD(map_icm_p->vpm_arr[i].pa_l >> 12, off,
- arbelprm_virtual_physical_mapping_st, pa_l);
- INS_FLD(map_icm_p->vpm_arr[i].log2_size, off,
- arbelprm_virtual_physical_mapping_st, log2size);
- }
-
- rc = cmd_invoke(&cmd_desc);
-
- return rc;
-}
-
-/*
- * cmd_query_dev_lim
- */
-static int cmd_query_dev_lim(struct dev_lim_st *dev_lim_p)
-{
- int rc;
- command_fields_t cmd_desc;
-
- memset(&cmd_desc, 0, sizeof cmd_desc);
-
- cmd_desc.opcode = MEMFREE_CMD_QUERY_DEV_LIM;
- cmd_desc.out_trans = TRANS_MAILBOX;
- cmd_desc.out_param = get_outprm_buf();
- cmd_desc.out_param_size = MT_STRUCT_SIZE(arbelprm_query_dev_lim_st);
-
- rc = cmd_invoke(&cmd_desc);
- if (!rc) {
- dev_lim_p->log2_rsvd_qps =
- EX_FLD(cmd_desc.out_param, arbelprm_query_dev_lim_st,
- log2_rsvd_qps);
- dev_lim_p->qpc_entry_sz =
- EX_FLD(cmd_desc.out_param, arbelprm_query_dev_lim_st,
- qpc_entry_sz);
-
- dev_lim_p->log2_rsvd_srqs =
- EX_FLD(cmd_desc.out_param, arbelprm_query_dev_lim_st,
- log2_rsvd_srqs);
- dev_lim_p->srq_entry_sz =
- EX_FLD(cmd_desc.out_param, arbelprm_query_dev_lim_st,
- srq_entry_sz);
-
- dev_lim_p->log2_rsvd_ees =
- EX_FLD(cmd_desc.out_param, arbelprm_query_dev_lim_st,
- log2_rsvd_ees);
- dev_lim_p->eec_entry_sz =
- EX_FLD(cmd_desc.out_param, arbelprm_query_dev_lim_st,
- eec_entry_sz);
-
- dev_lim_p->log2_rsvd_cqs =
- EX_FLD(cmd_desc.out_param, arbelprm_query_dev_lim_st,
- log2_rsvd_cqs);
- dev_lim_p->cqc_entry_sz =
- EX_FLD(cmd_desc.out_param, arbelprm_query_dev_lim_st,
- cqc_entry_sz);
-
- dev_lim_p->log2_rsvd_mtts =
- EX_FLD(cmd_desc.out_param, arbelprm_query_dev_lim_st,
- log2_rsvd_mtts);
- dev_lim_p->mtt_entry_sz =
- EX_FLD(cmd_desc.out_param, arbelprm_query_dev_lim_st,
- mtt_entry_sz);
-
- dev_lim_p->log2_rsvd_mrws =
- EX_FLD(cmd_desc.out_param, arbelprm_query_dev_lim_st,
- log2_rsvd_mrws);
- dev_lim_p->mpt_entry_sz =
- EX_FLD(cmd_desc.out_param, arbelprm_query_dev_lim_st,
- mpt_entry_sz);
-
- dev_lim_p->log2_rsvd_rdbs =
- EX_FLD(cmd_desc.out_param, arbelprm_query_dev_lim_st,
- log2_rsvd_rdbs);
-
- dev_lim_p->eqc_entry_sz =
- EX_FLD(cmd_desc.out_param, arbelprm_query_dev_lim_st,
- eqc_entry_sz);
-
- dev_lim_p->max_icm_size_l =
- EX_FLD(cmd_desc.out_param, arbelprm_query_dev_lim_st,
- max_icm_size_l);
- dev_lim_p->max_icm_size_h =
- EX_FLD(cmd_desc.out_param, arbelprm_query_dev_lim_st,
- max_icm_size_h);
-
- dev_lim_p->num_rsvd_uars =
- EX_FLD(cmd_desc.out_param, arbelprm_query_dev_lim_st,
- num_rsvd_uars);
- dev_lim_p->uar_sz =
- EX_FLD(cmd_desc.out_param, arbelprm_query_dev_lim_st,
- uar_sz);
- }
-
- return rc;
-}
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-
-#ifndef __cmdif_priv__h__
-#define __cmdif_priv__h__
-
-typedef enum {
- TRANS_NA,
- TRANS_IMMEDIATE,
- TRANS_MAILBOX
-} trans_type_t;
-
-typedef struct {
- __u32 *in_param; /* holds the virtually contigious buffer of the parameter block passed */
- unsigned int in_param_size;
- trans_type_t in_trans;
-
- __u32 input_modifier;
-
- __u32 *out_param; /* holds the virtually contigious buffer of the parameter block passed */
- unsigned int out_param_size;
- trans_type_t out_trans;
-
- __u32 opcode;
- __u8 opcode_modifier;
-} command_fields_t;
-
-typedef int XHH_cmd_status_t;
-
-static XHH_cmd_status_t cmd_invoke(command_fields_t * cmd_prms);
-
-#endif
+++ /dev/null
-.Boot over IB over Mellanox HCAs README - Pre-Alpha release
-==========================================================
-Document #2442, Rev 0.10, December 2005
-
-
-1. General
------------
-This README describes the Boot over IB package which enables booting a Linux
-kernel from a remote server using one of the Mellanox Technologies HCA
-devices. The package is based on Etherboot 5.4.1.
-
-The package actually implements a network driver for Etherboot. The wire
-protocol is compliant with IP Over IB
-(see http://www.ietf.org/html.charters/ipoib-charter.html for related
-documents).
-
-Etherboot uses a traditional setup of a DHCP server and a TFTP server to
-perform a remote boot in a similar manner to Ethernet NICs. The binary code is
-exported by the device as an expansion ROM image.
-
-
-2. Supported Devices
----------------------
-The following Mellanox Technologies HCA devices are supported:
-
- PCI Device ID Mellanox HCA Device
- ----------------------------------------------
- 23108 InfiniHost (P/N MT23108)
- 25208 InfiniHost III Ex (P/N MT25208) (InfiniHost)
- 25218 InfiniHost III Ex (P/N MT25208) (MemFree)
- 25204 InfiniHost III Lx (P/N MT25204)
-
-
- Note: For devices with more than one IB port, port 1 is used for
- communications.
-
-
-3. Compiling
-----------------
-From the src directory:
-Run" make bin/<device>.<ext>
-where device can be any of:
- MT23108
- MT25218
- MT25208
- MT25204
-
-and ext can be rom, zrom etc. (see Etherbot doumentation for more details)
-
-4. Directory Structure
------------------------
-All driver files are available under src/drivers/net/mlx_ipoib/. Under this
-directory the following files can be found:
-
- *** doc - Contains related documents including this file.
- *** patches - Contains needed patch files.
- *** samples - Contains sample files.
- *** . Contains driver source files.
-
-
-5. Burning the Flash Memory
-----------------------------
-The binary code resides in the same Flash device of the device firmware.
-However the binary files are distinct and do not affect each other. Mellanox's
-'mlxburn' tool is available for burning, however, it is not possible to burn
-the expansion ROM image by itself; rather, both the firmware and expansion ROM
-images must be burnt simultaneously.
-
-'mlxburn' is part of the Mellanox Firmware Tools (MFT) package available for
-download from www.mellanox.com under 'Firmware Downloads'.
-
-Example:
-The following command burns a firmware image and an expansion ROM image to an
-InfiniHost Adapter Card (P/N MHX-CE128-T.ini):
-
- mlxburn -fw fw-23108-a1-rel.mlx -exp_rom MT23108.bin
- /dev/mst/mt23108_pci_cr0 -conf MHX-CE128-T.ini
-
-*** Important Note: The .ini file must support burning expansion ROMs. For
-example, the following lines must appear in the .ini file. If they do not,
-please add them manually.
-
-[ADAPTER]
-exp_rom_en = true
-
-Mellanox's web site contains firmware binary files with extension .bin.gz.
-These files contain contain EVERYTHING the goes in the flash memory and thus
-are NOT suitable for including the expansion rom image. Therefore, one use the
-files with .mlx extension also available from Mellanox's web site.
-
-
-
-6. Preparing the DHCP Server
------------------------------
-DHCP messages over IP Over IB are transmitted as broadcasts. In order to
-distinguish between messages belonging to a certain DHCP session, the messages
-must carry the client identifier option (see ietf documentation referred to
-above). As of November 2005, ISC DHCP servers do not support this feature.
-They are expected to support this at the end of 2005. In order to work this
-out, the appropriate patch must be applied (see patches directory). It has
-been tested on version isc-dhcpd-V3.0.4b2.
-
-The DHCP server must run on a machine which supports IP Over IB. The Mellanox
-IBGD package (gen1 or gen2) can be used to provide this.
-To run the DHCP server from the command line use: dhcpd ib0
-
-7. DHCP Server Configuration File
-----------------------------------
-In order for the DHCP server to provide configuration records for clients, an
-appropriate configuration file dhcpd.conf must be created and put under /etc/.
-A sample configuration file with comments can be found in the samples directory.
-
-
-8. OpenSM
-----------
-To successfully boot over IB, the IB network must contain a Subnet Manager
-which configures the IB network. OpenSM is part of the IBGD distribution and
-can be used to accomplish that. Note that OpenSM may be run on the same host
-running the DHCP server but it is not mandatory.
-
-
-9. TFTP Server
----------------
-When the DHCP session is completed, the client has the IP address of the TFTP
-server from which it should download the kernel image. This TFTP server must
-run on a machine with InfiniBand support. The client loads first a loader
-image based on PXE API which then loads the kernel image. The image can be
-found in the Linux kernel homepage:
-
-http://www.kernel.org/pub/linux/boot/syslinux/
-
-
-10. BIOS Configuration
------------------------
-The expansion ROM image presents itself to the BIOS as a boot device. As a
-result, the BIOS will add it to the list of boot devices. The priority of this
-list can be modified when entering the BIOS setup. The boot over IB image must
-be set first for the BIOS to attempt to use it first.
-
-
-11. Operation
---------------
-When booting the client, a message appears on the screen describing the device
-found and the revision of the code. The user has 3 seconds to press a key for
-increased functionality:
-'V' will increase verbosity.
-'I' will prinit some information to aid in configuring the DHCP configuration
- file. In this case the display will hold for 5 seconds to let the user
- grasp the information.
-
-Note that increasing verbosity will significantly slow boot time and will
-print lots of debug messages to the screen.
-
-
-12. Diskless Machines
-----------------------
-Most often it is required to boot a diskless machine. In these cases the
-kernel mounts its root file system over NFS over one of the interfaces. For
-this to happen on a client with only InfiniBand interfaces, the kernel image
-must be configured accordingly and must include IP Over IB support. This can
-be achieved either by compiling this into the kernel or using initrd images
-that contain IP Over IB support.
-
-
-13. Changing Defaults
-----------------------
-As stated the driver uses port 1 for its communications. To use another port
-edit the file src/drivers/net/ib_driver.h and modify the definition of
-PXE_IB_PORT.
-
-
-14. Installing a package from Mellanox
---------------------------------------
-When using a package obtained from Mellanox Technologies' web site, the
-directory src/bin will contain the driver binary files. The files have a .bin
-extension and are equivalent to the same files with .zrom extension.
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-
-#include "ib_driver.h"
-
-static const __u8 ipv4_bcast_gid[] = {
- 0xff, 0x12, 0x40, 0x1b, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff
-};
-
-static int wait_logic_link_up(__u8 port)
-{
- unsigned int relax_time, max_time;
- relax_time = 500;
- max_time = 30000; /* 30 seconds */
- int rc;
- unsigned int i, error = 1;
- __u16 status;
- struct port_info_st pi_var;
- __u8 port_state;
-
- for (i = 0; i < max_time; i += relax_time) {
- rc = get_port_info(port, &pi_var, &status);
- if (rc) {
- eprintf("");
- return rc;
- } else {
- if (status == 0) {
- port_state = (pi_var.combined4 >> 24) & 0xf;
- //port_state= pi_var.port_state;
- if (port_state == 4) {
- error = 0;
- break;
- }
- }
- }
- printf("+");
- mdelay(relax_time);
- }
-
- if (i >= max_time)
- return -1;
-
- return 0;
-}
-
-static int ib_driver_init(struct pci_device *pci, udqp_t * ipoib_qph_p)
-{
- int rc;
- __u8 port;
- __u16 status;
- __u32 qkey;
- __u16 mlid;
- ud_av_t av;
- struct ib_eqe_st ib_eqe;
- __u8 num_eqe;
-
- tprintf("");
- rc = ib_device_init(pci);
- if (rc)
- return rc;
-
- tprintf("");
-
- memcpy(ib_data.bcast_gid.raw, ipv4_bcast_gid, sizeof(ipv4_bcast_gid));
-
- port = PXE_IB_PORT;
- rc = setup_hca(port, &ib_data.eq);
- if (rc)
- return rc;
- tprintf("setup_hca() success");
-
- ib_data.port = port;
-
- if(print_info)
- printf("boot port = %d\n", ib_data.port);
-
- rc = wait_logic_link_up(port);
- if (rc)
- return rc;
-
- tprintf("wait_logic_link_up() success");
-
- rc = get_guid_info(&status);
- if (rc) {
- eprintf("");
- return rc;
- } else if (status) {
- eprintf("");
- return rc;
- }
-
- tprintf("get_guid_info() success");
-
- /* this to flush stdout that contains previous chars */
- printf(" \n");
- if(print_info) {
- __u8 *gid=ib_data.port_gid.raw;
-
- printf("\n");
- printf("port GID=%hhx:%hhx:%hhx:%hhx:%hhx:%hhx:%hhx:%hhx:"
- "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx:%hhx:%hhx\n",
- gid[0],gid[1],gid[2],gid[3],gid[4],gid[5],gid[6],gid[7],
- gid[8],gid[9],gid[10],gid[11],gid[12],gid[13],gid[14],gid[15]);
- }
-
- rc = get_pkey_tbl(NULL, &status);
- if (rc) {
- eprintf("");
- return rc;
- } else if (status) {
- eprintf("");
- return rc;
- }
- rc = create_mads_qp(&ib_data.mads_qp,
- &ib_data.mads_snd_cq, &ib_data.mads_rcv_cq);
- if (rc) {
- eprintf("");
- return rc;
- }
-
- tprintf("attempt to join mcast group ...");
- rc = join_mc_group(&qkey, &mlid, 1);
- if (rc) {
- eprintf("");
- return rc;
- } else {
- tprintf("join_mc_group() successfull qkey=0x%lx, mlid=0x%x",
- qkey, mlid);
- }
-
- rc = create_ipoib_qp(&ib_data.ipoib_qp,
- &ib_data.ipoib_snd_cq,
- &ib_data.ipoib_rcv_cq, qkey);
- if (rc) {
- eprintf("");
- return rc;
- }
-
- tprintf("create_ipoib_qp() success");
- *ipoib_qph_p = ib_data.ipoib_qp;
-
- tprintf("register qp to receive mcast...");
- rc = add_qp_to_mcast_group(ib_data.bcast_gid, 1);
- if (rc) {
- eprintf("");
- return rc;
- } else {
- tprintf("add_qp_to_mcast_group() success");
- }
-
- /* create a broadcast group ud AV */
- av = alloc_ud_av();
- if (!av) {
- eprintf("");
- return -1;
- }
- tprintf("alloc_ud_av() success");
- modify_av_params(av, mlid, 1, 0, 0, &ib_data.bcast_gid, BCAST_QPN);
- tprintf("modify_av_params() success");
- ib_data.bcast_av = av;
-
- do {
- rc = poll_eq(&ib_eqe, &num_eqe);
- if (rc) {
- eprintf("");
- return -1;
- }
- if (num_eqe) {
- tprintf("num_eqe=%d", num_eqe);
- }
- tprintf("num_eqe=%d", num_eqe);
- } while (num_eqe);
- tprintf("eq is drained");
-
- clear_interrupt();
-
- return rc;
-}
-
-static int ib_driver_close(int fw_fatal)
-{
- int rc, ret = 0;
- __u32 qkey;
- __u16 mlid;
-
- rc = ib_device_close();
- if (rc) {
- eprintf("ib_device_close() failed");
- ret = 1;
- }
-
- tprintf("");
- if (!fw_fatal) {
- rc = join_mc_group(&qkey, &mlid, 0);
- if (rc) {
- eprintf("");
- ret = 1;
- }
- tprintf("join_mc_group(leave) success");
-
- rc = add_qp_to_mcast_group(ib_data.bcast_gid, 0);
- if (rc) {
- eprintf("");
- ret = 1;
- }
- tprintf("add_qp_to_mcast_group(remove) success");
-
- rc = cmd_close_ib(ib_data.port);
- if (rc) {
- eprintf("");
- ret = 1;
- }
- tprintf("cmd_close_ib(%d) success", ib_data.port);
-
- if (destroy_udqp(ib_data.mads_qp)) {
- eprintf("");
- ret = 1;
- }
-
- if (destroy_udqp(ib_data.ipoib_qp)) {
- eprintf("");
- ret = 1;
- }
- }
-
- rc = cmd_close_hca(fw_fatal);
- if (rc) {
- eprintf("");
- ret = 1;
- }
-
- if (!fw_fatal) {
- rc = cmd_sys_dis();
- if (rc) {
- eprintf("");
- ret = 1;
- }
- }
-
- return ret;
-}
-
-static int poll_cqe_tout(cq_t cqh, __u16 tout, void **wqe, int *good_p)
-{
- int rc;
- struct ib_cqe_st ib_cqe;
- __u8 num_cqes;
- unsigned long end;
-
- end = currticks() + tout;
- do {
- rc = ib_poll_cq(cqh, &ib_cqe, &num_cqes);
- if (rc)
- return rc;
-
- if (num_cqes == 1) {
- if (good_p) {
- *good_p = ib_cqe.is_error ? 0 : 1;
- }
- if (wqe)
- *wqe = ib_cqe.wqe;
- return 0;
- }
- }
- while (currticks() < end);
-
- return -1;
-}
-
-static u8 *get_port_gid(void)
-{
- return ib_data.port_gid.raw;
-}
-
-static __u32 ib_get_qpn(udqp_t qph)
-{
- __u32 qpn;
-
- qpn = dev_get_qpn(qph);
-
- return qpn;
-}
-
-static int drain_eq(void)
-{
- __u8 num_eqe = 0, tot_eqe = 0;
- int rc;
-
- do {
- tot_eqe += num_eqe;
- rc = poll_eq(ib_data.eq, &num_eqe);
- if (rc) {
- eprintf("");
- return -1;
- }
-
- tprintf("num_eqe=%d", num_eqe);
- } while (num_eqe);
- tprintf("eq is drained");
- if (tot_eqe) {
- tprintf("got %d eqes", tot_eqe);
- return -1;
- }
-
- return 0;
-}
-
-
-static int poll_error_buf(void)
-{
- __u32 *ptr= dev_ib_data.error_buf_addr;
- __u32 i;
-
- for (i=0; i<dev_ib_data.error_buf_size; ++i, ptr++) {
- if ( readl(ptr) ) {
- return -1;
- }
- }
-
- return 0;
-}
-
-
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-
-#ifndef __ib_driver_h__
-#define __ib_driver_h__
-
-#define MELLANOX_VENDOR_ID 0x15b3
-
-#define GLOBAL_PD 0x123456
-#define GLOBAL_QKEY 0x80010000
-
-#define MAD_BUF_SZ 256
-#define IPOIB_RCV_BUF_SZ 2048
-#define IPOIB_SND_BUF_SZ 2048
-#define GRH_SIZE 40
-
-#define ARP_BUF_SZ 56
-
-#define FL_EOL 255 /* end of free list */
-
-#define SEND_CQE_POLL_TOUT 38 /* 2 sec */
-#define SA_RESP_POLL_TOUT 91 /* 5 seconds */
-
-#define NUM_AVS 10
-
-#define PXE_IB_PORT 1
-
-#define SA_QPN 1
-#define BCAST_QPN 0xffffff
-
-#define QPN_BASE 0x550000
-
-enum {
- MADS_QPN_SN,
- IPOIB_QPN_SN,
- MAX_APP_QPS
-};
-
-enum {
- MADS_SND_CQN_SN,
- MADS_RCV_CQN_SN,
- IPOIB_SND_CQN_SN,
- IPOIB_RCV_CQN_SN,
- MAX_APP_CQS
-};
-
-enum {
- MTU_256 = 1,
- MTU_512 = 2,
- MTU_1024 = 3,
- MTU_2048 = 4,
-};
-
-#define HCR_BASE 0x80680
-#define HCR_OFFSET_GO 0x80698
-#define HCR_OFFSET_STATUS 0x80698
-#define HCR_OFFSET_OUTPRM_H 0x8068C
-#define HCR_OFFSET_OUTPRM_L 0x80690
-
-#define MKEY_PREFIX 0x77000000
-#define MKEY_IDX_MASK 0xffffff
-
-/* event types */
-/*=============*/
-/* Completion Events */
-#define XDEV_EV_TYPE_CQ_COMP 0
-
- /* IB - affiliated errors CQ */
-#define XDEV_EV_TYPE_CQ_ERR 0x04
-#define XDEV_EV_TYPE_LOCAL_WQ_CATAS_ERR 0x05
-
- /* Unaffiliated errors */
-#define XDEV_EV_TYPE_PORT_ERR 0x09
-#define XDEV_EV_TYPE_LOCAL_WQ_INVALID_REQ_ERR 0x10
-#define XDEV_EV_TYPE_LOCAL_WQ_ACCESS_VIOL_ERR 0x11
-
-/* NOPCODE field enumeration for doorbells and send-WQEs */
-#define XDEV_NOPCODE_SEND 10 /* Send */
-
-struct ib_gid_u32_st {
- __u32 dw[4];
-};
-
-union ib_gid_u {
- __u8 raw[16];
- struct ib_gid_u32_st as_u32;
-} __attribute__ ((packed));
-
-struct ib_cqe_st {
- __u8 is_error;
- __u8 is_send;
- void *wqe;
- __u32 count;
-};
-
-typedef void *udqp_t;
-typedef void *cq_t;
-typedef void *ud_av_t;
-typedef void *ud_send_wqe_t;
-typedef void *eq_t;
-
-struct ib_data_st {
-// __u32 mkey;
-// __u32 pd;
-// __u32 qkey;
- udqp_t mads_qp;
- udqp_t ipoib_qp;
- cq_t mads_snd_cq;
- cq_t mads_rcv_cq;
- cq_t ipoib_snd_cq;
- cq_t ipoib_rcv_cq;
- eq_t eq;
- __u16 sm_lid;
- __u16 pkey;
- union ib_gid_u port_gid;
- union ib_gid_u bcast_gid;
- ud_av_t bcast_av; /* av allocated and used solely for broadcast */
- __u8 port;
-};
-
-static int setup_hca(__u8 port, void **eq_p);
-static int post_send_req(udqp_t qp, ud_send_wqe_t wqe, __u8 num_gather);
-static void prep_send_wqe_buf(udqp_t qp,
- ud_av_t av,
- ud_send_wqe_t wqe,
- const void *buf,
- unsigned int offset, __u16 len, __u8 e);
-
-static int create_mads_qp(void **qp_pp, void **snd_cq_pp, void **rcv_cq_pp);
-
-static int create_ipoib_qp(udqp_t * qp_p,
- void **snd_cq_pp, void **rcv_cq_pp, __u32 qkey);
-
-static int gw_read_cr(__u32 addr, __u32 * result);
-static int gw_write_cr(__u32 addr, __u32 data);
-static ud_av_t alloc_ud_av(void);
-static void free_ud_av(ud_av_t av);
-static int ib_poll_cq(cq_t cq, struct ib_cqe_st *ib_cqe_p, __u8 * num_cqes);
-static int add_qp_to_mcast_group(union ib_gid_u mcast_gid, __u8 add);
-static int clear_interrupt(void);
-static int poll_cqe_tout(cq_t cqh, __u16 tout, void **wqe, int *good_p);
-
-static void *get_inprm_buf(void);
-static void *get_outprm_buf(void);
-static __u32 ib_get_qpn(udqp_t qph);
-
-static void dev_post_dbell(void *dbell, __u32 offset);
-
-static struct ib_data_st ib_data;
-
-#endif /* __ib_driver_h__ */
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-
-#include "ib_mad.h"
-#include "mad_attrib.h"
-#include "cmdif.h"
-#include "ib_driver.h"
-
-#define TID_START 0x1234
-#define TID_INC 117
-
-static u32 next_tid = TID_START;
-
-/*
- * get_port_info
- *
- * query the local device for the portinfo attribute
- *
- * port(in) port number to query
- * buf(out) buffer to hold the result
- */
-static int get_port_info(__u8 port, struct port_info_st *buf, __u16 * status)
-{
- union port_info_mad_u *inprm;
- union port_info_mad_u *outprm;
- int rc;
-
- inprm = get_inprm_buf();
- outprm = get_outprm_buf();
- memset(inprm, 0, sizeof *inprm);
-
- inprm->mad.mad_hdr.method = IB_MGMT_METHOD_GET;
- inprm->mad.mad_hdr.mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
- inprm->mad.mad_hdr.class_version = 1;
- inprm->mad.mad_hdr.base_version = IB_MGMT_BASE_VERSION;
- inprm->mad.mad_hdr.attr_id = IB_SMP_ATTR_PORT_INFO;
- inprm->mad.mad_hdr.attr_mod = port;
-
- rc = cmd_mad_ifc(inprm, (struct ib_mad_st *)outprm, port);
- if (!rc) {
- memcpy(buf, &outprm->mad.port_info,
- sizeof(outprm->mad.port_info));
- *status = inprm->mad.mad_hdr.status;
- if (!(*status)) {
- ib_data.sm_lid = outprm->mad.port_info.mastersm_lid;
- memcpy(&ib_data.port_gid.raw[0],
- outprm->mad.port_info.gid_prefix, 8);
- cpu_to_be_buf(&ib_data.port_gid.raw[0], 8);
- }
- }
- return rc;
-}
-
-/*
- * get_guid_info
- *
- * query the local device for the guidinfo attribute
- *
- * buf(out) buffer to hold the result
- */
-static int get_guid_info(__u16 * status)
-{
- union guid_info_mad_u *inprm;
- union guid_info_mad_u *outprm;
- int rc;
-
- inprm = get_inprm_buf();
- outprm = get_outprm_buf();
- memset(inprm, 0, sizeof *inprm);
-
- inprm->mad.mad_hdr.method = IB_MGMT_METHOD_GET;
- inprm->mad.mad_hdr.mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
- inprm->mad.mad_hdr.class_version = 1;
- inprm->mad.mad_hdr.base_version = IB_MGMT_BASE_VERSION;
- inprm->mad.mad_hdr.attr_id = IB_SMP_ATTR_GUID_INFO;
- inprm->mad.mad_hdr.attr_mod = 0;
-
- rc = cmd_mad_ifc(inprm, (struct ib_mad_st *)outprm, ib_data.port);
- if (!rc) {
- *status = inprm->mad.mad_hdr.status;
- if (!(*status)) {
- memcpy(&ib_data.port_gid.raw[8],
- &outprm->mad.guid_info.gid_tbl[0], 8);
- cpu_to_be_buf(&ib_data.port_gid.raw[8], 8);
- }
- }
- return rc;
-}
-
-static int get_pkey_tbl(struct pkey_tbl_st *pkey_tbl, __u16 * status)
-{
- union pkey_tbl_mad_u *inprm;
- union pkey_tbl_mad_u *outprm;
- int rc;
-
- inprm = get_inprm_buf();
- outprm = get_outprm_buf();
- memset(inprm, 0, sizeof *inprm);
- memset(outprm, 0, sizeof *outprm);
-
- inprm->mad.mad_hdr.method = IB_MGMT_METHOD_GET;
- inprm->mad.mad_hdr.mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
- inprm->mad.mad_hdr.class_version = 1;
- inprm->mad.mad_hdr.base_version = IB_MGMT_BASE_VERSION;
- inprm->mad.mad_hdr.attr_id = IB_SMP_ATTR_PKEY_TABLE;
- inprm->mad.mad_hdr.attr_mod = 0;
-
- rc = cmd_mad_ifc(inprm, (struct ib_mad_st *)outprm, 1);
- if (!rc) {
- if (pkey_tbl)
- memcpy(pkey_tbl, &outprm->mad.pkey_tbl, 2);
- *status = inprm->mad.mad_hdr.status;
- if (!(*status)) {
- ib_data.pkey = outprm->mad.pkey_tbl.pkey_tbl[0][1];
- ib_data.bcast_gid.raw[4] =
- outprm->mad.pkey_tbl.pkey_tbl[0][1] >> 8;
- ib_data.bcast_gid.raw[5] =
- outprm->mad.pkey_tbl.pkey_tbl[0][1] & 0xff;
- }
- }
- return rc;
-}
-
-static int join_mc_group(__u32 * qkey_p, __u16 * mlid_p, __u8 join)
-{
- struct mc_member_mad_st *mad, *rcv_mad;
- void *snd_wqe;
- void *tmp_wqe;
- udqp_t qp;
- void *av;
- int rc;
- u32 tid;
- void *rcv_wqe;
- int is_good;
-
- qp = ib_data.mads_qp;
-
- snd_wqe = alloc_send_wqe(qp);
- if (!snd_wqe) {
- eprintf("");
- return -1;
- }
- tprintf("allocated snd_wqe=0x%lx", snd_wqe);
-
- mad = get_send_wqe_buf(snd_wqe, 0);
- memset(mad, 0, 256);
-
- av = alloc_ud_av();
- if (!av) {
- eprintf("");
- free_wqe(snd_wqe);
- return -1;
- }
- modify_av_params(av, ib_data.sm_lid, 0, 0, 0, NULL, SA_QPN);
-
- prep_send_wqe_buf(qp, av, snd_wqe, NULL, 0, 256, 0);
-
- mad->mad_hdr.method = join ? IB_MGMT_METHOD_SET : IB_MGMT_METHOD_DELETE;
- mad->mad_hdr.mgmt_class = IB_MGMT_CLASS_SUBN_ADM;
- mad->mad_hdr.class_version = 2;
- mad->mad_hdr.base_version = IB_MGMT_BASE_VERSION;
- mad->mad_hdr.attr_id = IB_SA_ATTR_MC_MEMBER_REC;
- tid = next_tid;
- next_tid += TID_INC;
- mad->mad_hdr.tid[1] = tid;
-
- mad->sa_hdr.comp_mask[1] = IB_SA_MCMEMBER_REC_MGID |
- IB_SA_MCMEMBER_REC_PORT_GID | IB_SA_MCMEMBER_REC_JOIN_STATE;
-
- mad->mc_member.combined4 |= (1 << 24); /*mad->mc_member.join_state = 1; */
-
- be_to_cpu_buf(mad, sizeof *mad);
- memcpy(mad->mc_member.mgid, ib_data.bcast_gid.raw, 16);
- memcpy(mad->mc_member.port_gid, ib_data.port_gid.raw, 16);
-
- rc = post_send_req(qp, snd_wqe, 1);
- if (rc) {
- eprintf("");
- free_ud_av(av);
- free_wqe(snd_wqe);
- return -1;
- }
-
- tprintf("");
- /* poll the CQ to get the completions
- on the send and the expected receive */
-
- /* send completion */
- rc = poll_cqe_tout(ib_data.mads_snd_cq, SEND_CQE_POLL_TOUT, &tmp_wqe,
- &is_good);
- if (rc) {
- eprintf("");
- return -1;
- }
-
- if (tmp_wqe != snd_wqe) {
- eprintf("");
- return -1;
- }
-
- if (free_wqe(snd_wqe)) {
- eprintf("");
- return -1;
- }
- free_ud_av(av);
-
- if (!is_good) {
- eprintf("");
- return -1;
- }
-
- /* receive completion */
- rc = poll_cqe_tout(ib_data.mads_rcv_cq, SA_RESP_POLL_TOUT, &rcv_wqe,
- &is_good);
- if (rc) {
- eprintf("");
- return -1;
- }
-
- if (is_good) {
- rcv_mad = get_rcv_wqe_buf(rcv_wqe, 1);
- be_to_cpu_buf(rcv_mad, sizeof *rcv_mad);
- if (rcv_mad->mad_hdr.tid[1] == tid) {
- /* that's our response */
- if (mad->mad_hdr.status == 0) {
- /* good response - save results */
- *qkey_p = rcv_mad->mc_member.q_key;
- *mlid_p = rcv_mad->mc_member.combined1 >> 16; // rcv_mad->mc_member.mlid;
- } else {
- /* join failed */
- eprintf("");
- return -1;
- }
- } else {
- /* not our response */
- eprintf("");
- return -1;
- }
- }
-
- if (free_wqe(rcv_wqe)) {
- eprintf("");
- return -1;
- }
-
- return is_good ? 0 : -1;
-}
-
-static int get_path_record(union ib_gid_u *dgid, __u16 * dlid_p, u8 * sl_p,
- u8 * rate_p)
-{
- struct path_record_mad_st *mad, *rcv_mad;
- void *snd_wqe;
- udqp_t qp;
- ud_av_t av;
- void *tmp_wqe;
- void *rcv_wqe;
- u32 tid;
- int rc;
- int is_good;
-
- tprintf("gid=%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:"
- "%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x",
- dgid->raw[0], dgid->raw[1], dgid->raw[2], dgid->raw[3],
- dgid->raw[4], dgid->raw[5], dgid->raw[6], dgid->raw[7],
- dgid->raw[8], dgid->raw[9], dgid->raw[10], dgid->raw[11],
- dgid->raw[12], dgid->raw[13], dgid->raw[14], dgid->raw[15]);
- qp = ib_data.mads_qp;
-
- snd_wqe = alloc_send_wqe(qp);
- if (!snd_wqe) {
- eprintf("");
- return -1;
- }
-
- mad = get_send_wqe_buf(snd_wqe, 0);
- memset(mad, 0, 256);
-
- av = alloc_ud_av();
- if (!av) {
- eprintf("");
- free_wqe(snd_wqe);
- return -1;
- }
- modify_av_params(av, ib_data.sm_lid, 0, 0, 0, NULL, SA_QPN);
-
- prep_send_wqe_buf(qp, av, snd_wqe, NULL, 0, 256, 0);
-
- mad->mad_hdr.method = IB_MGMT_METHOD_GET;
- mad->mad_hdr.mgmt_class = IB_MGMT_CLASS_SUBN_ADM;
- mad->mad_hdr.class_version = 2;
- mad->mad_hdr.base_version = IB_MGMT_BASE_VERSION;
- mad->mad_hdr.attr_id = IB_SA_ATTR_PATH_REC;
- tid = next_tid;
- next_tid += TID_INC;
- mad->mad_hdr.tid[1] = tid;
-
- memcpy(mad->path_record.dgid.raw, dgid->raw, 16);
- cpu_to_be_buf(mad->path_record.dgid.raw, 16);
-
- mad->sa_hdr.comp_mask[1] = IB_SA_PATH_REC_DGID | IB_SA_PATH_REC_SGID;
-
- cpu_to_be_buf(mad, sizeof *mad);
- memcpy(mad->path_record.sgid.raw, ib_data.port_gid.raw, 16);
-
- rc = post_send_req(qp, snd_wqe, 1);
- if (rc) {
- eprintf("");
- free_ud_av(av);
- free_wqe(snd_wqe);
- return rc;
- }
-
- /* poll the CQ to get the completions
- on the send and the expected receive */
-
- /* send completion */
- rc = poll_cqe_tout(ib_data.mads_snd_cq, SEND_CQE_POLL_TOUT, &tmp_wqe,
- &is_good);
- if (rc) {
- eprintf("");
- return -1;
- }
-
- if (tmp_wqe != snd_wqe) {
- eprintf("");
- return -1;
- }
-
- if (free_wqe(snd_wqe)) {
- eprintf("");
- return -1;
- }
- free_ud_av(av);
-
- if (!is_good) {
- eprintf("");
- return -1;
- }
-
- /* receive completion */
- rc = poll_cqe_tout(ib_data.mads_rcv_cq, SA_RESP_POLL_TOUT, &rcv_wqe,
- &is_good);
- if (rc) {
- eprintf("");
- return -1;
- }
-
- if (is_good) {
- rcv_mad = get_rcv_wqe_buf(rcv_wqe, 1);
- be_to_cpu_buf(rcv_mad, sizeof *rcv_mad);
- if (rcv_mad->mad_hdr.tid[1] == tid) {
- /* that's our response */
- if (mad->mad_hdr.status == 0) {
- /* good response - save results */
- *dlid_p = rcv_mad->path_record.dlid;
- *sl_p = (rcv_mad->path_record.combined3 >> 16) & 0xf; // rcv_mad->path_record.sl;
- *rate_p = rcv_mad->path_record.combined3 & 0x3f; //rcv_mad->path_record.rate;
- } else {
- /* join failed */
- eprintf("");
- return -1;
- }
- } else {
- /* not our response */
- eprintf("");
- return -1;
- }
- }
-
- if (free_wqe(rcv_wqe)) {
- eprintf("");
- return -1;
- }
-
- tprintf("");
- return is_good ? 0 : -1;
-}
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-
-#ifndef __ib_mad_h__
-#define __ib_mad_h__
-
-#include "ib_driver.h"
-
-/* Management base version */
-#define IB_MGMT_BASE_VERSION 1
-
-/* Management classes */
-#define IB_MGMT_CLASS_SUBN_LID_ROUTED 0x01
-#define IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE 0x81
-#define IB_MGMT_CLASS_SUBN_ADM 0x03
-#define IB_MGMT_CLASS_PERF_MGMT 0x04
-#define IB_MGMT_CLASS_BM 0x05
-#define IB_MGMT_CLASS_DEVICE_MGMT 0x06
-#define IB_MGMT_CLASS_CM 0x07
-#define IB_MGMT_CLASS_SNMP 0x08
-#define IB_MGMT_CLASS_VENDOR_RANGE2_START 0x30
-#define IB_MGMT_CLASS_VENDOR_RANGE2_END 0x4F
-
-/* Management methods */
-#define IB_MGMT_METHOD_GET 0x01
-#define IB_MGMT_METHOD_SET 0x02
-#define IB_MGMT_METHOD_GET_RESP 0x81
-#define IB_MGMT_METHOD_SEND 0x03
-#define IB_MGMT_METHOD_TRAP 0x05
-#define IB_MGMT_METHOD_REPORT 0x06
-#define IB_MGMT_METHOD_REPORT_RESP 0x86
-#define IB_MGMT_METHOD_TRAP_REPRESS 0x07
-#define IB_MGMT_METHOD_DELETE 0x15
-
-#define IB_MGMT_METHOD_RESP 0x80
-
-/* Subnet management attributes */
-#define IB_SMP_ATTR_NOTICE 0x0002
-#define IB_SMP_ATTR_NODE_DESC 0x0010
-#define IB_SMP_ATTR_NODE_INFO 0x0011
-#define IB_SMP_ATTR_SWITCH_INFO 0x0012
-#define IB_SMP_ATTR_GUID_INFO 0x0014
-#define IB_SMP_ATTR_PORT_INFO 0x0015
-#define IB_SMP_ATTR_PKEY_TABLE 0x0016
-#define IB_SMP_ATTR_SL_TO_VL_TABLE 0x0017
-#define IB_SMP_ATTR_VL_ARB_TABLE 0x0018
-#define IB_SMP_ATTR_LINEAR_FORWARD_TABLE 0x0019
-#define IB_SMP_ATTR_RANDOM_FORWARD_TABLE 0x001A
-#define IB_SMP_ATTR_MCAST_FORWARD_TABLE 0x001B
-#define IB_SMP_ATTR_SM_INFO 0x0020
-#define IB_SMP_ATTR_VENDOR_DIAG 0x0030
-#define IB_SMP_ATTR_LED_INFO 0x0031
-#define IB_SMP_ATTR_VENDOR_MASK 0xFF00
-
-struct ib_mad_hdr_st {
- __u8 method;
- __u8 class_version;
- __u8 mgmt_class;
- __u8 base_version;
- __u16 class_specific;
- __u16 status;
- __u32 tid[2];
- __u16 resv;
- __u16 attr_id;
- __u32 attr_mod;
-} __attribute__ ((packed));
-
-struct rmpp_hdr_st {
- __u32 raw[3];
-} __attribute__ ((packed));
-
-struct sa_header_st {
- __u32 sm_key[2];
- __u16 attrib_offset;
- __u16 r0;
- __u32 comp_mask[2];
-} __attribute__ ((packed));
-
-struct ib_mad_st {
- struct ib_mad_hdr_st mad_hdr;
- __u8 data[232];
-} __attribute__ ((packed));
-
-union mad_u {
- __u8 raw[256];
- struct ib_mad_st mad;
-} __attribute__ ((packed));
-
-static int get_path_record(union ib_gid_u *dgid, __u16 * dlid_p, __u8 * sl_p,
- __u8 * rate_p);
-
-#endif /* __ib_mad_h__ */
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-
-#include "mt23108.h"
-#include "ib_driver.h"
-#include <gpxe/pci.h>
-
-struct device_buffers_st {
- union recv_wqe_u mads_qp_rcv_queue[NUM_MADS_RCV_WQES]
- __attribute__ ((aligned(RECV_WQE_U_ALIGN)));
- union recv_wqe_u ipoib_qp_rcv_queue[NUM_IPOIB_RCV_WQES]
- __attribute__ ((aligned(RECV_WQE_U_ALIGN)));
- union ud_send_wqe_u mads_qp_snd_queue[NUM_MADS_SND_WQES]
- __attribute__ ((aligned(UD_SEND_WQE_U_ALIGN)));
- union ud_send_wqe_u ipoib_qp_snd_queue[NUM_IPOIB_SND_WQES]
- __attribute__ ((aligned(UD_SEND_WQE_U_ALIGN)));
- u8 inprm_buf[INPRM_BUF_SZ] __attribute__ ((aligned(INPRM_BUF_ALIGN)));
- u8 outprm_buf[OUTPRM_BUF_SZ]
- __attribute__ ((aligned(OUTPRM_BUF_ALIGN)));
- struct eqe_t eq_buf[1 << LOG2_EQ_SZ]
- __attribute__ ((aligned(sizeof(struct eqe_t))));
- union cqe_st mads_snd_cq_buf[NUM_MADS_SND_CQES]
- __attribute__ ((aligned(sizeof(union cqe_st))));
- union cqe_st ipoib_snd_cq_buf[NUM_IPOIB_SND_CQES]
- __attribute__ ((aligned(sizeof(union cqe_st))));
- union cqe_st mads_rcv_cq_buf[NUM_MADS_RCV_CQES]
- __attribute__ ((aligned(sizeof(union cqe_st))));
- union cqe_st ipoib_rcv_cq_buf[NUM_IPOIB_RCV_CQES]
- __attribute__ ((aligned(sizeof(union cqe_st))));
- union ud_av_u av_array[NUM_AVS]
- __attribute__ ((aligned(ADDRESS_VECTOR_ST_ALIGN)));
-} __attribute__ ((packed));
-
-#define STRUCT_ALIGN_SZ 4096
-#define SRC_BUF_SZ (sizeof(struct device_buffers_st) + STRUCT_ALIGN_SZ - 1)
-
-/* the following must be kept in this order
- for the memory region to cover the buffers */
-static u8 src_buf[SRC_BUF_SZ];
-static struct ib_buffers_st ib_buffers;
-static __u32 memreg_size;
-/* end of order constraint */
-
-static struct dev_pci_struct tavor_pci_dev;
-static struct device_buffers_st *dev_buffers_p;
-static struct device_ib_data_st dev_ib_data;
-
-static int gw_write_cr(__u32 addr, __u32 data)
-{
- writel(htonl(data), tavor_pci_dev.cr_space + addr);
- return 0;
-}
-
-static int gw_read_cr(__u32 addr, __u32 * result)
-{
- *result = ntohl(readl(tavor_pci_dev.cr_space + addr));
- return 0;
-}
-
-static int reset_hca(void)
-{
- return gw_write_cr(TAVOR_RESET_OFFSET, 1);
-}
-
-static int find_mlx_bridge(__u8 hca_bus, __u8 * br_bus_p, __u8 * br_devfn_p)
-{
- int bus;
- int dev;
- int devfn;
- int rc;
- __u16 vendor, dev_id;
- __u8 sec_bus;
-
- for (bus = 0; bus < 256; ++bus) {
- for (dev = 0; dev < 32; ++dev) {
- devfn = (dev << 3);
- rc = pcibios_read_config_word(bus, devfn, PCI_VENDOR_ID,
- &vendor);
- if (rc)
- return rc;
-
- if (vendor != MELLANOX_VENDOR_ID)
- continue;
-
- rc = pcibios_read_config_word(bus, devfn, PCI_DEVICE_ID,
- &dev_id);
- if (rc)
- return rc;
-
- if (dev_id != TAVOR_BRIDGE_DEVICE_ID)
- continue;
-
- rc = pcibios_read_config_byte(bus, devfn,
- PCI_SECONDARY_BUS,
- &sec_bus);
- if (rc)
- return rc;
-
- if (sec_bus == hca_bus) {
- *br_bus_p = bus;
- *br_devfn_p = devfn;
- return 0;
- }
- }
- }
-
- return -1;
-}
-
-static int ib_device_init(struct pci_device *dev)
-{
- int i;
- int rc;
- __u8 br_bus, br_devfn;
-
- tprintf("");
-
- memset(&dev_ib_data, 0, sizeof dev_ib_data);
-
- /* save bars */
- tprintf("bus=%d devfn=0x%x", dev->bus, dev->devfn);
- for (i = 0; i < 6; ++i) {
- tavor_pci_dev.dev.bar[i] =
- pci_bar_start(dev, PCI_BASE_ADDRESS_0 + (i << 2));
- tprintf("bar[%d]= 0x%08lx", i, tavor_pci_dev.dev.bar[i]);
- }
-
- tprintf("");
- /* save config space */
- for (i = 0; i < 64; ++i) {
- rc = pci_read_config_dword(dev, i << 2,
- &tavor_pci_dev.dev.
- dev_config_space[i]);
- if (rc) {
- eprintf("");
- return rc;
- }
- tprintf("config[%d]= 0x%08lx", i << 2,
- tavor_pci_dev.dev.dev_config_space[i]);
- }
-
- tprintf("");
- tavor_pci_dev.dev.dev = dev;
-
- tprintf("");
- if (dev->dev_id == TAVOR_DEVICE_ID) {
-
- rc = find_mlx_bridge(dev->bus, &br_bus, &br_devfn);
- if (rc) {
- eprintf("");
- return rc;
- }
-
- tavor_pci_dev.br.bus = br_bus;
- tavor_pci_dev.br.devfn = br_devfn;
-
- tprintf("bus=%d devfn=0x%x", br_bus, br_devfn);
- /* save config space */
- for (i = 0; i < 64; ++i) {
- rc = pcibios_read_config_dword(br_bus, br_devfn, i << 2,
- &tavor_pci_dev.br.
- dev_config_space[i]);
- if (rc) {
- eprintf("");
- return rc;
- }
- tprintf("config[%d]= 0x%08lx", i << 2,
- tavor_pci_dev.br.dev_config_space[i]);
- }
- }
-
- tprintf("");
-
- /* map cr-space */
- tavor_pci_dev.cr_space = ioremap(tavor_pci_dev.dev.bar[0], 0x100000);
- if (!tavor_pci_dev.cr_space) {
- eprintf("");
- return -1;
- }
-
- /* map uar */
- tavor_pci_dev.uar =
- ioremap(tavor_pci_dev.dev.bar[2] + UAR_IDX * 0x1000, 0x1000);
- if (!tavor_pci_dev.uar) {
- eprintf("");
- return -1;
- }
- tprintf("uar_base (pa:va) = 0x%lx 0x%lx",
- tavor_pci_dev.dev.bar[2] + UAR_IDX * 0x1000, tavor_pci_dev.uar);
-
- tprintf("");
-
- return 0;
-}
-
-static inline unsigned long lalign(unsigned long buf, unsigned long align)
-{
- return (unsigned long)((buf + align - 1) &
- (~(((unsigned long)align) - 1)));
-}
-
-static int init_dev_data(void)
-{
- unsigned long tmp;
-
- tmp = lalign(virt_to_bus(src_buf), STRUCT_ALIGN_SZ);
-
- dev_buffers_p = bus_to_virt(tmp);
- memreg_size = (__u32) (&memreg_size) - (__u32) dev_buffers_p;
- tprintf("src_buf=0x%lx, dev_buffers_p=0x%lx, memreg_size=0x%x", src_buf,
- dev_buffers_p, memreg_size);
-
- return 0;
-}
-
-static int restore_config(void)
-{
- int i;
- int rc;
-
- if (tavor_pci_dev.dev.dev->dev_id == TAVOR_DEVICE_ID) {
- for (i = 0; i < 64; ++i) {
- rc = pcibios_write_config_dword(tavor_pci_dev.br.bus,
- tavor_pci_dev.br.devfn,
- i << 2,
- tavor_pci_dev.br.
- dev_config_space[i]);
- if (rc) {
- return rc;
- }
- }
- }
-
- for (i = 0; i < 64; ++i) {
- if (i != 22 && i != 23) {
- rc = pci_write_config_dword(tavor_pci_dev.dev.dev,
- i << 2,
- tavor_pci_dev.dev.
- dev_config_space[i]);
- if (rc) {
- return rc;
- }
- }
- }
- return 0;
-}
-
-static void prep_init_hca_buf(const struct init_hca_st *init_hca_p, void *buf)
-{
- /*struct init_hca_param_st */ void *p = buf;
- void *tmp;
-
- memset(buf, 0, MT_STRUCT_SIZE(tavorprm_init_hca_st));
-
- tmp =
- p + MT_BYTE_OFFSET(tavorprm_init_hca_st,
- qpc_eec_cqc_eqc_rdb_parameters);
-
- INS_FLD(init_hca_p->qpc_base_addr_h, tmp, tavorprm_qpcbaseaddr_st,
- qpc_base_addr_h);
- INS_FLD(init_hca_p->
- qpc_base_addr_l >> (32 -
- (MT_BIT_SIZE
- (tavorprm_qpcbaseaddr_st,
- qpc_base_addr_l))), tmp,
- tavorprm_qpcbaseaddr_st, qpc_base_addr_l);
- INS_FLD(init_hca_p->log_num_of_qp, tmp, tavorprm_qpcbaseaddr_st,
- log_num_of_qp);
-
- INS_FLD(init_hca_p->cqc_base_addr_h, tmp, tavorprm_qpcbaseaddr_st,
- cqc_base_addr_h);
- INS_FLD(init_hca_p->
- cqc_base_addr_l >> (32 -
- (MT_BIT_SIZE
- (tavorprm_qpcbaseaddr_st,
- cqc_base_addr_l))), tmp,
- tavorprm_qpcbaseaddr_st, cqc_base_addr_l);
- INS_FLD(init_hca_p->log_num_of_cq, tmp, tavorprm_qpcbaseaddr_st,
- log_num_of_cq);
-
- INS_FLD(init_hca_p->eqc_base_addr_h, tmp, tavorprm_qpcbaseaddr_st,
- eqc_base_addr_h);
- INS_FLD(init_hca_p->
- eqc_base_addr_l >> (32 -
- (MT_BIT_SIZE
- (tavorprm_qpcbaseaddr_st,
- eqc_base_addr_l))), tmp,
- tavorprm_qpcbaseaddr_st, eqc_base_addr_l);
- INS_FLD(LOG2_EQS, tmp, tavorprm_qpcbaseaddr_st, log_num_eq);
-
- INS_FLD(init_hca_p->srqc_base_addr_h, tmp, tavorprm_qpcbaseaddr_st,
- srqc_base_addr_h);
- INS_FLD(init_hca_p->
- srqc_base_addr_l >> (32 -
- (MT_BIT_SIZE
- (tavorprm_qpcbaseaddr_st,
- srqc_base_addr_l))), tmp,
- tavorprm_qpcbaseaddr_st, srqc_base_addr_l);
- INS_FLD(init_hca_p->log_num_of_srq, tmp, tavorprm_qpcbaseaddr_st,
- log_num_of_srq);
-
- INS_FLD(init_hca_p->eqpc_base_addr_h, tmp, tavorprm_qpcbaseaddr_st,
- eqpc_base_addr_h);
- INS_FLD(init_hca_p->eqpc_base_addr_l, tmp, tavorprm_qpcbaseaddr_st,
- eqpc_base_addr_l);
-
- INS_FLD(init_hca_p->eeec_base_addr_h, tmp, tavorprm_qpcbaseaddr_st,
- eeec_base_addr_h);
- INS_FLD(init_hca_p->eeec_base_addr_l, tmp, tavorprm_qpcbaseaddr_st,
- eeec_base_addr_l);
-
- tmp = p + MT_BYTE_OFFSET(tavorprm_init_hca_st, multicast_parameters);
-
- INS_FLD(init_hca_p->mc_base_addr_h, tmp, tavorprm_multicastparam_st,
- mc_base_addr_h);
- INS_FLD(init_hca_p->mc_base_addr_l, tmp, tavorprm_multicastparam_st,
- mc_base_addr_l);
-
- INS_FLD(init_hca_p->log_mc_table_entry_sz, tmp,
- tavorprm_multicastparam_st, log_mc_table_entry_sz);
- INS_FLD(init_hca_p->log_mc_table_sz, tmp, tavorprm_multicastparam_st,
- log_mc_table_sz);
- INS_FLD(init_hca_p->mc_table_hash_sz, tmp, tavorprm_multicastparam_st,
- mc_table_hash_sz);
-
- tmp = p + MT_BYTE_OFFSET(tavorprm_init_hca_st, tpt_parameters);
-
- INS_FLD(init_hca_p->mpt_base_addr_h, tmp, tavorprm_tptparams_st,
- mpt_base_adr_h);
- INS_FLD(init_hca_p->mpt_base_addr_l, tmp, tavorprm_tptparams_st,
- mpt_base_adr_l);
- INS_FLD(init_hca_p->log_mpt_sz, tmp, tavorprm_tptparams_st, log_mpt_sz);
-
- INS_FLD(init_hca_p->mtt_base_addr_h, tmp, tavorprm_tptparams_st,
- mtt_base_addr_h);
- INS_FLD(init_hca_p->mtt_base_addr_l, tmp, tavorprm_tptparams_st,
- mtt_base_addr_l);
-
- tmp = p + MT_BYTE_OFFSET(tavorprm_init_hca_st, uar_parameters);
- INS_FLD(tavor_pci_dev.dev.bar[3], tmp, tavorprm_uar_params_st,
- uar_base_addr_h);
- INS_FLD(tavor_pci_dev.dev.bar[2] & 0xfff00000, tmp,
- tavorprm_uar_params_st, uar_base_addr_l);
-
-}
-
-static void prep_sw2hw_mpt_buf(void *buf, __u32 mkey)
-{
- INS_FLD(1, buf, tavorprm_mpt_st, m_io);
- INS_FLD(1, buf, tavorprm_mpt_st, lw);
- INS_FLD(1, buf, tavorprm_mpt_st, lr);
- INS_FLD(1, buf, tavorprm_mpt_st, pa);
- INS_FLD(1, buf, tavorprm_mpt_st, r_w);
-
- INS_FLD(mkey, buf, tavorprm_mpt_st, mem_key);
- INS_FLD(GLOBAL_PD, buf, tavorprm_mpt_st, pd);
-
- INS_FLD(virt_to_bus(dev_buffers_p), buf, tavorprm_mpt_st,
- start_address_l);
- INS_FLD(memreg_size, buf, tavorprm_mpt_st, reg_wnd_len_l);
-}
-
-static void prep_sw2hw_eq_buf(void *buf, struct eqe_t *eq)
-{
- memset(buf, 0, MT_STRUCT_SIZE(tavorprm_eqc_st));
-
- INS_FLD(2, buf, tavorprm_eqc_st, st); /* fired */
- INS_FLD(virt_to_bus(eq), buf, tavorprm_eqc_st, start_address_l);
- INS_FLD(LOG2_EQ_SZ, buf, tavorprm_eqc_st, log_eq_size);
- INS_FLD(UAR_IDX, buf, tavorprm_eqc_st, usr_page);
- INS_FLD(GLOBAL_PD, buf, tavorprm_eqc_st, pd);
- INS_FLD(dev_ib_data.mkey, buf, tavorprm_eqc_st, lkey);
-}
-
-static void init_eq_buf(void *eq_buf)
-{
- int num_eqes = 1 << LOG2_EQ_SZ;
-
- memset(eq_buf, 0xff, num_eqes * sizeof(struct eqe_t));
-}
-
-static void prep_init_ib_buf(void *buf)
-{
- __u32 *ptr = (__u32 *) buf;
-
- ptr[0] = 0x4310;
- ptr[1] = 1;
- ptr[2] = 64;
-}
-
-static void prep_sw2hw_cq_buf(void *buf, __u8 eqn, __u32 cqn,
- union cqe_st *cq_buf)
-{
- __u32 *ptr = (__u32 *) buf;
-
- ptr[2] = virt_to_bus(cq_buf);
- ptr[3] = (LOG2_CQ_SZ << 24) | UAR_IDX;
- ptr[4] = eqn;
- ptr[5] = eqn;
- ptr[6] = dev_ib_data.pd;
- ptr[7] = dev_ib_data.mkey;
- ptr[12] = cqn;
-}
-
-static void prep_rst2init_qpee_buf(void *buf, __u32 snd_cqn, __u32 rcv_cqn,
- __u32 qkey)
-{
- struct qp_ee_state_tarnisition_st *prm;
- void *tmp;
-
- prm = (struct qp_ee_state_tarnisition_st *)buf;
-
- INS_FLD(3, &prm->ctx, tavorprm_queue_pair_ee_context_entry_st, st); /* service type = UD */
- INS_FLD(3, &prm->ctx, tavorprm_queue_pair_ee_context_entry_st, pm_state); /* required for UD QP */
- INS_FLD(UAR_IDX, &prm->ctx, tavorprm_queue_pair_ee_context_entry_st,
- usr_page);
- INS_FLD(dev_ib_data.pd, &prm->ctx,
- tavorprm_queue_pair_ee_context_entry_st, pd);
- INS_FLD(dev_ib_data.mkey, &prm->ctx,
- tavorprm_queue_pair_ee_context_entry_st, wqe_lkey);
- INS_FLD(1, &prm->ctx, tavorprm_queue_pair_ee_context_entry_st, ssc); /* generate send CQE */
- INS_FLD(1, &prm->ctx, tavorprm_queue_pair_ee_context_entry_st, rsc); /* generate receive CQE */
- INS_FLD(snd_cqn, &prm->ctx, tavorprm_queue_pair_ee_context_entry_st,
- cqn_snd);
- INS_FLD(rcv_cqn, &prm->ctx, tavorprm_queue_pair_ee_context_entry_st,
- cqn_rcv);
- INS_FLD(qkey, &prm->ctx, tavorprm_queue_pair_ee_context_entry_st,
- q_key);
-
- tmp =
- (void *)(&prm->ctx) +
- MT_BYTE_OFFSET(tavorprm_queue_pair_ee_context_entry_st,
- primary_address_path);
- INS_FLD(dev_ib_data.port, tmp, tavorprm_address_path_st, port_number);
-
- INS_FLD(4, &prm->ctx, tavorprm_queue_pair_ee_context_entry_st, mtu);
- INS_FLD(0xb, &prm->ctx, tavorprm_queue_pair_ee_context_entry_st,
- msg_max);
-}
-
-static void prep_init2rtr_qpee_buf(void *buf)
-{
- struct qp_ee_state_tarnisition_st *prm;
-
- prm = (struct qp_ee_state_tarnisition_st *)buf;
-
- INS_FLD(4, &prm->ctx, tavorprm_queue_pair_ee_context_entry_st, mtu);
- INS_FLD(0xb, &prm->ctx, tavorprm_queue_pair_ee_context_entry_st,
- msg_max);
-}
-
-static void init_av_array()
-{
- int i;
-
- dev_ib_data.udav.av_array = dev_buffers_p->av_array;
- dev_ib_data.udav.udav_next_free = FL_EOL;
- for (i = 0; i < NUM_AVS; ++i) {
- dev_ib_data.udav.av_array[i].ud_av.next_free =
- dev_ib_data.udav.udav_next_free;
- dev_ib_data.udav.udav_next_free = i;
- }
- tprintf("dev_ib_data.udav.udav_next_free=%d", i);
-}
-
-static int setup_hca(__u8 port, void **eq_p)
-{
- int rc;
- __u32 key, in_key;
- __u32 *inprm;
- struct eqe_t *eq_buf;
- __u32 event_mask;
- void *cfg;
- int ret = 0;
- __u8 eqn;
- struct dev_lim_st dev_lim;
- struct init_hca_st init_hca;
- __u32 offset, base_h, base_l;
- const __u32 delta = 0x400000;
- struct query_fw_st qfw;
-
- tprintf("called");
-
- init_dev_data();
-
- rc = reset_hca();
- if (rc) {
- ret = -1;
- eprintf("");
- goto exit;
- } else {
- tprintf("reset_hca() success");
- }
-
- mdelay(1000); /* wait for 1 sec */
-
- rc = restore_config();
- if (rc) {
- ret = -1;
- eprintf("");
- goto exit;
- } else {
- tprintf("restore_config() success");
- }
-
- dev_ib_data.pd = GLOBAL_PD;
- dev_ib_data.port = port;
-
- /* execute system enable command */
- rc = cmd_sys_en();
- if (rc) {
- ret = -1;
- eprintf("");
- goto exit;
- } else {
- tprintf("cmd_sys_en() success");
- }
-
- rc= cmd_query_fw(&qfw);
- if (rc) {
- ret = -1;
- eprintf("");
- goto exit;
- } else {
- tprintf("cmd_query_fw() success");
-
- if (print_info) {
- printf("FW ver = %d.%d.%d\n",
- qfw.fw_rev_major,
- qfw.fw_rev_minor,
- qfw.fw_rev_subminor);
- }
- tprintf("fw_rev_major=%d", qfw.fw_rev_major);
- tprintf("fw_rev_minor=%d", qfw.fw_rev_minor);
- tprintf("fw_rev_subminor=%d", qfw.fw_rev_subminor);
- tprintf("error_buf_start_h=0x%x", qfw.error_buf_start_h);
- tprintf("error_buf_start_l=0x%x", qfw.error_buf_start_l);
- tprintf("error_buf_size=%d", qfw.error_buf_size);
- }
-
- if (qfw.error_buf_start_h) {
- eprintf("too high physical address");
- ret = -1;
- goto exit;
- }
-
- dev_ib_data.error_buf_addr= ioremap(qfw.error_buf_start_l,
- qfw.error_buf_size*4);
- dev_ib_data.error_buf_size= qfw.error_buf_size;
- if (!dev_ib_data.error_buf_addr) {
- eprintf("");
- ret = -1;
- goto exit;
- }
-
-
- rc = cmd_query_dev_lim(&dev_lim);
- if (rc) {
- ret = -1;
- eprintf("");
- goto exit;
- } else {
- tprintf("cmd_query_dev_lim() success");
- tprintf("log2_rsvd_qps=%x", dev_lim.log2_rsvd_qps);
- tprintf("qpc_entry_sz=%x", dev_lim.qpc_entry_sz);
- tprintf("log2_rsvd_srqs=%x", dev_lim.log2_rsvd_srqs);
- tprintf("srq_entry_sz=%x", dev_lim.srq_entry_sz);
- tprintf("log2_rsvd_ees=%x", dev_lim.log2_rsvd_ees);
- tprintf("eec_entry_sz=%x", dev_lim.eec_entry_sz);
- tprintf("log2_rsvd_cqs=%x", dev_lim.log2_rsvd_cqs);
- tprintf("cqc_entry_sz=%x", dev_lim.cqc_entry_sz);
- tprintf("log2_rsvd_mtts=%x", dev_lim.log2_rsvd_mtts);
- tprintf("mtt_entry_sz=%x", dev_lim.mtt_entry_sz);
- tprintf("log2_rsvd_mrws=%x", dev_lim.log2_rsvd_mrws);
- tprintf("mpt_entry_sz=%x", dev_lim.mpt_entry_sz);
- tprintf("eqc_entry_sz=%x", dev_lim.eqc_entry_sz);
- }
-
- /* set the qp and cq numbers according
- to the results of query_dev_lim */
- dev_ib_data.mads_qp.qpn = (1 << dev_lim.log2_rsvd_qps) +
- +QPN_BASE + MADS_QPN_SN;
- dev_ib_data.ipoib_qp.qpn = (1 << dev_lim.log2_rsvd_qps) +
- +QPN_BASE + IPOIB_QPN_SN;
-
- dev_ib_data.mads_qp.snd_cq.cqn = (1 << dev_lim.log2_rsvd_cqs) +
- MADS_SND_CQN_SN;
- dev_ib_data.mads_qp.rcv_cq.cqn = (1 << dev_lim.log2_rsvd_cqs) +
- MADS_RCV_CQN_SN;
-
- dev_ib_data.ipoib_qp.snd_cq.cqn = (1 << dev_lim.log2_rsvd_cqs) +
- IPOIB_SND_CQN_SN;
- dev_ib_data.ipoib_qp.rcv_cq.cqn = (1 << dev_lim.log2_rsvd_cqs) +
- IPOIB_RCV_CQN_SN;
-
- /* disable SRQ */
- cfg = (void *)dev_buffers_p->inprm_buf;
- memset(cfg, 0, MT_STRUCT_SIZE(tavorprm_mod_stat_cfg_st));
- INS_FLD(1, cfg, tavorprm_mod_stat_cfg_st, srq_m); //cfg->srq_m = 1;
- rc = cmd_mod_stat_cfg(cfg);
- if (rc) {
- ret = -1;
- eprintf("");
- goto exit;
- } else {
- tprintf("cmd_mod_stat_cfg() success");
- }
-
- /* prepare the init_hca params to pass
- to prep_init_hca_buf */
- memset(&init_hca, 0, sizeof init_hca);
- offset = 0;
- base_h = tavor_pci_dev.dev.bar[5] & 0xfffffff0;
- base_l = tavor_pci_dev.dev.bar[4] & 0xfffffff0;
-
- tprintf("base_h=0x%lx, base_l=0x%lx", base_h, base_l);
-
- init_hca.qpc_base_addr_h = base_h;
- init_hca.qpc_base_addr_l = base_l + offset;
- init_hca.log_num_of_qp = dev_lim.log2_rsvd_qps + 1;
- offset += delta;
-
- init_hca.eec_base_addr_h = base_h;
- init_hca.eec_base_addr_l = base_l + offset;
- init_hca.log_num_of_ee = dev_lim.log2_rsvd_ees;
- offset += delta;
-
- init_hca.srqc_base_addr_h = base_h;
- init_hca.srqc_base_addr_l = base_l + offset;
- init_hca.log_num_of_srq = dev_lim.log2_rsvd_srqs;
- offset += delta;
-
- init_hca.cqc_base_addr_h = base_h;
- init_hca.cqc_base_addr_l = base_l + offset;
- init_hca.log_num_of_cq = dev_lim.log2_rsvd_cqs + 1;
- offset += delta;
-
- init_hca.eqpc_base_addr_h = base_h;
- init_hca.eqpc_base_addr_l = base_l + offset;
- offset += delta;
-
- init_hca.eeec_base_addr_h = base_h;
- init_hca.eeec_base_addr_l = base_l + offset;
- offset += delta;
-
- init_hca.eqc_base_addr_h = base_h;
- init_hca.eqc_base_addr_l = base_l + offset;
- init_hca.log_num_of_eq = LOG2_EQS;
- offset += delta;
-
- init_hca.rdb_base_addr_h = base_h;
- init_hca.rdb_base_addr_l = base_l + offset;
- offset += delta;
-
- init_hca.mc_base_addr_h = base_h;
- init_hca.mc_base_addr_l = base_l + offset;
- init_hca.log_mc_table_entry_sz = LOG2_MC_ENTRY;
- init_hca.mc_table_hash_sz = 0;
- init_hca.log_mc_table_sz = LOG2_MC_GROUPS;
- offset += delta;
-
- init_hca.mpt_base_addr_h = base_h;
- init_hca.mpt_base_addr_l = base_l + offset;
- init_hca.log_mpt_sz = dev_lim.log2_rsvd_mrws + 1;
- offset += delta;
-
- init_hca.mtt_base_addr_h = base_h;
- init_hca.mtt_base_addr_l = base_l + offset;
-
- /* this buffer is used for all the commands */
- inprm = (void *)dev_buffers_p->inprm_buf;
- /* excute init_hca command */
- prep_init_hca_buf(&init_hca, inprm);
-
- rc = cmd_init_hca(inprm, MT_STRUCT_SIZE(tavorprm_init_hca_st));
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_sys_en;
- } else
- tprintf("cmd_init_hca() success");
-
- /* register a single memory region which covers
- 4 GB of the address space which will be used
- throughout the driver */
- memset(inprm, 0, SW2HW_MPT_IBUF_SZ);
- in_key = MKEY_PREFIX + (1 << dev_lim.log2_rsvd_mrws);
- prep_sw2hw_mpt_buf(inprm, in_key);
- rc = cmd_sw2hw_mpt(&key, in_key, inprm, SW2HW_MPT_IBUF_SZ);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_init_hca;
- } else {
- tprintf("cmd_sw2hw_mpt() success, key=0x%lx", key);
- }
- dev_ib_data.mkey = key;
-
- eqn = EQN;
- /* allocate a single EQ which will receive
- all the events */
- eq_buf = dev_buffers_p->eq_buf;
- init_eq_buf(eq_buf); /* put in HW ownership */
- prep_sw2hw_eq_buf(inprm, eq_buf);
- rc = cmd_sw2hw_eq(SW2HW_EQ_IBUF_SZ);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_sw2hw_mpt;
- } else
- tprintf("cmd_sw2hw_eq() success");
-
- event_mask = (1 << XDEV_EV_TYPE_CQ_COMP) |
- (1 << XDEV_EV_TYPE_CQ_ERR) |
- (1 << XDEV_EV_TYPE_LOCAL_WQ_CATAS_ERR) |
- (1 << XDEV_EV_TYPE_PORT_ERR) |
- (1 << XDEV_EV_TYPE_LOCAL_WQ_INVALID_REQ_ERR) |
- (1 << XDEV_EV_TYPE_LOCAL_WQ_ACCESS_VIOL_ERR) |
- (1 << TAVOR_IF_EV_TYPE_OVERRUN);
- rc = cmd_map_eq(eqn, event_mask, 1);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_sw2hw_eq;
- } else
- tprintf("cmd_map_eq() success");
-
- dev_ib_data.eq.eqn = eqn;
- dev_ib_data.eq.eq_buf = eq_buf;
- dev_ib_data.eq.cons_idx = 0;
- dev_ib_data.eq.eq_size = 1 << LOG2_EQ_SZ;
- *eq_p = &dev_ib_data.eq;
-
- memset(inprm, 0, INIT_IB_IBUF_SZ);
- prep_init_ib_buf(inprm);
- rc = cmd_init_ib(port, inprm, INIT_IB_IBUF_SZ);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_sw2hw_eq;
- } else
- tprintf("cmd_init_ib() success");
-
- init_av_array();
- tprintf("init_av_array() done");
-
- goto exit;
-
- undo_sw2hw_eq:
- rc = cmd_hw2sw_eq(EQN);
- if (rc) {
- eprintf("");
- } else
- tprintf("cmd_hw2sw_eq() success");
-
- undo_sw2hw_mpt:
- rc = cmd_hw2sw_mpt(key);
- if (rc)
- eprintf("");
- else
- tprintf("cmd_hw2sw_mpt() success key=0x%lx", key);
-
- undo_init_hca:
- rc = cmd_close_hca(0);
- if (rc) {
- eprintf("");
- goto undo_sys_en;
- } else
- tprintf("cmd_close_hca() success");
-
- undo_sys_en:
- rc = cmd_sys_dis();
- if (rc) {
- eprintf("");
- goto undo_sys_en;
- } else
- tprintf("cmd_sys_dis() success");
- goto exit;
-
- exit:
- return ret;
-}
-
-static void *get_inprm_buf(void)
-{
- return dev_buffers_p->inprm_buf;
-}
-
-static void *get_outprm_buf(void)
-{
- return dev_buffers_p->outprm_buf;
-}
-
-static void *get_send_wqe_buf(void *wqe, __u8 index)
-{
- struct ud_send_wqe_st *snd_wqe = wqe;
-
- return bus_to_virt(snd_wqe->mpointer[index].local_addr_l);
-}
-
-static void *get_rcv_wqe_buf(void *wqe, __u8 index)
-{
- struct recv_wqe_st *rcv_wqe = wqe;
-
- return bus_to_virt(be32_to_cpu(rcv_wqe->mpointer[index].local_addr_l));
-}
-
-static void modify_av_params(struct ud_av_st *av,
- __u16 dlid,
- __u8 g,
- __u8 sl, __u8 rate, union ib_gid_u *gid, __u32 qpn)
-{
- memset(&av->av, 0, sizeof av->av);
- INS_FLD(dev_ib_data.port, &av->av, tavorprm_ud_address_vector_st,
- port_number);
- INS_FLD(dev_ib_data.pd, &av->av, tavorprm_ud_address_vector_st, pd);
- INS_FLD(dlid, &av->av, tavorprm_ud_address_vector_st, rlid);
- INS_FLD(g, &av->av, tavorprm_ud_address_vector_st, g);
- INS_FLD(sl, &av->av, tavorprm_ud_address_vector_st, sl);
- INS_FLD(3, &av->av, tavorprm_ud_address_vector_st, msg);
-
- if (rate >= 3)
- INS_FLD(0, &av->av, tavorprm_ud_address_vector_st, max_stat_rate); /* 4x */
- else
- INS_FLD(1, &av->av, tavorprm_ud_address_vector_st, max_stat_rate); /* 1x */
-
- cpu_to_be_buf(&av->av, sizeof(av->av));
- if (g) {
- if (gid) {
- INS_FLD(*((__u32 *) (&gid->raw[0])), &av->av,
- tavorprm_ud_address_vector_st, rgid_127_96);
- INS_FLD(*((__u32 *) (&gid->raw[4])), &av->av,
- tavorprm_ud_address_vector_st, rgid_95_64);
- INS_FLD(*((__u32 *) (&gid->raw[8])), &av->av,
- tavorprm_ud_address_vector_st, rgid_63_32);
- INS_FLD(*((__u32 *) (&gid->raw[12])), &av->av,
- tavorprm_ud_address_vector_st, rgid_31_0);
- } else {
- INS_FLD(0, &av->av, tavorprm_ud_address_vector_st,
- rgid_127_96);
- INS_FLD(0, &av->av, tavorprm_ud_address_vector_st,
- rgid_95_64);
- INS_FLD(0, &av->av, tavorprm_ud_address_vector_st,
- rgid_63_32);
- INS_FLD(0, &av->av, tavorprm_ud_address_vector_st,
- rgid_31_0);
- }
- } else {
- INS_FLD(0, &av->av, tavorprm_ud_address_vector_st, rgid_127_96);
- INS_FLD(0, &av->av, tavorprm_ud_address_vector_st, rgid_95_64);
- INS_FLD(0, &av->av, tavorprm_ud_address_vector_st, rgid_63_32);
- INS_FLD(2, &av->av, tavorprm_ud_address_vector_st, rgid_31_0);
- }
- av->dest_qp = qpn;
-}
-
-static void init_cq_buf(union cqe_st *cq_buf, __u8 num_cqes)
-{
- memset(cq_buf, 0xff, num_cqes * sizeof cq_buf[0]);
-}
-
-static int post_rcv_buf(struct udqp_st *qp, struct recv_wqe_st *rcv_wqe)
-{
- struct recv_doorbell_st dbell;
- int rc;
- __u32 tmp[2];
- struct recv_wqe_st *tmp_wqe = (struct recv_wqe_st *)tmp;
- __u32 *ptr_dst;
-
- memset(&dbell, 0, sizeof dbell);
- INS_FLD(sizeof(*rcv_wqe) >> 4, &dbell, tavorprm_receive_doorbell_st,
- nds);
- INS_FLD(virt_to_bus(rcv_wqe) >> 6, &dbell, tavorprm_receive_doorbell_st,
- nda);
- INS_FLD(qp->qpn, &dbell, tavorprm_receive_doorbell_st, qpn);
- INS_FLD(1, &dbell, tavorprm_receive_doorbell_st, credits);
-
- if (qp->last_posted_rcv_wqe) {
- memcpy(tmp, qp->last_posted_rcv_wqe, sizeof(tmp));
- be_to_cpu_buf(tmp, sizeof(tmp));
- INS_FLD(1, tmp_wqe->next, wqe_segment_next_st, dbd);
- INS_FLD(sizeof(*rcv_wqe) >> 4, tmp_wqe->next,
- wqe_segment_next_st, nds);
- INS_FLD(virt_to_bus(rcv_wqe) >> 6, tmp_wqe->next,
- wqe_segment_next_st, nda_31_6);
- /* this is not really opcode but since the struct
- is used for both send and receive, in receive this bit must be 1
- which coinsides with nopcode */
- INS_FLD(1, tmp_wqe->next, wqe_segment_next_st, nopcode);
-
- cpu_to_be_buf(tmp, sizeof(tmp));
-
- ptr_dst = (__u32 *) (qp->last_posted_rcv_wqe);
- ptr_dst[0] = tmp[0];
- ptr_dst[1] = tmp[1];
- }
- rc = cmd_post_doorbell(&dbell, POST_RCV_OFFSET);
- if (!rc) {
- qp->last_posted_rcv_wqe = rcv_wqe;
- }
-
- return rc;
-}
-
-static int post_send_req(void *qph, void *wqeh, __u8 num_gather)
-{
- struct send_doorbell_st dbell;
- int rc;
- struct udqp_st *qp = qph;
- struct ud_send_wqe_st *snd_wqe = wqeh;
- struct next_control_seg_st tmp;
- __u32 *psrc, *pdst;
- __u32 nds;
-
- tprintf("snd_wqe=0x%lx, virt_to_bus(snd_wqe)=0x%lx", snd_wqe,
- virt_to_bus(snd_wqe));
-
- memset(&dbell, 0, sizeof dbell);
- INS_FLD(XDEV_NOPCODE_SEND, &dbell, tavorprm_send_doorbell_st, nopcode);
- INS_FLD(1, &dbell, tavorprm_send_doorbell_st, f);
- INS_FLD(virt_to_bus(snd_wqe) >> 6, &dbell, tavorprm_send_doorbell_st,
- nda);
- nds =
- (sizeof(snd_wqe->next) + sizeof(snd_wqe->udseg) +
- sizeof(snd_wqe->mpointer[0]) * num_gather) >> 4;
- INS_FLD(nds, &dbell, tavorprm_send_doorbell_st, nds);
- INS_FLD(qp->qpn, &dbell, tavorprm_send_doorbell_st, qpn);
-
- tprintf("0= %lx", ((__u32 *) ((void *)(&dbell)))[0]);
- tprintf("1= %lx", ((__u32 *) ((void *)(&dbell)))[1]);
-
- if (qp->last_posted_snd_wqe) {
- memcpy(&tmp, &qp->last_posted_snd_wqe->next, sizeof tmp);
- be_to_cpu_buf(&tmp, sizeof tmp);
- INS_FLD(1, &tmp, wqe_segment_next_st, dbd);
- INS_FLD(virt_to_bus(snd_wqe) >> 6, &tmp, wqe_segment_next_st,
- nda_31_6);
- INS_FLD(nds, &tmp, wqe_segment_next_st, nds);
-
- psrc = (__u32 *) (&tmp);
- pdst = (__u32 *) (&qp->last_posted_snd_wqe->next);
- pdst[0] = htonl(psrc[0]);
- pdst[1] = htonl(psrc[1]);
- }
-
- rc = cmd_post_doorbell(&dbell, POST_SND_OFFSET);
- if (!rc) {
- qp->last_posted_snd_wqe = snd_wqe;
- }
-
- return rc;
-}
-
-static int create_mads_qp(void **qp_pp, void **snd_cq_pp, void **rcv_cq_pp)
-{
- __u8 i;
- int rc;
- struct udqp_st *qp;
-
- qp = &dev_ib_data.mads_qp;
-
- /* set the pointer to the receive WQEs buffer */
- qp->rcv_wq = dev_buffers_p->mads_qp_rcv_queue;
-
- qp->send_buf_sz = MAD_BUF_SZ;
- qp->rcv_buf_sz = MAD_BUF_SZ;
-
- qp->recv_wqe_alloc_idx = 0;
- qp->max_recv_wqes = NUM_MADS_RCV_WQES;
- qp->recv_wqe_cur_free = NUM_MADS_RCV_WQES;
-
- /* iterrate through the list */
- for (i = 0; i < NUM_MADS_RCV_WQES; ++i) {
- /* clear the WQE */
- memset(&qp->rcv_wq[i], 0, sizeof(qp->rcv_wq[i]));
-
- qp->rcv_wq[i].wqe_cont.qp = qp;
- qp->rcv_bufs[i] = ib_buffers.rcv_mad_buf[i];
- }
-
- /* set the pointer to the send WQEs buffer */
- qp->snd_wq = dev_buffers_p->mads_qp_snd_queue;
-
- qp->snd_wqe_alloc_idx = 0;
- qp->max_snd_wqes = NUM_MADS_SND_WQES;
- qp->snd_wqe_cur_free = NUM_MADS_SND_WQES;
-
- /* iterrate through the list */
- for (i = 0; i < NUM_MADS_SND_WQES; ++i) {
- /* clear the WQE */
- memset(&qp->snd_wq[i], 0, sizeof(qp->snd_wq[i]));
-
- /* link the WQE to the free list */
- qp->snd_wq[i].wqe_cont.qp = qp;
- qp->snd_bufs[i] = ib_buffers.send_mad_buf[i];
- }
-
- /* qp number and cq numbers are already set up */
- qp->snd_cq.cq_buf = dev_buffers_p->mads_snd_cq_buf;
- qp->rcv_cq.cq_buf = dev_buffers_p->mads_rcv_cq_buf;
- qp->snd_cq.num_cqes = NUM_MADS_SND_CQES;
- qp->rcv_cq.num_cqes = NUM_MADS_RCV_CQES;
- qp->qkey = GLOBAL_QKEY;
- rc = create_udqp(qp);
- if (!rc) {
- *qp_pp = qp;
- *snd_cq_pp = &qp->snd_cq;
- *rcv_cq_pp = &qp->rcv_cq;
- }
-
- return rc;
-}
-
-static int create_ipoib_qp(void **qp_pp,
- void **snd_cq_pp, void **rcv_cq_pp, __u32 qkey)
-{
- __u8 i;
- int rc;
- struct udqp_st *qp;
- qp = &dev_ib_data.ipoib_qp;
-
- /* set the pointer to the receive WQEs buffer */
- qp->rcv_wq = dev_buffers_p->ipoib_qp_rcv_queue;
-
- qp->rcv_buf_sz = IPOIB_RCV_BUF_SZ;
-
- qp->recv_wqe_alloc_idx = 0;
- qp->max_recv_wqes = NUM_IPOIB_RCV_WQES;
- qp->recv_wqe_cur_free = NUM_IPOIB_RCV_WQES;
-
- /* iterrate through the list */
- for (i = 0; i < NUM_IPOIB_RCV_WQES; ++i) {
- /* clear the WQE */
- memset(&qp->rcv_wq[i], 0, sizeof(qp->rcv_wq[i]));
-
- /* update data */
- qp->rcv_wq[i].wqe_cont.qp = qp;
- qp->rcv_bufs[i] = ib_buffers.ipoib_rcv_buf[i];
- tprintf("rcv_buf=%lx", qp->rcv_bufs[i]);
- }
-
- /* init send queue WQEs list */
- /* set the list empty */
- qp->snd_wqe_alloc_idx = 0;
- qp->max_snd_wqes = NUM_IPOIB_SND_WQES;
- qp->snd_wqe_cur_free = NUM_IPOIB_SND_WQES;
-
- /* set the pointer to the send WQEs buffer */
- qp->snd_wq = dev_buffers_p->ipoib_qp_snd_queue;
-
- /* iterrate through the list */
- for (i = 0; i < NUM_IPOIB_SND_WQES; ++i) {
- /* clear the WQE */
- memset(&qp->snd_wq[i], 0, sizeof(qp->snd_wq[i]));
-
- /* update data */
- qp->snd_wq[i].wqe_cont.qp = qp;
- qp->snd_bufs[i] = ib_buffers.send_ipoib_buf[i];
- qp->send_buf_sz = 4;
- }
-
- /* qp number and cq numbers are already set up */
-
- qp->snd_cq.cq_buf = dev_buffers_p->ipoib_snd_cq_buf;
- qp->rcv_cq.cq_buf = dev_buffers_p->ipoib_rcv_cq_buf;
- qp->snd_cq.num_cqes = NUM_IPOIB_SND_CQES;
- qp->rcv_cq.num_cqes = NUM_IPOIB_RCV_CQES;
- qp->qkey = qkey;
- rc = create_udqp(qp);
- if (!rc) {
- *qp_pp = qp;
- *snd_cq_pp = &qp->snd_cq;
- *rcv_cq_pp = &qp->rcv_cq;
- }
-
- return rc;
-}
-
-static int create_udqp(struct udqp_st *qp)
-{
- int rc, ret = 0;
- void *inprm;
- struct recv_wqe_st *rcv_wqe;
-
- inprm = dev_buffers_p->inprm_buf;
-
- /* create send CQ */
- init_cq_buf(qp->snd_cq.cq_buf, qp->snd_cq.num_cqes);
- qp->snd_cq.cons_idx = 0;
- memset(inprm, 0, SW2HW_CQ_IBUF_SZ);
- prep_sw2hw_cq_buf(inprm, dev_ib_data.eq.eqn, qp->snd_cq.cqn,
- qp->snd_cq.cq_buf);
- rc = cmd_sw2hw_cq(qp->snd_cq.cqn, inprm, SW2HW_CQ_IBUF_SZ);
- if (rc) {
- ret = -1;
- eprintf("");
- goto exit;
- }
-
- /* create receive CQ */
- init_cq_buf(qp->rcv_cq.cq_buf, qp->rcv_cq.num_cqes);
- qp->rcv_cq.cons_idx = 0;
- memset(inprm, 0, SW2HW_CQ_IBUF_SZ);
- prep_sw2hw_cq_buf(inprm, dev_ib_data.eq.eqn, qp->rcv_cq.cqn,
- qp->rcv_cq.cq_buf);
- rc = cmd_sw2hw_cq(qp->rcv_cq.cqn, inprm, SW2HW_CQ_IBUF_SZ);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_snd_cq;
- }
-
- memset(inprm, 0, QPCTX_IBUF_SZ);
- prep_rst2init_qpee_buf(inprm, qp->snd_cq.cqn, qp->rcv_cq.cqn, qp->qkey);
- rc = cmd_rst2init_qpee(qp->qpn, inprm, QPCTX_IBUF_SZ);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_rcv_cq;
- }
-
- qp->last_posted_rcv_wqe = NULL;
- qp->last_posted_snd_wqe = NULL;
-
- /* post all the buffers to the receive queue */
- while (1) {
- /* allocate wqe */
- rcv_wqe = alloc_rcv_wqe(qp);
- if (!rcv_wqe)
- break;
-
- /* post the buffer */
- rc = post_rcv_buf(qp, rcv_wqe);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_rcv_cq;
- }
- }
-
- memset(inprm, 0, QPCTX_IBUF_SZ);
- prep_init2rtr_qpee_buf(inprm);
- rc = cmd_init2rtr_qpee(qp->qpn, inprm, QPCTX_IBUF_SZ);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_rcv_cq;
- }
-
- memset(inprm, 0, QPCTX_IBUF_SZ);
- rc = cmd_rtr2rts_qpee(qp->qpn, inprm, QPCTX_IBUF_SZ);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_rcv_cq;
- }
-
- goto exit;
-
- undo_rcv_cq:
- rc = cmd_hw2sw_cq(qp->rcv_cq.cqn);
- if (rc)
- eprintf("");
-
- undo_snd_cq:
- rc = cmd_hw2sw_cq(qp->snd_cq.cqn);
- if (rc)
- eprintf("");
-
- exit:
- return ret;
-}
-
-static int destroy_udqp(struct udqp_st *qp)
-{
- int rc;
-
- rc = cmd_2err_qpee(qp->qpn);
- if (rc) {
- eprintf("");
- return rc;
- }
- tprintf("cmd_2err_qpee(0x%lx) success", qp->qpn);
-
- rc = cmd_2rst_qpee(qp->qpn);
- if (rc) {
- eprintf("");
- return rc;
- }
- tprintf("cmd_2rst_qpee(0x%lx) success", qp->qpn);
-
- rc = cmd_hw2sw_cq(qp->rcv_cq.cqn);
- if (rc) {
- eprintf("");
- return rc;
- }
- tprintf("cmd_hw2sw_cq(0x%lx) success", qp->snd_cq.cqn);
-
- rc = cmd_hw2sw_cq(qp->snd_cq.cqn);
- if (rc) {
- eprintf("");
- return rc;
- }
- tprintf("cmd_hw2sw_cq(0x%lx) success", qp->rcv_cq.cqn);
-
- return rc;
-}
-
-static void prep_send_wqe_buf(void *qph,
- void *avh,
- void *wqeh,
- const void *buf,
- unsigned int offset, __u16 len, __u8 e)
-{
- struct udqp_st *qp = qph;
- struct ud_av_st *av = avh;
- struct ud_send_wqe_st *wqe = wqeh;
-
- INS_FLD(e, wqe->next.control, wqe_segment_ctrl_send_st, e);
- INS_FLD(1, wqe->next.control, wqe_segment_ctrl_send_st, always1);
-
- wqe->udseg.av_add_h = 0;
- wqe->udseg.av_add_l = virt_to_bus(&av->av);
- wqe->udseg.dest_qp = av->dest_qp;
- wqe->udseg.lkey = dev_ib_data.mkey;
- wqe->udseg.qkey = qp->qkey;
-
- if (buf) {
- memcpy(bus_to_virt(wqe->mpointer[0].local_addr_l) + offset, buf,
- len);
- len += offset;
- }
- wqe->mpointer[0].byte_count = len;
- wqe->mpointer[0].lkey = dev_ib_data.mkey;
-
- cpu_to_be_buf(wqe, sizeof *wqe);
-}
-
-static void *alloc_ud_av(void)
-{
- u8 next_free;
-
- if (dev_ib_data.udav.udav_next_free == FL_EOL) {
- return NULL;
- }
-
- next_free = dev_ib_data.udav.udav_next_free;
- dev_ib_data.udav.udav_next_free =
- dev_buffers_p->av_array[next_free].ud_av.next_free;
- tprintf("allocated udav %d", next_free);
- return &dev_buffers_p->av_array[next_free].ud_av;
-}
-
-static void free_ud_av(void *avh)
-{
- union ud_av_u *avu;
- __u8 idx, old_idx;
- struct ud_av_st *av = avh;
-
- avu = (union ud_av_u *)av;
-
- idx = avu - dev_buffers_p->av_array;
- tprintf("freeing udav idx=%d", idx);
- old_idx = dev_ib_data.udav.udav_next_free;
- dev_ib_data.udav.udav_next_free = idx;
- avu->ud_av.next_free = old_idx;
-}
-
-static int update_cq_cons_idx(struct cq_st *cq)
-{
- struct cq_dbell_st dbell;
- int rc;
-
- memset(&dbell, 0, sizeof dbell);
- INS_FLD(cq->cqn, &dbell, tavorprm_cq_cmd_doorbell_st, cqn);
- INS_FLD(CQ_DBELL_CMD_INC_CONS_IDX, &dbell, tavorprm_cq_cmd_doorbell_st,
- cq_cmd);
- rc = cmd_post_doorbell(&dbell, CQ_DBELL_OFFSET);
- return rc;
-}
-
-static int poll_cq(void *cqh, union cqe_st *cqe_p, u8 * num_cqes)
-{
- union cqe_st cqe;
- int rc;
- u32 *ptr;
- struct cq_st *cq = cqh;
-
- if (cq->cqn < 0x80 || cq->cqn > 0x83) {
- eprintf("");
- return -1;
- }
- ptr = (u32 *) (&(cq->cq_buf[cq->cons_idx]));
- barrier();
- if ((ptr[7] & 0x80000000) == 0) {
- cqe = cq->cq_buf[cq->cons_idx];
- be_to_cpu_buf(&cqe, sizeof(cqe));
- *cqe_p = cqe;
- ptr[7] = 0x80000000;
- barrier();
- cq->cons_idx = (cq->cons_idx + 1) % cq->num_cqes;
- rc = update_cq_cons_idx(cq);
- if (rc) {
- return rc;
- }
- *num_cqes = 1;
- } else
- *num_cqes = 0;
-
- return 0;
-}
-
-static void dev2ib_cqe(struct ib_cqe_st *ib_cqe_p, union cqe_st *cqe_p)
-{
- __u8 opcode;
- __u32 wqe_addr_ba;
-
- opcode =
- EX_FLD(cqe_p->good_cqe, tavorprm_completion_queue_entry_st, opcode);
- if (opcode >= CQE_ERROR_OPCODE)
- ib_cqe_p->is_error = 1;
- else
- ib_cqe_p->is_error = 0;
-
- ib_cqe_p->is_send =
- EX_FLD(cqe_p->good_cqe, tavorprm_completion_queue_entry_st, s);
- wqe_addr_ba =
- EX_FLD(cqe_p->good_cqe, tavorprm_completion_queue_entry_st,
- wqe_adr) << 6;
- ib_cqe_p->wqe = bus_to_virt(wqe_addr_ba);
-
-// if (ib_cqe_p->is_send) {
-// be_to_cpu_buf(ib_cqe_p->wqe, sizeof(struct ud_send_wqe_st));
-// }
-// else {
-// be_to_cpu_buf(ib_cqe_p->wqe, sizeof(struct recv_wqe_st));
-// }
- ib_cqe_p->count =
- EX_FLD(cqe_p->good_cqe, tavorprm_completion_queue_entry_st,
- byte_cnt);
-}
-
-static int ib_poll_cq(void *cqh, struct ib_cqe_st *ib_cqe_p, u8 * num_cqes)
-{
- int rc;
- union cqe_st cqe;
- struct cq_st *cq = cqh;
- __u8 opcode;
-
- rc = poll_cq(cq, &cqe, num_cqes);
- if (rc || ((*num_cqes) == 0)) {
- return rc;
- }
-
- dev2ib_cqe(ib_cqe_p, &cqe);
-
- opcode =
- EX_FLD(cqe.good_cqe, tavorprm_completion_queue_entry_st, opcode);
- if (opcode >= CQE_ERROR_OPCODE) {
- struct ud_send_wqe_st *wqe_p, wqe;
- __u32 *ptr;
- unsigned int i;
-
- wqe_p =
- bus_to_virt(EX_FLD
- (cqe.error_cqe,
- tavorprm_completion_with_error_st,
- wqe_addr) << 6);
- eprintf("syndrome=0x%lx",
- EX_FLD(cqe.error_cqe, tavorprm_completion_with_error_st,
- syndrome));
- eprintf("wqe_addr=0x%lx", wqe_p);
- eprintf("wqe_size=0x%lx",
- EX_FLD(cqe.error_cqe, tavorprm_completion_with_error_st,
- wqe_size));
- eprintf("myqpn=0x%lx",
- EX_FLD(cqe.error_cqe, tavorprm_completion_with_error_st,
- myqpn));
- eprintf("db_cnt=0x%lx",
- EX_FLD(cqe.error_cqe, tavorprm_completion_with_error_st,
- db_cnt));
- memcpy(&wqe, wqe_p, sizeof wqe);
- be_to_cpu_buf(&wqe, sizeof wqe);
-
- eprintf("dumping wqe...");
- ptr = (__u32 *) (&wqe);
- for (i = 0; i < sizeof wqe; i += 4) {
- printf("%lx : ", ptr[i >> 2]);
- }
-
- }
-
- return rc;
-}
-
-/* always work on ipoib qp */
-static int add_qp_to_mcast_group(union ib_gid_u mcast_gid, __u8 add)
-{
- void *mg;
- __u8 *tmp;
- int rc;
- __u16 mgid_hash;
- void *mgmqp_p;
-
- tmp = dev_buffers_p->inprm_buf;
- memcpy(tmp, mcast_gid.raw, 16);
- be_to_cpu_buf(tmp, 16);
- rc = cmd_mgid_hash(tmp, &mgid_hash);
- if (!rc) {
- mg = (void *)dev_buffers_p->inprm_buf;
- memset(mg, 0, MT_STRUCT_SIZE(tavorprm_mgm_entry_st));
- INS_FLD(mcast_gid.as_u32.dw[0], mg, tavorprm_mgm_entry_st, mgid_128_96); // memcpy(&mg->mgid_128_96, &mcast_gid.raw[0], 4);
- INS_FLD(mcast_gid.as_u32.dw[1], mg, tavorprm_mgm_entry_st, mgid_95_64); // memcpy(&mg->mgid_95_64, &mcast_gid.raw[4], 4);
- INS_FLD(mcast_gid.as_u32.dw[2], mg, tavorprm_mgm_entry_st, mgid_63_32); //memcpy(&mg->mgid_63_32, &mcast_gid.raw[8], 4);
- INS_FLD(mcast_gid.as_u32.dw[3], mg, tavorprm_mgm_entry_st, mgid_31_0); //memcpy(&mg->mgid_31_0, &mcast_gid.raw[12], 4);
- be_to_cpu_buf(mg + MT_BYTE_OFFSET(tavorprm_mgm_entry_st, mgid_128_96), 16); //be_to_cpu_buf(&mg->mgid_128_96, 16);
- mgmqp_p = mg + MT_BYTE_OFFSET(tavorprm_mgm_entry_st, mgmqp_0);
- INS_FLD(dev_ib_data.ipoib_qp.qpn, mgmqp_p, tavorprm_mgmqp_st, qpn_i); //mg->mgmqp[0].qpn = dev_ib_data.ipoib_qp.qpn;
- INS_FLD(add, mgmqp_p, tavorprm_mgmqp_st, qi); //mg->mgmqp[0].valid = add ? 1 : 0;
- rc = cmd_write_mgm(mg, mgid_hash);
- }
- return rc;
-}
-
-static int clear_interrupt(void)
-{
- __u32 ecr;
- int ret = 0;
-
- if (gw_read_cr(0x80704, &ecr)) {
- eprintf("");
- } else {
- if (ecr) {
- ret = 1;
- }
- }
- gw_write_cr(0xf00d8, 0x80000000); /* clear int */
- gw_write_cr(0x8070c, 0xffffffff);
-
- return ret;
-}
-
-static struct ud_send_wqe_st *alloc_send_wqe(udqp_t qph)
-{
- struct udqp_st *qp = qph;
- __u8 new_entry;
- struct ud_send_wqe_st *wqe;
-
- if (qp->snd_wqe_cur_free == 0) {
- return NULL;
- }
- new_entry = qp->snd_wqe_alloc_idx;
-
- wqe = &qp->snd_wq[new_entry].wqe;
- qp->snd_wqe_cur_free--;
- qp->snd_wqe_alloc_idx = (qp->snd_wqe_alloc_idx + 1) % qp->max_snd_wqes;
-
- memset(wqe, 0, sizeof *wqe);
-
- wqe->mpointer[0].local_addr_l = virt_to_bus(qp->snd_bufs[new_entry]);
-
- return wqe;
-}
-
-/*
- * alloc_rcv_wqe
- *
- * Note: since we work directly on the work queue, wqes
- * are left in big endian
- */
-static struct recv_wqe_st *alloc_rcv_wqe(struct udqp_st *qp)
-{
- __u8 new_entry;
- struct recv_wqe_st *wqe;
-
- if (qp->recv_wqe_cur_free == 0) {
- return NULL;
- }
-
- new_entry = qp->recv_wqe_alloc_idx;
- wqe = &qp->rcv_wq[new_entry].wqe;
-
- qp->recv_wqe_cur_free--;
- qp->recv_wqe_alloc_idx =
- (qp->recv_wqe_alloc_idx + 1) % qp->max_recv_wqes;
-
- memset(wqe, 0, sizeof *wqe);
-
- /* GRH is always required */
- wqe->mpointer[0].local_addr_h = 0;
- wqe->mpointer[0].local_addr_l = virt_to_bus(qp->rcv_bufs[new_entry]);
- wqe->mpointer[0].lkey = dev_ib_data.mkey;
- wqe->mpointer[0].byte_count = GRH_SIZE;
-
- wqe->mpointer[1].local_addr_h = 0;
- wqe->mpointer[1].local_addr_l =
- virt_to_bus(qp->rcv_bufs[new_entry] + GRH_SIZE);
- wqe->mpointer[1].lkey = dev_ib_data.mkey;
- wqe->mpointer[1].byte_count = qp->rcv_buf_sz;
-
- tprintf("rcv_buf=%lx\n", qp->rcv_bufs[new_entry]);
-
- /* we do it only on the data segment since the control
- segment is always owned by HW */
- cpu_to_be_buf(wqe, sizeof *wqe);
-
-// tprintf("alloc wqe= 0x%x", wqe);
- return wqe;
-}
-
-static int free_send_wqe(struct ud_send_wqe_st *wqe)
-{
- union ud_send_wqe_u *wqe_u;
- struct udqp_st *qp;
-
- wqe_u = (union ud_send_wqe_u *)wqe;
- qp = wqe_u->wqe_cont.qp;
-
- if (qp->snd_wqe_cur_free >= qp->max_snd_wqes) {
- return -1;
- }
-
- qp->snd_wqe_cur_free++;
-
- return 0;
-}
-
-static int free_rcv_wqe(struct recv_wqe_st *wqe)
-{
- union recv_wqe_u *wqe_u;
- struct udqp_st *qp;
-
- wqe_u = (union recv_wqe_u *)wqe;
- qp = wqe_u->wqe_cont.qp;
-
- if (qp->recv_wqe_cur_free >= qp->max_recv_wqes) {
- return -1;
- }
-
- qp->recv_wqe_cur_free++;
-
- return 0;
-}
-
-static int free_wqe(void *wqe)
-{
- int rc = 0;
- struct recv_wqe_st *rcv_wqe;
-
-// tprintf("free wqe= 0x%x", wqe);
- if ((wqe >= (void *)(dev_ib_data.ipoib_qp.rcv_wq)) &&
- (wqe <
- (void *)(&dev_ib_data.ipoib_qp.rcv_wq[NUM_IPOIB_RCV_WQES]))) {
- /* ipoib receive wqe */
- free_rcv_wqe(wqe);
- rcv_wqe = alloc_rcv_wqe(&dev_ib_data.ipoib_qp);
- if (rcv_wqe) {
- rc = post_rcv_buf(&dev_ib_data.ipoib_qp, rcv_wqe);
- if (rc) {
- eprintf("");
- }
- }
- } else if (wqe >= (void *)(dev_ib_data.ipoib_qp.snd_wq) &&
- wqe <
- (void *)(&dev_ib_data.ipoib_qp.snd_wq[NUM_IPOIB_SND_WQES])) {
- /* ipoib send wqe */
- free_send_wqe(wqe);
- } else if (wqe >= (void *)(dev_ib_data.mads_qp.rcv_wq) &&
- wqe <
- (void *)(&dev_ib_data.mads_qp.rcv_wq[NUM_MADS_RCV_WQES])) {
- /* mads receive wqe */
- free_rcv_wqe(wqe);
- rcv_wqe = alloc_rcv_wqe(&dev_ib_data.mads_qp);
- if (rcv_wqe) {
- rc = post_rcv_buf(&dev_ib_data.mads_qp, rcv_wqe);
- if (rc) {
- eprintf("");
- }
- }
- } else if (wqe >= (void *)(dev_ib_data.mads_qp.snd_wq) &&
- wqe <
- (void *)(&dev_ib_data.mads_qp.snd_wq[NUM_MADS_SND_WQES])) {
- /* mads send wqe */
- free_send_wqe(wqe);
- } else {
- rc = -1;
- eprintf("");
- }
-
- return rc;
-}
-
-static int update_eq_cons_idx(struct eq_st *eq)
-{
- struct eq_dbell_st dbell;
- int rc;
-
- memset(&dbell, 0, sizeof dbell);
- INS_FLD(dev_ib_data.eq.eqn, &dbell, tavorprm_eq_cmd_doorbell_st, eqn);
- INS_FLD(EQ_DBELL_CMD_SET_CONS_IDX, &dbell, tavorprm_eq_cmd_doorbell_st,
- eq_cmd);
- INS_FLD(eq->cons_idx, &dbell, tavorprm_eq_cmd_doorbell_st, eq_param);
- rc = cmd_post_doorbell(&dbell, EQ_DBELL_OFFSET);
-
- return rc;
-}
-
-static void dev2ib_eqe(struct ib_eqe_st *ib_eqe_p, void *eqe_p)
-{
- void *tmp;
-
- ib_eqe_p->event_type =
- EX_FLD(eqe_p, tavorprm_event_queue_entry_st, event_type);
-
- tmp = eqe_p + MT_BYTE_OFFSET(tavorprm_event_queue_entry_st, event_data);
- ib_eqe_p->cqn = EX_FLD(tmp, tavorprm_completion_event_st, cqn);
-}
-
-static int poll_eq(struct ib_eqe_st *ib_eqe_p, __u8 * num_eqes)
-{
- struct eqe_t eqe;
- __u8 owner;
- int rc;
- __u32 *ptr;
- struct eq_st *eq = &dev_ib_data.eq;
-
- ptr = (__u32 *) (&(eq->eq_buf[eq->cons_idx]));
- tprintf("cons)idx=%d, addr(eqe)=%x, val=0x%x", eq->cons_idx, virt_to_bus(ptr), ptr[7]);
- owner = (ptr[7] & 0x80000000) ? OWNER_HW : OWNER_SW;
- if (owner == OWNER_SW) {
- tprintf("got eqe");
- eqe = eq->eq_buf[eq->cons_idx];
- be_to_cpu_buf(&eqe, sizeof(eqe));
- dev2ib_eqe(ib_eqe_p, &eqe);
- ptr[7] |= 0x80000000;
- eq->eq_buf[eq->cons_idx] = eqe;
- eq->cons_idx = (eq->cons_idx + 1) % eq->eq_size;
- rc = update_eq_cons_idx(eq);
- if (rc) {
- return -1;
- }
- *num_eqes = 1;
- } else {
- *num_eqes = 0;
- }
- return 0;
-}
-
-static int ib_device_close(void)
-{
- iounmap(tavor_pci_dev.uar);
- iounmap(tavor_pci_dev.cr_space);
- iounmap(dev_ib_data.error_buf_addr);
- return 0;
-}
-
-static __u32 dev_get_qpn(void *qph)
-{
- struct udqp_st *qp = qph;
-
- return qp->qpn;
-}
-
-static void dev_post_dbell(void *dbell, __u32 offset)
-{
- __u32 *ptr;
- unsigned long address;
-
- ptr = dbell;
- tprintf("ptr[0]= 0x%lx", ptr[0]);
- tprintf("ptr[1]= 0x%lx", ptr[1]);
- address = (unsigned long)(tavor_pci_dev.uar) + offset;
- tprintf("va=0x%lx pa=0x%lx", address,
- virt_to_bus((const void *)address));
- writel(htonl(ptr[0]), tavor_pci_dev.uar + offset);
- barrier();
- address += 4;
- tprintf("va=0x%lx pa=0x%lx", address,
- virt_to_bus((const void *)address));
- writel(htonl(ptr[1]), tavor_pci_dev.uar + offset + 4);
-}
-
-
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-
-#include "mt25218.h"
-#include "ib_driver.h"
-#include <gpxe/pci.h>
-
-#define MOD_INC(counter, max_count) (counter) = ((counter)+1) & ((max_count) - 1)
-
-#define breakpoint {volatile __u32 *p=(__u32 *)0x1234;printf("breakpoint\n");do {} while((*p) != 0x1234);}
-
-#define WRITE_BYTE_VOL(addr, off, val) \
- do { \
- (*((volatile __u8 *)(((volatile __u8 *)(addr)) + off))) = (val); \
- } while(0)
-
-#define WRITE_WORD_VOL(addr, off, val) \
- do { \
- (*((volatile __u16 *)(((volatile __u8 *)(addr)) + off))) = (val); \
- } while(0)
-
-#define WRITE_DWORD_VOL(addr, off, val) \
- do { \
- (*((volatile __u32 *)(((volatile __u8 *)(addr)) + off))) = (val); \
- } while(0)
-
-struct device_buffers_st {
- /* inprm and outprm do not have alignnemet constraint sice that
- is acheived programatically */
- u8 inprm_buf[INPRM_BUF_SZ];
- u8 outprm_buf[OUTPRM_BUF_SZ];
- union recv_wqe_u mads_qp_rcv_queue[NUM_MADS_RCV_WQES]
- __attribute__ ((aligned(RECV_WQE_U_ALIGN)));
- union recv_wqe_u ipoib_qp_rcv_queue[NUM_IPOIB_RCV_WQES]
- __attribute__ ((aligned(RECV_WQE_U_ALIGN)));
- union ud_send_wqe_u mads_qp_snd_queue[NUM_MADS_SND_WQES]
- __attribute__ ((aligned(UD_SEND_WQE_U_ALIGN)));
- union ud_send_wqe_u ipoib_qp_snd_queue[NUM_IPOIB_SND_WQES]
- __attribute__ ((aligned(UD_SEND_WQE_U_ALIGN)));
- struct eqe_t eq_buf[1 << LOG2_EQ_SZ]
- __attribute__ ((aligned(sizeof(struct eqe_t))));
- union cqe_st mads_snd_cq_buf[NUM_MADS_SND_CQES]
- __attribute__ ((aligned(sizeof(union cqe_st))));
- union cqe_st ipoib_snd_cq_buf[NUM_IPOIB_SND_CQES]
- __attribute__ ((aligned(sizeof(union cqe_st))));
- union cqe_st mads_rcv_cq_buf[NUM_MADS_RCV_CQES]
- __attribute__ ((aligned(sizeof(union cqe_st))));
- union cqe_st ipoib_rcv_cq_buf[NUM_IPOIB_RCV_CQES]
- __attribute__ ((aligned(sizeof(union cqe_st))));
- union ud_av_u av_array[NUM_AVS];
-} __attribute__ ((packed));
-
-#define STRUCT_ALIGN_SZ 4096
-#define SRC_BUF_SZ (sizeof(struct device_buffers_st) + STRUCT_ALIGN_SZ - 1)
-
-/* the following must be kept in this order
- for the memory region to cover the buffers */
-static u8 src_buf[SRC_BUF_SZ];
-static struct ib_buffers_st ib_buffers;
-static __u32 memreg_size;
-/* end of order constraint */
-
-struct phys_mem_desc_st {
- unsigned long base;
- unsigned long offset;
-};
-
-static struct phys_mem_desc_st phys_mem;
-
-static struct dev_pci_struct memfree_pci_dev;
-static struct device_buffers_st *dev_buffers_p;
-static struct device_ib_data_st dev_ib_data;
-
-static int gw_write_cr(__u32 addr, __u32 data)
-{
- writel(htonl(data), memfree_pci_dev.cr_space + addr);
- return 0;
-}
-
-static int gw_read_cr(__u32 addr, __u32 * result)
-{
- *result = ntohl(readl(memfree_pci_dev.cr_space + addr));
- return 0;
-}
-
-static int reset_hca(void)
-{
- return gw_write_cr(MEMFREE_RESET_OFFSET, 1);
-}
-
-static int ib_device_init(struct pci_device *dev)
-{
- int i;
- int rc;
-
- tprintf("");
-
- memset(&dev_ib_data, 0, sizeof dev_ib_data);
-
- /* save bars */
- tprintf("bus=%d devfn=0x%x", dev->bus, dev->devfn);
- for (i = 0; i < 6; ++i) {
- memfree_pci_dev.dev.bar[i] =
- pci_bar_start(dev, PCI_BASE_ADDRESS_0 + (i << 2));
- tprintf("bar[%d]= 0x%08lx", i, memfree_pci_dev.dev.bar[i]);
- }
-
- tprintf("");
- /* save config space */
- for (i = 0; i < 64; ++i) {
- rc = pci_read_config_dword(dev, i << 2,
- &memfree_pci_dev.dev.
- dev_config_space[i]);
- if (rc) {
- eprintf("");
- return rc;
- }
- tprintf("config[%d]= 0x%08lx", i << 2,
- memfree_pci_dev.dev.dev_config_space[i]);
- }
-
- tprintf("");
- memfree_pci_dev.dev.dev = dev;
-
- /* map cr-space */
- memfree_pci_dev.cr_space =
- ioremap(memfree_pci_dev.dev.bar[0], 0x100000);
- if (!memfree_pci_dev.cr_space) {
- eprintf("");
- return -1;
- }
-
- /* map uar */
- memfree_pci_dev.uar =
- ioremap(memfree_pci_dev.dev.bar[2] + UAR_IDX * 0x1000, 0x1000);
- if (!memfree_pci_dev.uar) {
- eprintf("");
- return -1;
- }
- tprintf("uar_base (pa:va) = 0x%lx 0x%lx",
- memfree_pci_dev.dev.bar[2] + UAR_IDX * 0x1000,
- memfree_pci_dev.uar);
-
- tprintf("");
-
- return 0;
-}
-
-static inline unsigned long lalign(unsigned long buf, unsigned long align)
-{
- return (unsigned long)((buf + align - 1) &
- (~(((unsigned long)align) - 1)));
-}
-
-static int init_dev_data(void)
-{
- unsigned long tmp;
- unsigned long reserve_size = 32 * 1024 * 1024;
-
- tmp = lalign(virt_to_bus(src_buf), STRUCT_ALIGN_SZ);
-
- dev_buffers_p = bus_to_virt(tmp);
- memreg_size = (__u32) (&memreg_size) - (__u32) dev_buffers_p;
- tprintf("src_buf=0x%lx, dev_buffers_p=0x%lx, memreg_size=0x%x", src_buf,
- dev_buffers_p, memreg_size);
-
- tprintf("inprm: va=0x%lx, pa=0x%lx", dev_buffers_p->inprm_buf,
- virt_to_bus(dev_buffers_p->inprm_buf));
- tprintf("outprm: va=0x%lx, pa=0x%lx", dev_buffers_p->outprm_buf,
- virt_to_bus(dev_buffers_p->outprm_buf));
-
- phys_mem.base =
- (virt_to_phys(_text) - reserve_size) & (~(reserve_size - 1));
-
- phys_mem.offset = 0;
-
- return 0;
-}
-
-static int restore_config(void)
-{
- int i;
- int rc;
-
- for (i = 0; i < 64; ++i) {
- if (i != 22 && i != 23) {
- rc = pci_write_config_dword(memfree_pci_dev.dev.dev,
- i << 2,
- memfree_pci_dev.dev.
- dev_config_space[i]);
- if (rc) {
- return rc;
- }
- }
- }
- return 0;
-}
-
-static void prep_init_hca_buf(struct init_hca_st *init_hca_p, void *buf)
-{
- unsigned long ptr;
- __u8 shift;
-
- memset(buf, 0, MT_STRUCT_SIZE(arbelprm_init_hca_st));
-
- ptr = (unsigned long)buf +
- MT_BYTE_OFFSET(arbelprm_init_hca_st,
- qpc_eec_cqc_eqc_rdb_parameters);
-
- shift = 32 - MT_BIT_SIZE(arbelprm_qpcbaseaddr_st, qpc_base_addr_l);
- INS_FLD(init_hca_p->qpc_base_addr_h, ptr, arbelprm_qpcbaseaddr_st,
- qpc_base_addr_h);
- INS_FLD(init_hca_p->qpc_base_addr_l >> shift, ptr,
- arbelprm_qpcbaseaddr_st, qpc_base_addr_l);
- INS_FLD(init_hca_p->log_num_of_qp, ptr, arbelprm_qpcbaseaddr_st,
- log_num_of_qp);
-
- shift = 32 - MT_BIT_SIZE(arbelprm_qpcbaseaddr_st, eec_base_addr_l);
- INS_FLD(init_hca_p->eec_base_addr_h, ptr, arbelprm_qpcbaseaddr_st,
- eec_base_addr_h);
- INS_FLD(init_hca_p->eec_base_addr_l >> shift, ptr,
- arbelprm_qpcbaseaddr_st, eec_base_addr_l);
- INS_FLD(init_hca_p->log_num_of_ee, ptr, arbelprm_qpcbaseaddr_st,
- log_num_of_ee);
-
- shift = 32 - MT_BIT_SIZE(arbelprm_qpcbaseaddr_st, srqc_base_addr_l);
- INS_FLD(init_hca_p->srqc_base_addr_h, ptr, arbelprm_qpcbaseaddr_st,
- srqc_base_addr_h);
- INS_FLD(init_hca_p->srqc_base_addr_l >> shift, ptr,
- arbelprm_qpcbaseaddr_st, srqc_base_addr_l);
- INS_FLD(init_hca_p->log_num_of_srq, ptr, arbelprm_qpcbaseaddr_st,
- log_num_of_srq);
-
- shift = 32 - MT_BIT_SIZE(arbelprm_qpcbaseaddr_st, cqc_base_addr_l);
- INS_FLD(init_hca_p->cqc_base_addr_h, ptr, arbelprm_qpcbaseaddr_st,
- cqc_base_addr_h);
- INS_FLD(init_hca_p->cqc_base_addr_l >> shift, ptr,
- arbelprm_qpcbaseaddr_st, cqc_base_addr_l);
- INS_FLD(init_hca_p->log_num_of_cq, ptr, arbelprm_qpcbaseaddr_st,
- log_num_of_cq);
-
- INS_FLD(init_hca_p->eqpc_base_addr_h, ptr, arbelprm_qpcbaseaddr_st,
- eqpc_base_addr_h);
- INS_FLD(init_hca_p->eqpc_base_addr_l, ptr, arbelprm_qpcbaseaddr_st,
- eqpc_base_addr_l);
-
- INS_FLD(init_hca_p->eeec_base_addr_h, ptr, arbelprm_qpcbaseaddr_st,
- eeec_base_addr_h);
- INS_FLD(init_hca_p->eeec_base_addr_l, ptr, arbelprm_qpcbaseaddr_st,
- eeec_base_addr_l);
-
- shift = 32 - MT_BIT_SIZE(arbelprm_qpcbaseaddr_st, eqc_base_addr_l);
- INS_FLD(init_hca_p->eqc_base_addr_h, ptr, arbelprm_qpcbaseaddr_st,
- eqc_base_addr_h);
- INS_FLD(init_hca_p->eqc_base_addr_l >> shift, ptr,
- arbelprm_qpcbaseaddr_st, eqc_base_addr_l);
- INS_FLD(init_hca_p->log_num_of_eq, ptr, arbelprm_qpcbaseaddr_st,
- log_num_eq);
-
- INS_FLD(init_hca_p->rdb_base_addr_h, ptr, arbelprm_qpcbaseaddr_st,
- rdb_base_addr_h);
- INS_FLD(init_hca_p->rdb_base_addr_l, ptr, arbelprm_qpcbaseaddr_st,
- rdb_base_addr_l);
-
- ptr = (unsigned long)buf +
- MT_BYTE_OFFSET(arbelprm_init_hca_st, multicast_parameters);
-
- INS_FLD(init_hca_p->mc_base_addr_h, ptr, arbelprm_multicastparam_st,
- mc_base_addr_h);
- INS_FLD(init_hca_p->mc_base_addr_l, ptr, arbelprm_multicastparam_st,
- mc_base_addr_l);
- INS_FLD(init_hca_p->log_mc_table_entry_sz, ptr,
- arbelprm_multicastparam_st, log_mc_table_entry_sz);
- INS_FLD(init_hca_p->mc_table_hash_sz, ptr, arbelprm_multicastparam_st,
- mc_table_hash_sz);
- INS_FLD(init_hca_p->log_mc_table_sz, ptr, arbelprm_multicastparam_st,
- log_mc_table_sz);
-
- ptr = (unsigned long)buf +
- MT_BYTE_OFFSET(arbelprm_init_hca_st, tpt_parameters);
-
- INS_FLD(init_hca_p->mpt_base_addr_h, ptr, arbelprm_tptparams_st,
- mpt_base_adr_h);
- INS_FLD(init_hca_p->mpt_base_addr_l, ptr, arbelprm_tptparams_st,
- mpt_base_adr_l);
- INS_FLD(init_hca_p->log_mpt_sz, ptr, arbelprm_tptparams_st, log_mpt_sz);
- INS_FLD(init_hca_p->mtt_base_addr_h, ptr, arbelprm_tptparams_st,
- mtt_base_addr_h);
- INS_FLD(init_hca_p->mtt_base_addr_l, ptr, arbelprm_tptparams_st,
- mtt_base_addr_l);
-
- ptr = (unsigned long)buf +
- MT_BYTE_OFFSET(arbelprm_init_hca_st, uar_parameters);
-
- INS_FLD(init_hca_p->log_max_uars, ptr, arbelprm_uar_params_st,
- log_max_uars);
-
-}
-
-static void prep_sw2hw_mpt_buf(void *buf, __u32 mkey)
-{
- INS_FLD(1, buf, arbelprm_mpt_st, lw);
- INS_FLD(1, buf, arbelprm_mpt_st, lr);
- INS_FLD(1, buf, arbelprm_mpt_st, pa);
- INS_FLD(1, buf, arbelprm_mpt_st, r_w);
- INS_FLD(mkey, buf, arbelprm_mpt_st, mem_key);
- INS_FLD(GLOBAL_PD, buf, arbelprm_mpt_st, pd);
- INS_FLD(virt_to_bus(dev_buffers_p), buf, arbelprm_mpt_st,
- start_address_l);
- INS_FLD(memreg_size, buf, arbelprm_mpt_st, reg_wnd_len_l);
-}
-
-static void prep_sw2hw_eq_buf(void *buf, struct eqe_t *eq_buf)
-{
- memset(buf, 0, MT_STRUCT_SIZE(arbelprm_eqc_st));
-
- INS_FLD(0xa, buf, arbelprm_eqc_st, st); /* fired */
- INS_FLD(virt_to_bus(eq_buf), buf, arbelprm_eqc_st, start_address_l);
- INS_FLD(LOG2_EQ_SZ, buf, arbelprm_eqc_st, log_eq_size);
- INS_FLD(GLOBAL_PD, buf, arbelprm_eqc_st, pd);
- INS_FLD(dev_ib_data.mkey, buf, arbelprm_eqc_st, lkey);
-}
-
-static void init_eq_buf(void *eq_buf)
-{
- struct eqe_t *eq = eq_buf;
- int i, num_eqes = 1 << LOG2_EQ_SZ;
-
- memset(eq, 0, num_eqes * sizeof eq[0]);
- for (i = 0; i < num_eqes; ++i)
- WRITE_BYTE_VOL(&eq[i], EQE_OWNER_OFFSET, EQE_OWNER_VAL_HW);
-}
-
-static void prep_init_ib_buf(void *buf)
-{
- memset(buf, 0, MT_STRUCT_SIZE(arbelprm_init_ib_st));
-
- INS_FLD(MTU_2048, buf, arbelprm_init_ib_st, mtu_cap);
- INS_FLD(3, buf, arbelprm_init_ib_st, port_width_cap);
- INS_FLD(1, buf, arbelprm_init_ib_st, vl_cap);
- INS_FLD(1, buf, arbelprm_init_ib_st, max_gid);
- INS_FLD(64, buf, arbelprm_init_ib_st, max_pkey);
-}
-
-static void prep_sw2hw_cq_buf(void *buf, __u8 eqn,
- __u32 cqn,
- union cqe_st *cq_buf,
- __u32 cq_ci_db_record, __u32 cq_state_db_record)
-{
- memset(buf, 0, MT_STRUCT_SIZE(arbelprm_completion_queue_context_st));
-
- INS_FLD(0xA, buf, arbelprm_completion_queue_context_st, st);
- INS_FLD(virt_to_bus(cq_buf), buf, arbelprm_completion_queue_context_st,
- start_address_l);
- INS_FLD(LOG2_CQ_SZ, buf, arbelprm_completion_queue_context_st,
- log_cq_size);
- INS_FLD(dev_ib_data.uar_idx, buf, arbelprm_completion_queue_context_st,
- usr_page);
- INS_FLD(eqn, buf, arbelprm_completion_queue_context_st, c_eqn);
- INS_FLD(GLOBAL_PD, buf, arbelprm_completion_queue_context_st, pd);
- INS_FLD(dev_ib_data.mkey, buf, arbelprm_completion_queue_context_st,
- l_key);
- INS_FLD(cqn, buf, arbelprm_completion_queue_context_st, cqn);
- INS_FLD(cq_ci_db_record, buf, arbelprm_completion_queue_context_st,
- cq_ci_db_record);
- INS_FLD(cq_state_db_record, buf, arbelprm_completion_queue_context_st,
- cq_state_db_record);
-}
-
-static void prep_rst2init_qpee_buf(void *buf,
- __u32 snd_cqn,
- __u32 rcv_cqn,
- __u32 qkey,
- __u32 log_rq_size,
- __u32 log_rq_stride,
- __u32 log_sq_size,
- __u32 log_sq_stride,
- __u32 snd_wqe_base_adr_l,
- __u32 snd_db_record_index,
- __u32 rcv_wqe_base_adr_l,
- __u32 rcv_db_record_index)
-{
- void *tmp;
- int shift;
- struct qp_ee_state_tarnisition_st *prm = buf;
-
- memset(buf, 0, sizeof *prm);
-
- tprintf("snd_cqn=0x%lx", snd_cqn);
- tprintf("rcv_cqn=0x%lx", rcv_cqn);
- tprintf("qkey=0x%lx", qkey);
- tprintf("log_rq_size=0x%lx", log_rq_size);
- tprintf("log_rq_stride=0x%lx", log_rq_stride);
- tprintf("log_sq_size=0x%lx", log_sq_size);
- tprintf("log_sq_stride=0x%lx", log_sq_stride);
- tprintf("snd_wqe_base_adr_l=0x%lx", snd_wqe_base_adr_l);
- tprintf("snd_db_record_index=0x%lx", snd_db_record_index);
- tprintf("rcv_wqe_base_adr_l=0x%lx", rcv_wqe_base_adr_l);
- tprintf("rcv_db_record_index=0x%lx", rcv_db_record_index);
-
- tmp = &prm->ctx;
- INS_FLD(TS_UD, tmp, arbelprm_queue_pair_ee_context_entry_st, st);
- INS_FLD(PM_STATE_MIGRATED, tmp, arbelprm_queue_pair_ee_context_entry_st,
- pm_state);
- INS_FLD(1, tmp, arbelprm_queue_pair_ee_context_entry_st, de);
- INS_FLD(MTU_2048, tmp, arbelprm_queue_pair_ee_context_entry_st, mtu);
- INS_FLD(11, tmp, arbelprm_queue_pair_ee_context_entry_st, msg_max);
- INS_FLD(log_rq_size, tmp, arbelprm_queue_pair_ee_context_entry_st,
- log_rq_size);
- INS_FLD(log_rq_stride, tmp, arbelprm_queue_pair_ee_context_entry_st,
- log_rq_stride);
- INS_FLD(log_sq_size, tmp, arbelprm_queue_pair_ee_context_entry_st,
- log_sq_size);
- INS_FLD(log_sq_stride, tmp, arbelprm_queue_pair_ee_context_entry_st,
- log_sq_stride);
- INS_FLD(dev_ib_data.uar_idx, tmp,
- arbelprm_queue_pair_ee_context_entry_st, usr_page);
- INS_FLD(GLOBAL_PD, tmp, arbelprm_queue_pair_ee_context_entry_st, pd);
- INS_FLD(dev_ib_data.mkey, tmp, arbelprm_queue_pair_ee_context_entry_st,
- wqe_lkey);
- INS_FLD(1, tmp, arbelprm_queue_pair_ee_context_entry_st, ssc);
- INS_FLD(snd_cqn, tmp, arbelprm_queue_pair_ee_context_entry_st, cqn_snd);
- shift =
- 32 - MT_BIT_SIZE(arbelprm_queue_pair_ee_context_entry_st,
- snd_wqe_base_adr_l);
- INS_FLD(snd_wqe_base_adr_l >> shift, tmp,
- arbelprm_queue_pair_ee_context_entry_st, snd_wqe_base_adr_l);
- INS_FLD(snd_db_record_index, tmp,
- arbelprm_queue_pair_ee_context_entry_st, snd_db_record_index);
- INS_FLD(1, tmp, arbelprm_queue_pair_ee_context_entry_st, rsc);
- INS_FLD(rcv_cqn, tmp, arbelprm_queue_pair_ee_context_entry_st, cqn_rcv);
- shift =
- 32 - MT_BIT_SIZE(arbelprm_queue_pair_ee_context_entry_st,
- rcv_wqe_base_adr_l);
- INS_FLD(rcv_wqe_base_adr_l >> shift, tmp,
- arbelprm_queue_pair_ee_context_entry_st, rcv_wqe_base_adr_l);
- INS_FLD(rcv_db_record_index, tmp,
- arbelprm_queue_pair_ee_context_entry_st, rcv_db_record_index);
- INS_FLD(qkey, tmp, arbelprm_queue_pair_ee_context_entry_st, q_key);
-
- tmp =
- (__u8 *) (&prm->ctx) +
- MT_BYTE_OFFSET(arbelprm_queue_pair_ee_context_entry_st,
- primary_address_path);
- INS_FLD(dev_ib_data.port, tmp, arbelprm_address_path_st, port_number);
-
-}
-
-static void prep_init2rtr_qpee_buf(void *buf)
-{
- struct qp_ee_state_tarnisition_st *prm;
-
- prm = (struct qp_ee_state_tarnisition_st *)buf;
-
- memset(prm, 0, sizeof *prm);
-
- INS_FLD(MTU_2048, &prm->ctx, arbelprm_queue_pair_ee_context_entry_st,
- mtu);
- INS_FLD(11, &prm->ctx, arbelprm_queue_pair_ee_context_entry_st,
- msg_max);
-}
-
-static void init_av_array(void)
-{
-}
-
-/*
- * my_log2()
- */
-static int my_log2(unsigned long arg)
-{
- int i;
- __u32 tmp;
-
- if (arg == 0) {
- return INT_MIN; /* log2(0) = -infinity */
- }
-
- tmp = 1;
- i = 0;
- while (tmp < arg) {
- tmp = tmp << 1;
- ++i;
- }
-
- return i;
-}
-
-/*
- * get_req_icm_pages
- */
-static unsigned long get_req_icm_pages(unsigned long log2_reserved,
- unsigned long app_rsrc,
- unsigned long entry_size,
- unsigned long *log2_entries_p)
-{
- unsigned long size;
- unsigned long log2_entries;
-
- log2_entries = my_log2((1 << log2_reserved) + app_rsrc);
- *log2_entries_p = log2_entries;
- size = (1 << log2_entries) * entry_size;
-
- return (size + 4095) >> 12;
-}
-
-static void init_uar_context(void *uar_context_va)
-{
- void *ptr;
- /* clear all uar context */
- memset(uar_context_va, 0, 4096);
-
- ptr = uar_context_va + MADS_RCV_CQ_ARM_DB_IDX * 8;
- INS_FLD_TO_BE(UAR_RES_CQ_ARM, ptr, arbelprm_cq_arm_db_record_st, res);
- INS_FLD_TO_BE(dev_ib_data.mads_qp.rcv_cq.cqn, ptr,
- arbelprm_cq_arm_db_record_st, cq_number);
-
- ptr = uar_context_va + MADS_SND_CQ_ARM_DB_IDX * 8;
- INS_FLD_TO_BE(UAR_RES_CQ_ARM, ptr, arbelprm_cq_arm_db_record_st, res);
- INS_FLD_TO_BE(dev_ib_data.mads_qp.snd_cq.cqn, ptr,
- arbelprm_cq_arm_db_record_st, cq_number);
-
- ptr = uar_context_va + IPOIB_RCV_CQ_ARM_DB_IDX * 8;
- INS_FLD_TO_BE(UAR_RES_CQ_ARM, ptr, arbelprm_cq_arm_db_record_st, res);
- INS_FLD_TO_BE(dev_ib_data.ipoib_qp.rcv_cq.cqn, ptr,
- arbelprm_cq_arm_db_record_st, cq_number);
-
- ptr = uar_context_va + IPOIB_SND_CQ_ARM_DB_IDX * 8;
- INS_FLD_TO_BE(UAR_RES_CQ_ARM, ptr, arbelprm_cq_arm_db_record_st, res);
- INS_FLD_TO_BE(dev_ib_data.ipoib_qp.snd_cq.cqn, ptr,
- arbelprm_cq_arm_db_record_st, cq_number);
-
- ptr = uar_context_va + MADS_SND_QP_DB_IDX * 8;
- INS_FLD_TO_BE(UAR_RES_SQ_DBELL, ptr, arbelprm_qp_db_record_st, res);
- INS_FLD_TO_BE(dev_ib_data.mads_qp.qpn, ptr, arbelprm_qp_db_record_st,
- qp_number);
-
- ptr = uar_context_va + IPOIB_SND_QP_DB_IDX * 8;
- INS_FLD_TO_BE(UAR_RES_SQ_DBELL, ptr, arbelprm_qp_db_record_st, res);
- INS_FLD_TO_BE(dev_ib_data.ipoib_qp.qpn, ptr, arbelprm_qp_db_record_st,
- qp_number);
-
- ptr = uar_context_va + GROUP_SEP_IDX * 8;
- INS_FLD_TO_BE(UAR_RES_GROUP_SEP, ptr, arbelprm_cq_arm_db_record_st,
- res);
-
- ptr = uar_context_va + MADS_RCV_QP_DB_IDX * 8;
- INS_FLD_TO_BE(UAR_RES_RQ_DBELL, ptr, arbelprm_qp_db_record_st, res);
- INS_FLD_TO_BE(dev_ib_data.mads_qp.qpn, ptr, arbelprm_qp_db_record_st,
- qp_number);
-
- ptr = uar_context_va + IPOIB_RCV_QP_DB_IDX * 8;
- INS_FLD_TO_BE(UAR_RES_RQ_DBELL, ptr, arbelprm_qp_db_record_st, res);
- INS_FLD_TO_BE(dev_ib_data.ipoib_qp.qpn, ptr, arbelprm_qp_db_record_st,
- qp_number);
-
- ptr = uar_context_va + MADS_RCV_CQ_CI_DB_IDX * 8;
- INS_FLD_TO_BE(UAR_RES_CQ_SET_CI, ptr, arbelprm_cq_ci_db_record_st, res);
- INS_FLD_TO_BE(dev_ib_data.mads_qp.rcv_cq.cqn, ptr,
- arbelprm_cq_ci_db_record_st, cq_number);
-
- ptr = uar_context_va + MADS_SND_CQ_CI_DB_IDX * 8;
- INS_FLD_TO_BE(UAR_RES_CQ_SET_CI, ptr, arbelprm_cq_ci_db_record_st, res);
- INS_FLD_TO_BE(dev_ib_data.mads_qp.snd_cq.cqn, ptr,
- arbelprm_cq_ci_db_record_st, cq_number);
-
- ptr = uar_context_va + IPOIB_RCV_CQ_CI_DB_IDX * 8;
- INS_FLD_TO_BE(UAR_RES_CQ_SET_CI, ptr, arbelprm_cq_ci_db_record_st, res);
- INS_FLD_TO_BE(dev_ib_data.ipoib_qp.rcv_cq.cqn, ptr,
- arbelprm_cq_ci_db_record_st, cq_number);
-
- ptr = uar_context_va + IPOIB_SND_CQ_CI_DB_IDX * 8;
- INS_FLD_TO_BE(UAR_RES_CQ_SET_CI, ptr, arbelprm_cq_ci_db_record_st, res);
- INS_FLD_TO_BE(dev_ib_data.ipoib_qp.snd_cq.cqn, ptr,
- arbelprm_cq_ci_db_record_st, cq_number);
-
-}
-
-static int setup_hca(__u8 port, void **eq_p)
-{
- int ret;
- int rc;
- struct query_fw_st qfw;
- struct map_icm_st map_obj;
- struct dev_lim_st dev_lim;
- struct init_hca_st init_hca;
- __u8 log2_pages;
- unsigned long icm_start, icm_size, tmp;
- unsigned long log2_entries;
- __u32 aux_pages;
- __u32 mem_key, key, tmp_key;
- __u8 eqn;
- __u32 event_mask;
- struct eqe_t *eq_buf;
- void *inprm;
- unsigned long bus_addr;
- struct query_adapter_st qa;
- __u8 log_max_uars = 1;
- void *uar_context_va;
- __u32 uar_context_pa;
-
- tprintf("called");
- init_dev_data();
- inprm = get_inprm_buf();
-
- rc = reset_hca();
- if (rc) {
- eprintf("");
- return rc;
- } else {
- tprintf("reset_hca() success");
- }
-
- mdelay(1000); /* wait for 1 sec */
-
- rc = restore_config();
- if (rc) {
- eprintf("");
- return rc;
- } else {
- tprintf("restore_config() success");
- }
-
- dev_ib_data.pd = GLOBAL_PD;
- dev_ib_data.port = port;
- dev_ib_data.qkey = GLOBAL_QKEY;
-
- rc = cmd_query_fw(&qfw);
- if (rc) {
- eprintf("");
- return rc;
- }
- else {
- tprintf("cmd_query_fw() success");
-
- if (print_info) {
- printf("FW ver = %d.%d.%d\n",
- qfw.fw_rev_major,
- qfw.fw_rev_minor,
- qfw.fw_rev_subminor);
- }
-
- tprintf("fw_rev_major=%d", qfw.fw_rev_major);
- tprintf("fw_rev_minor=%d", qfw.fw_rev_minor);
- tprintf("fw_rev_subminor=%d", qfw.fw_rev_subminor);
- tprintf("error_buf_start_h=0x%x", qfw.error_buf_start_h);
- tprintf("error_buf_start_l=0x%x", qfw.error_buf_start_l);
- tprintf("error_buf_size=%d", qfw.error_buf_size);
- }
-
-
-
- bus_addr =
- ((unsigned long)((u64) qfw.error_buf_start_h << 32) | qfw.
- error_buf_start_l);
- dev_ib_data.error_buf_addr= ioremap(bus_addr,
- qfw.error_buf_size*4);
- dev_ib_data.error_buf_size= qfw.error_buf_size;
- if (!dev_ib_data.error_buf_addr) {
- eprintf("");
- return -1;
- }
-
-
- bus_addr =
- ((unsigned long)((u64) qfw.clear_int_addr.addr_h << 32) | qfw.
- clear_int_addr.addr_l);
- dev_ib_data.clr_int_addr = bus_to_virt(bus_addr);
-
- rc = cmd_enable_lam();
- if (rc == 0x22 /* LAM_NOT_PRE -- need to put a name here */ ) {
- // ??????
- } else if (rc == 0) {
- // ??????
- } else {
- eprintf("");
- return rc;
- }
-
- log2_pages = my_log2(qfw.fw_pages);
-
- memset(&map_obj, 0, sizeof map_obj);
- map_obj.num_vpm = 1;
- map_obj.vpm_arr[0].log2_size = log2_pages;
- map_obj.vpm_arr[0].pa_l = phys_mem.base + phys_mem.offset;
- rc = cmd_map_fa(&map_obj);
- if (rc) {
- eprintf("");
- return rc;
- }
- phys_mem.offset += 1 << (log2_pages + 12);
-
- rc = cmd_run_fw();
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_map_fa;
- }
-
- rc = cmd_mod_stat_cfg();
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_map_fa;
- }
-
- rc = cmd_query_dev_lim(&dev_lim);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_map_fa;
- }
-
- dev_ib_data.uar_idx = dev_lim.num_rsvd_uars;
-
- tprintf("max_icm_size_h=0x%lx", dev_lim.max_icm_size_h);
- tprintf("max_icm_size_l=0x%lx", dev_lim.max_icm_size_l);
-
- memset(&init_hca, 0, sizeof init_hca);
- icm_start = 0;
- icm_size = 0;
-
- icm_start += ((dev_lim.num_rsvd_uars + 1) << 12);
- icm_size += ((dev_lim.num_rsvd_uars + 1) << 12);
-
- tmp = get_req_icm_pages(dev_lim.log2_rsvd_qps,
- MAX_APP_QPS,
- dev_lim.qpc_entry_sz, &log2_entries);
- init_hca.qpc_base_addr_l = icm_start;
- init_hca.log_num_of_qp = log2_entries;
- icm_start += (tmp << 12);
- icm_size += (tmp << 12);
-
- init_hca.eqpc_base_addr_l = icm_start;
- icm_start += (tmp << 12);
- icm_size += (tmp << 12);
-
- tmp = get_req_icm_pages(dev_lim.log2_rsvd_srqs,
- 0, dev_lim.srq_entry_sz, &log2_entries);
- init_hca.srqc_base_addr_l = icm_start;
- init_hca.log_num_of_srq = log2_entries;
- icm_start += (tmp << 12);
- icm_size += (tmp << 12);
-
- tmp = get_req_icm_pages(dev_lim.log2_rsvd_ees,
- 0, dev_lim.eec_entry_sz, &log2_entries);
- init_hca.eec_base_addr_l = icm_start;
- init_hca.log_num_of_ee = log2_entries;
- icm_start += (tmp << 12);
- icm_size += (tmp << 12);
-
- init_hca.eeec_base_addr_l = icm_start;
- icm_start += (tmp << 12);
- icm_size += (tmp << 12);
-
- tmp = get_req_icm_pages(dev_lim.log2_rsvd_cqs,
- MAX_APP_CQS,
- dev_lim.cqc_entry_sz, &log2_entries);
- init_hca.cqc_base_addr_l = icm_start;
- init_hca.log_num_of_cq = log2_entries;
- icm_start += (tmp << 12);
- icm_size += (tmp << 12);
-
- tmp = get_req_icm_pages(dev_lim.log2_rsvd_mtts,
- 0, dev_lim.mtt_entry_sz, &log2_entries);
- init_hca.mtt_base_addr_l = icm_start;
- icm_start += (tmp << 12);
- icm_size += (tmp << 12);
-
- tmp = get_req_icm_pages(dev_lim.log2_rsvd_mrws,
- 1, dev_lim.mpt_entry_sz, &log2_entries);
- init_hca.mpt_base_addr_l = icm_start;
- init_hca.log_mpt_sz = log2_entries;
- icm_start += (tmp << 12);
- icm_size += (tmp << 12);
-
- tmp = get_req_icm_pages(dev_lim.log2_rsvd_rdbs, 1, 32, /* size of rdb entry */
- &log2_entries);
- init_hca.rdb_base_addr_l = icm_start;
- icm_start += (tmp << 12);
- icm_size += (tmp << 12);
-
- init_hca.eqc_base_addr_l = icm_start;
- init_hca.log_num_of_eq = LOG2_EQS;
- tmp = dev_lim.eqc_entry_sz * (1 << LOG2_EQS);
- icm_start += tmp;
- icm_size += tmp;
-
- init_hca.mc_base_addr_l = icm_start;
- init_hca.log_mc_table_entry_sz =
- my_log2(MT_STRUCT_SIZE(arbelprm_mgm_entry_st));
- init_hca.mc_table_hash_sz = 8;
- init_hca.log_mc_table_sz = 3;
- icm_size +=
- (MT_STRUCT_SIZE(arbelprm_mgm_entry_st) * init_hca.mc_table_hash_sz);
- icm_start +=
- (MT_STRUCT_SIZE(arbelprm_mgm_entry_st) * init_hca.mc_table_hash_sz);
-
- rc = cmd_set_icm_size(icm_size, &aux_pages);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_map_fa;
- }
-
- memset(&map_obj, 0, sizeof map_obj);
- map_obj.num_vpm = 1;
- map_obj.vpm_arr[0].pa_l = phys_mem.base + phys_mem.offset;
- map_obj.vpm_arr[0].log2_size = my_log2(aux_pages);
- rc = cmd_map_icm_aux(&map_obj);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_map_fa;
- }
- phys_mem.offset += (1 << (map_obj.vpm_arr[0].log2_size + 12));
-
- uar_context_pa = phys_mem.base + phys_mem.offset +
- dev_ib_data.uar_idx * 4096;
- uar_context_va = phys_to_virt(uar_context_pa);
- tprintf("uar_context: va=0x%lx, pa=0x%lx", uar_context_va,
- uar_context_pa);
- dev_ib_data.uar_context_base = uar_context_va;
-
- memset(&map_obj, 0, sizeof map_obj);
- map_obj.num_vpm = 1;
- map_obj.vpm_arr[0].pa_l = phys_mem.base + phys_mem.offset;
- map_obj.vpm_arr[0].log2_size = my_log2((icm_size + 4095) >> 12);
- rc = cmd_map_icm(&map_obj);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_map_fa;
- }
- phys_mem.offset += (1 << (map_obj.vpm_arr[0].log2_size + 12));
-
- init_hca.log_max_uars = log_max_uars;
- tprintf("inprm: va=0x%lx, pa=0x%lx", inprm, virt_to_bus(inprm));
- prep_init_hca_buf(&init_hca, inprm);
- rc = cmd_init_hca(inprm, MT_STRUCT_SIZE(arbelprm_init_hca_st));
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_map_fa;
- }
-
- rc = cmd_query_adapter(&qa);
- if (rc) {
- eprintf("");
- return rc;
- }
- dev_ib_data.clr_int_data = 1 << qa.intapin;
-
- tmp_key = 1 << dev_lim.log2_rsvd_mrws | MKEY_PREFIX;
- mem_key = 1 << (dev_lim.log2_rsvd_mrws + 8) | (MKEY_PREFIX >> 24);
- prep_sw2hw_mpt_buf(inprm, tmp_key);
- rc = cmd_sw2hw_mpt(&key, 1 << dev_lim.log2_rsvd_mrws, inprm,
- SW2HW_MPT_IBUF_SZ);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_map_fa;
- } else {
- tprintf("cmd_sw2hw_mpt() success, key=0x%lx", mem_key);
- }
- dev_ib_data.mkey = mem_key;
-
- eqn = EQN;
- /* allocate a single EQ which will receive
- all the events */
- eq_buf = dev_buffers_p->eq_buf;
- init_eq_buf(eq_buf); /* put in HW ownership */
- prep_sw2hw_eq_buf(inprm, eq_buf);
- rc = cmd_sw2hw_eq(SW2HW_EQ_IBUF_SZ);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_sw2hw_mpt;
- } else
- tprintf("cmd_sw2hw_eq() success");
-
- event_mask = (1 << XDEV_EV_TYPE_CQ_COMP) |
- (1 << XDEV_EV_TYPE_CQ_ERR) |
- (1 << XDEV_EV_TYPE_LOCAL_WQ_CATAS_ERR) |
- (1 << XDEV_EV_TYPE_PORT_ERR) |
- (1 << XDEV_EV_TYPE_LOCAL_WQ_INVALID_REQ_ERR) |
- (1 << XDEV_EV_TYPE_LOCAL_WQ_ACCESS_VIOL_ERR) |
- (1 << TAVOR_IF_EV_TYPE_OVERRUN);
- rc = cmd_map_eq(eqn, event_mask, 1);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_sw2hw_eq;
- } else
- tprintf("cmd_map_eq() success");
-
- dev_ib_data.eq.eqn = eqn;
- dev_ib_data.eq.eq_buf = eq_buf;
- dev_ib_data.eq.cons_counter = 0;
- dev_ib_data.eq.eq_size = 1 << LOG2_EQ_SZ;
- bus_addr =
- ((unsigned long)((u64) qfw.eq_ci_table.addr_h << 32) | qfw.
- eq_ci_table.addr_l)
- + eqn * 8;
- dev_ib_data.eq.ci_base_base_addr = bus_to_virt(bus_addr);
- *eq_p = &dev_ib_data.eq;
-
- prep_init_ib_buf(inprm);
- rc = cmd_init_ib(port, inprm, INIT_IB_IBUF_SZ);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_sw2hw_eq;
- } else
- tprintf("cmd_init_ib() success");
-
- init_av_array();
- tprintf("init_av_array() done");
-
- /* set the qp and cq numbers according
- to the results of query_dev_lim */
- dev_ib_data.mads_qp.qpn = (1 << dev_lim.log2_rsvd_qps) +
- +QPN_BASE + MADS_QPN_SN;
- dev_ib_data.ipoib_qp.qpn = (1 << dev_lim.log2_rsvd_qps) +
- +QPN_BASE + IPOIB_QPN_SN;
-
- dev_ib_data.mads_qp.snd_cq.cqn = (1 << dev_lim.log2_rsvd_cqs) +
- MADS_SND_CQN_SN;
- dev_ib_data.mads_qp.rcv_cq.cqn = (1 << dev_lim.log2_rsvd_cqs) +
- MADS_RCV_CQN_SN;
-
- dev_ib_data.ipoib_qp.snd_cq.cqn = (1 << dev_lim.log2_rsvd_cqs) +
- IPOIB_SND_CQN_SN;
- dev_ib_data.ipoib_qp.rcv_cq.cqn = (1 << dev_lim.log2_rsvd_cqs) +
- IPOIB_RCV_CQN_SN;
-
- init_uar_context(uar_context_va);
-
- ret = 0;
- goto exit;
-
- undo_sw2hw_eq:
- rc = cmd_hw2sw_eq(eqn);
- if (rc)
- eprintf("");
- else
- tprintf("cmd_hw2sw_eq() success");
-
- undo_sw2hw_mpt:
- rc = cmd_hw2sw_mpt(tmp_key);
- if (rc)
- eprintf("");
-
- undo_map_fa:
- rc = cmd_unmap_fa();
- if (rc)
- eprintf("");
-
- exit:
- return ret;
-}
-
-static void *get_inprm_buf(void)
-{
- return dev_buffers_p->inprm_buf;
-}
-
-static void *get_outprm_buf(void)
-{
- return dev_buffers_p->outprm_buf;
-}
-
-static void *get_send_wqe_buf(void *wqe, __u8 index)
-{
- struct ud_send_wqe_st *snd_wqe = wqe;
-
- return bus_to_virt(be32_to_cpu(snd_wqe->mpointer[index].local_addr_l));
-}
-
-static void *get_rcv_wqe_buf(void *wqe, __u8 index)
-{
- struct recv_wqe_st *rcv_wqe = wqe;
-
- return bus_to_virt(be32_to_cpu(rcv_wqe->mpointer[index].local_addr_l));
-}
-
-static void modify_av_params(struct ud_av_st *av,
- __u16 dlid,
- __u8 g,
- __u8 sl, __u8 rate, union ib_gid_u *gid, __u32 qpn)
-{
- memset(&av->av, 0, sizeof av->av);
-
- INS_FLD_TO_BE(dev_ib_data.port, &av->av, arbelprm_ud_address_vector_st,
- port_number);
- INS_FLD_TO_BE(dev_ib_data.pd, &av->av, arbelprm_ud_address_vector_st,
- pd);
- INS_FLD_TO_BE(dlid, &av->av, arbelprm_ud_address_vector_st, rlid);
- INS_FLD_TO_BE(g, &av->av, arbelprm_ud_address_vector_st, g);
- INS_FLD_TO_BE(sl, &av->av, arbelprm_ud_address_vector_st, sl);
- INS_FLD_TO_BE(3, &av->av, arbelprm_ud_address_vector_st, msg);
-
- if (rate >= 3)
- INS_FLD_TO_BE(0, &av->av, arbelprm_ud_address_vector_st, max_stat_rate); /* 4x */
- else
- INS_FLD_TO_BE(1, &av->av, arbelprm_ud_address_vector_st, max_stat_rate); /* 1x */
-
- if (g) {
- if (gid) {
- INS_FLD(*((__u32 *) (&gid->raw[0])), &av->av,
- arbelprm_ud_address_vector_st, rgid_127_96);
- INS_FLD(*((__u32 *) (&gid->raw[4])), &av->av,
- arbelprm_ud_address_vector_st, rgid_95_64);
- INS_FLD(*((__u32 *) (&gid->raw[8])), &av->av,
- arbelprm_ud_address_vector_st, rgid_63_32);
- INS_FLD(*((__u32 *) (&gid->raw[12])), &av->av,
- arbelprm_ud_address_vector_st, rgid_31_0);
- } else {
- INS_FLD(0, &av->av, arbelprm_ud_address_vector_st,
- rgid_127_96);
- INS_FLD(0, &av->av, arbelprm_ud_address_vector_st,
- rgid_95_64);
- INS_FLD(0, &av->av, arbelprm_ud_address_vector_st,
- rgid_63_32);
- INS_FLD(0, &av->av, arbelprm_ud_address_vector_st,
- rgid_31_0);
- }
- } else {
- INS_FLD(0, &av->av, arbelprm_ud_address_vector_st, rgid_127_96);
- INS_FLD(0, &av->av, arbelprm_ud_address_vector_st, rgid_95_64);
- INS_FLD(0, &av->av, arbelprm_ud_address_vector_st, rgid_63_32);
- INS_FLD(2, &av->av, arbelprm_ud_address_vector_st, rgid_31_0);
- }
- av->dest_qp = qpn;
- av->qkey = dev_ib_data.qkey;
-}
-
-static void init_cq_buf(union cqe_st *cq_buf, __u8 num_cqes)
-{
- int i;
-
- memset(cq_buf, 0, sizeof(union cqe_st) * num_cqes);
- for (i = 0; i < num_cqes; ++i) {
- WRITE_BYTE_VOL(&cq_buf[i], CQE_OWNER_OFFSET, CQE_OWNER_VAL_HW);
- }
-}
-
-static int post_rcv_buf(struct udqp_st *qp, struct recv_wqe_st *rcv_wqe)
-{
- int i;
-
- /* put a valid lkey */
- for (i = 0; i < MAX_SCATTER; ++i) {
- rcv_wqe->mpointer[i].lkey = cpu_to_be32(dev_ib_data.mkey);
- }
-
- qp->post_rcv_counter++;
- WRITE_WORD_VOL(qp->rcv_uar_context, 2, htons(qp->post_rcv_counter));
-
- return 0;
-}
-
-static int post_send_req(void *qph, void *wqeh, __u8 num_gather)
-{
- int rc;
- struct udqp_st *qp = qph;
- struct ud_send_wqe_st *snd_wqe = wqeh;
- struct send_doorbell_st dbell;
- __u32 nds;
-
- qp->post_send_counter++;
-
- WRITE_WORD_VOL(qp->send_uar_context, 2, htons(qp->post_send_counter));
-
- memset(&dbell, 0, sizeof dbell);
- INS_FLD(XDEV_NOPCODE_SEND, &dbell, arbelprm_send_doorbell_st, nopcode);
- INS_FLD(1, &dbell, arbelprm_send_doorbell_st, f);
- INS_FLD(qp->post_send_counter - 1, &dbell, arbelprm_send_doorbell_st,
- wqe_counter);
- INS_FLD(1, &dbell, arbelprm_send_doorbell_st, wqe_cnt);
- nds = (sizeof(snd_wqe->next) +
- sizeof(snd_wqe->udseg) +
- sizeof(snd_wqe->mpointer[0]) * num_gather) >> 4;
- INS_FLD(nds, &dbell, arbelprm_send_doorbell_st, nds);
- INS_FLD(qp->qpn, &dbell, arbelprm_send_doorbell_st, qpn);
-
- if (qp->last_posted_snd_wqe) {
- INS_FLD_TO_BE(nds,
- &qp->last_posted_snd_wqe->next.next,
- arbelprm_wqe_segment_next_st, nds);
- INS_FLD_TO_BE(1,
- &qp->last_posted_snd_wqe->next.next,
- arbelprm_wqe_segment_next_st, f);
- INS_FLD_TO_BE(XDEV_NOPCODE_SEND,
- &qp->last_posted_snd_wqe->next.next,
- arbelprm_wqe_segment_next_st, nopcode);
- }
-
- rc = cmd_post_doorbell(&dbell, POST_SND_OFFSET);
- if (!rc) {
- qp->last_posted_snd_wqe = snd_wqe;
- }
-
- return rc;
-
-}
-
-static int create_mads_qp(void **qp_pp, void **snd_cq_pp, void **rcv_cq_pp)
-{
- __u8 i, next_i, j, k;
- int rc;
- struct udqp_st *qp;
- __u32 bus_addr;
- __u8 nds;
- void *ptr;
-
- qp = &dev_ib_data.mads_qp;
-
- /* set the pointer to the receive WQEs buffer */
- qp->rcv_wq = dev_buffers_p->mads_qp_rcv_queue;
-
- qp->send_buf_sz = MAD_BUF_SZ;
- qp->rcv_buf_sz = MAD_BUF_SZ;
-
- qp->max_recv_wqes = NUM_MADS_RCV_WQES; /* max wqes in this work queue */
- qp->recv_wqe_cur_free = NUM_MADS_RCV_WQES; /* current free wqes */
- qp->recv_wqe_alloc_idx = 0; /* index from wqes can be allocated if there are free wqes */
-
- qp->rcv_uar_context =
- dev_ib_data.uar_context_base + 8 * MADS_RCV_QP_DB_IDX;
- qp->send_uar_context =
- dev_ib_data.uar_context_base + 8 * MADS_SND_QP_DB_IDX;
-
- memset(&qp->rcv_wq[0], 0, NUM_MADS_RCV_WQES * sizeof(qp->rcv_wq[0]));
- nds = sizeof(qp->rcv_wq[0].wqe) >> 4;
- /* iterrate through the list */
- for (j = 0, i = 0, next_i = 1;
- j < NUM_MADS_RCV_WQES;
- MOD_INC(i, NUM_MADS_RCV_WQES), MOD_INC(next_i, NUM_MADS_RCV_WQES),
- ++j) {
-
- qp->rcv_bufs[i] = ib_buffers.rcv_mad_buf[i];
- /* link the WQE to the next one */
- bus_addr = virt_to_bus(&qp->rcv_wq[next_i].wqe);
- ptr = qp->rcv_wq[i].wqe.control +
- MT_BYTE_OFFSET(arbelprm_wqe_segment_ctrl_recv_st,
- wqe_segment_next);
- INS_FLD(bus_addr >> 6, ptr, arbelprm_recv_wqe_segment_next_st,
- nda_31_6);
- INS_FLD(nds, ptr, arbelprm_recv_wqe_segment_next_st, nds);
-
- /* set the allocated buffers */
- qp->rcv_bufs[i] = ib_buffers.rcv_mad_buf[i];
- bus_addr = virt_to_bus(qp->rcv_bufs[i]);
- qp->rcv_wq[i].wqe.mpointer[0].local_addr_l = bus_addr;
- qp->rcv_wq[i].wqe.mpointer[0].byte_count = GRH_SIZE;
- bus_addr = virt_to_bus(qp->rcv_bufs[i] + GRH_SIZE);
- qp->rcv_wq[i].wqe.mpointer[1].local_addr_l = bus_addr;
- qp->rcv_wq[i].wqe.mpointer[1].byte_count = MAD_BUF_SZ;
-
- for (k = 0; k < (((sizeof(qp->rcv_wq[i])) >> 4) - 1); ++k) {
- qp->rcv_wq[i].wqe.mpointer[k].lkey = INVALID_WQE_LKEY;
- }
- }
- cpu_to_be_buf(&qp->rcv_wq[0],
- NUM_MADS_RCV_WQES * sizeof(qp->rcv_wq[0]));
-
- for (i = 0; i < qp->max_recv_wqes; ++i) {
- qp->rcv_wq[i].wqe_cont.qp = qp;
- }
-
- /* set the pointer to the send WQEs buffer */
- qp->snd_wq = dev_buffers_p->mads_qp_snd_queue;
-
- qp->snd_wqe_alloc_idx = 0;
- qp->max_snd_wqes = NUM_MADS_SND_WQES;
- qp->snd_wqe_cur_free = NUM_MADS_SND_WQES;
-
- memset(&qp->snd_wq[0], 0, NUM_MADS_SND_WQES * sizeof(qp->snd_wq[i]));
- /* iterrate through the list */
- for (j = 0, i = 0, next_i = 1;
- j < NUM_MADS_RCV_WQES;
- MOD_INC(i, NUM_MADS_SND_WQES), MOD_INC(next_i, NUM_MADS_SND_WQES),
- ++j) {
-
- /* link the WQE to the next one */
- bus_addr = virt_to_bus(&qp->snd_wq[next_i].wqe_cont.wqe);
- INS_FLD(bus_addr >> 6, &qp->snd_wq[i].wqe_cont.wqe.next.next,
- arbelprm_wqe_segment_next_st, nda_31_6);
-
- /* set the allocated buffers */
- qp->snd_bufs[i] = ib_buffers.send_mad_buf[i];
- bus_addr = virt_to_bus(qp->snd_bufs[i]);
- qp->snd_wq[i].wqe_cont.wqe.mpointer[0].local_addr_l = bus_addr;
- qp->snd_wq[i].wqe_cont.wqe.mpointer[0].lkey = dev_ib_data.mkey;
- qp->snd_wq[i].wqe_cont.wqe.mpointer[0].byte_count =
- qp->send_buf_sz;
-
- }
-
- cpu_to_be_buf(&qp->snd_wq[0],
- NUM_MADS_SND_WQES * sizeof(qp->snd_wq[i]));
-
- for (i = 0; i < qp->max_snd_wqes; ++i) {
- qp->snd_wq[i].wqe_cont.qp = qp;
- }
-
- /* qp number and cq numbers are already set up */
- qp->snd_cq.cq_buf = dev_buffers_p->mads_snd_cq_buf;
- qp->rcv_cq.cq_buf = dev_buffers_p->mads_rcv_cq_buf;
- qp->snd_cq.num_cqes = NUM_MADS_SND_CQES;
- qp->rcv_cq.num_cqes = NUM_MADS_RCV_CQES;
- qp->snd_cq.arm_db_ctx_idx = MADS_SND_CQ_ARM_DB_IDX;
- qp->snd_cq.ci_db_ctx_idx = MADS_SND_CQ_CI_DB_IDX;
- qp->rcv_cq.arm_db_ctx_idx = MADS_RCV_CQ_ARM_DB_IDX;
- qp->rcv_cq.ci_db_ctx_idx = MADS_RCV_CQ_CI_DB_IDX;
- qp->rcv_db_record_index = MADS_RCV_QP_DB_IDX;
- qp->snd_db_record_index = MADS_SND_QP_DB_IDX;
- qp->qkey = GLOBAL_QKEY;
- rc = create_udqp(qp);
- if (!rc) {
- *qp_pp = qp;
- *snd_cq_pp = &qp->snd_cq;
- *rcv_cq_pp = &qp->rcv_cq;
- }
-
- return rc;
-}
-
-static int create_ipoib_qp(void **qp_pp,
- void **snd_cq_pp, void **rcv_cq_pp, __u32 qkey)
-{
- __u8 i, next_i, j, k;
- int rc;
- struct udqp_st *qp;
- __u32 bus_addr;
- __u8 nds;
- void *ptr;
-
- qp = &dev_ib_data.ipoib_qp;
-
- /* set the pointer to the receive WQEs buffer */
- qp->rcv_wq = dev_buffers_p->ipoib_qp_rcv_queue;
-
- qp->send_buf_sz = IPOIB_SND_BUF_SZ;
- qp->rcv_buf_sz = IPOIB_RCV_BUF_SZ;
-
- qp->max_recv_wqes = NUM_IPOIB_RCV_WQES;
- qp->recv_wqe_cur_free = NUM_IPOIB_RCV_WQES;
-
- qp->rcv_uar_context =
- dev_ib_data.uar_context_base + 8 * IPOIB_RCV_QP_DB_IDX;
- qp->send_uar_context =
- dev_ib_data.uar_context_base + 8 * IPOIB_SND_QP_DB_IDX;
-
- memset(&qp->rcv_wq[0], 0, NUM_IPOIB_RCV_WQES * sizeof(qp->rcv_wq[0]));
- nds = sizeof(qp->rcv_wq[0].wqe) >> 4;
- /* iterrate through the list */
- for (j = 0, i = 0, next_i = 1;
- j < NUM_IPOIB_RCV_WQES;
- MOD_INC(i, NUM_IPOIB_RCV_WQES), MOD_INC(next_i,
- NUM_IPOIB_RCV_WQES), ++j) {
-
- /* link the WQE to the next one */
- bus_addr = virt_to_bus(&qp->rcv_wq[next_i].wqe);
- ptr = qp->rcv_wq[i].wqe.control +
- MT_BYTE_OFFSET(arbelprm_wqe_segment_ctrl_recv_st,
- wqe_segment_next);
- INS_FLD(bus_addr >> 6, ptr, arbelprm_recv_wqe_segment_next_st,
- nda_31_6);
- INS_FLD(nds, ptr, arbelprm_recv_wqe_segment_next_st, nds);
-
- /* set the allocated buffers */
- qp->rcv_bufs[i] = ib_buffers.ipoib_rcv_buf[i];
- bus_addr = virt_to_bus(qp->rcv_bufs[i]);
- qp->rcv_wq[i].wqe.mpointer[0].local_addr_l = bus_addr;
- qp->rcv_wq[i].wqe.mpointer[0].byte_count = GRH_SIZE;
- bus_addr = virt_to_bus(qp->rcv_bufs[i] + GRH_SIZE);
- qp->rcv_wq[i].wqe.mpointer[1].local_addr_l = bus_addr;
- qp->rcv_wq[i].wqe.mpointer[1].byte_count = IPOIB_RCV_BUF_SZ;
-
- for (k = 0; k < (((sizeof(qp->rcv_wq[i].wqe)) >> 4) - 1); ++k) {
- qp->rcv_wq[i].wqe.mpointer[k].lkey = INVALID_WQE_LKEY;
- }
- }
- cpu_to_be_buf(&qp->rcv_wq[0],
- NUM_IPOIB_RCV_WQES * sizeof(qp->rcv_wq[0]));
-
- for (i = 0; i < qp->max_recv_wqes; ++i) {
- qp->rcv_wq[i].wqe_cont.qp = qp;
- }
-
- /* set the pointer to the send WQEs buffer */
- qp->snd_wq = dev_buffers_p->ipoib_qp_snd_queue;
-
- qp->snd_wqe_alloc_idx = 0;
- qp->max_snd_wqes = NUM_IPOIB_SND_WQES;
- qp->snd_wqe_cur_free = NUM_IPOIB_SND_WQES;
-
- memset(&qp->snd_wq[0], 0, NUM_IPOIB_SND_WQES * sizeof(qp->snd_wq[i]));
- /* iterrate through the list */
- for (j = 0, i = 0, next_i = 1;
- j < NUM_IPOIB_RCV_WQES;
- MOD_INC(i, NUM_IPOIB_SND_WQES), MOD_INC(next_i,
- NUM_IPOIB_SND_WQES), ++j) {
-
- /* link the WQE to the next one */
- bus_addr = virt_to_bus(&qp->snd_wq[next_i].wqe_cont.wqe);
- INS_FLD(bus_addr >> 6, &qp->snd_wq[i].wqe_cont.wqe.next.next,
- arbelprm_wqe_segment_next_st, nda_31_6);
-
- /* set the allocated buffers */
- qp->snd_bufs[i] = ib_buffers.send_ipoib_buf[i];
- bus_addr = virt_to_bus(qp->snd_bufs[i]);
- qp->snd_wq[i].wqe_cont.wqe.mpointer[0].local_addr_l = bus_addr;
- qp->snd_wq[i].wqe_cont.wqe.mpointer[0].lkey = dev_ib_data.mkey;
-
- }
- cpu_to_be_buf(&qp->snd_wq[0],
- NUM_IPOIB_SND_WQES * sizeof(qp->snd_wq[i]));
-
- for (i = 0; i < qp->max_snd_wqes; ++i) {
- qp->snd_wq[i].wqe_cont.qp = qp;
- }
-
- /* qp number and cq numbers are already set up */
- qp->snd_cq.cq_buf = dev_buffers_p->ipoib_snd_cq_buf;
- qp->rcv_cq.cq_buf = dev_buffers_p->ipoib_rcv_cq_buf;
- qp->snd_cq.num_cqes = NUM_IPOIB_SND_CQES;
- qp->rcv_cq.num_cqes = NUM_IPOIB_RCV_CQES;
- qp->snd_cq.arm_db_ctx_idx = IPOIB_SND_CQ_ARM_DB_IDX;
- qp->snd_cq.ci_db_ctx_idx = IPOIB_SND_CQ_CI_DB_IDX;
- qp->rcv_cq.arm_db_ctx_idx = IPOIB_RCV_CQ_ARM_DB_IDX;
- qp->rcv_cq.ci_db_ctx_idx = IPOIB_RCV_CQ_CI_DB_IDX;
- qp->rcv_db_record_index = IPOIB_RCV_QP_DB_IDX;
- qp->snd_db_record_index = IPOIB_SND_QP_DB_IDX;
- qp->qkey = qkey;
- rc = create_udqp(qp);
- if (!rc) {
- *qp_pp = qp;
- *snd_cq_pp = &qp->snd_cq;
- *rcv_cq_pp = &qp->rcv_cq;
- }
-
- return rc;
-}
-
-static int create_udqp(struct udqp_st *qp)
-{
- int rc, ret = 0;
- void *inprm;
- struct recv_wqe_st *rcv_wqe;
-
- inprm = dev_buffers_p->inprm_buf;
-
- qp->rcv_cq.arm_db_ctx_pointer =
- dev_ib_data.uar_context_base + 8 * qp->rcv_cq.arm_db_ctx_idx;
- qp->rcv_cq.ci_db_ctx_pointer =
- dev_ib_data.uar_context_base + 8 * qp->rcv_cq.ci_db_ctx_idx;
- qp->snd_cq.arm_db_ctx_pointer =
- dev_ib_data.uar_context_base + 8 * qp->snd_cq.arm_db_ctx_idx;
- qp->snd_cq.ci_db_ctx_pointer =
- dev_ib_data.uar_context_base + 8 * qp->snd_cq.ci_db_ctx_idx;
-
- /* create send CQ */
- init_cq_buf(qp->snd_cq.cq_buf, qp->snd_cq.num_cqes);
- qp->snd_cq.cons_counter = 0;
- prep_sw2hw_cq_buf(inprm,
- dev_ib_data.eq.eqn,
- qp->snd_cq.cqn,
- qp->snd_cq.cq_buf,
- qp->snd_cq.ci_db_ctx_idx, qp->snd_cq.arm_db_ctx_idx);
-
- rc = cmd_sw2hw_cq(qp->snd_cq.cqn, inprm, SW2HW_CQ_IBUF_SZ);
- if (rc) {
- ret = -1;
- eprintf("");
- goto exit;
- }
-
- /* create receive CQ */
- init_cq_buf(qp->rcv_cq.cq_buf, qp->rcv_cq.num_cqes);
- qp->rcv_cq.cons_counter = 0;
- memset(inprm, 0, SW2HW_CQ_IBUF_SZ);
- prep_sw2hw_cq_buf(inprm,
- dev_ib_data.eq.eqn,
- qp->rcv_cq.cqn,
- qp->rcv_cq.cq_buf,
- qp->rcv_cq.ci_db_ctx_idx, qp->rcv_cq.arm_db_ctx_idx);
-
- rc = cmd_sw2hw_cq(qp->rcv_cq.cqn, inprm, SW2HW_CQ_IBUF_SZ);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_snd_cq;
- }
-
- prep_rst2init_qpee_buf(inprm,
- qp->snd_cq.cqn,
- qp->rcv_cq.cqn,
- qp->qkey,
- my_log2(qp->max_recv_wqes),
- my_log2(sizeof(qp->rcv_wq[0])) - 4,
- my_log2(qp->max_snd_wqes),
- my_log2(sizeof(qp->snd_wq[0])) - 4,
- virt_to_bus(qp->snd_wq),
- qp->snd_db_record_index,
- virt_to_bus(qp->rcv_wq),
- qp->rcv_db_record_index);
-
- rc = cmd_rst2init_qpee(qp->qpn, inprm, QPCTX_IBUF_SZ);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_rcv_cq;
- }
-
- qp->last_posted_rcv_wqe = NULL;
- qp->last_posted_snd_wqe = NULL;
-
- /* post all the buffers to the receive queue */
- while (1) {
- /* allocate wqe */
- rcv_wqe = alloc_rcv_wqe(qp);
- if (!rcv_wqe)
- break;
-
- /* post the buffer */
- rc = post_rcv_buf(qp, rcv_wqe);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_rcv_cq;
- }
- }
-
- prep_init2rtr_qpee_buf(inprm);
- rc = cmd_init2rtr_qpee(qp->qpn, inprm, QPCTX_IBUF_SZ);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_rcv_cq;
- }
-
- memset(inprm, 0, QPCTX_IBUF_SZ);
- rc = cmd_rtr2rts_qpee(qp->qpn, inprm, QPCTX_IBUF_SZ);
- if (rc) {
- ret = -1;
- eprintf("");
- goto undo_rcv_cq;
- }
-
- goto exit;
-
- undo_rcv_cq:
- rc = cmd_hw2sw_cq(qp->rcv_cq.cqn);
- if (rc)
- eprintf("");
-
- undo_snd_cq:
- rc = cmd_hw2sw_cq(qp->snd_cq.cqn);
- if (rc)
- eprintf("");
-
- exit:
- return ret;
-}
-
-static int destroy_udqp(struct udqp_st *qp)
-{
- int rc;
-
- rc = cmd_2err_qpee(qp->qpn);
- if (rc) {
- eprintf("");
- return rc;
- }
- tprintf("cmd_2err_qpee(0x%lx) success", qp->qpn);
-
- rc = cmd_2rst_qpee(qp->qpn);
- if (rc) {
- eprintf("");
- return rc;
- }
- tprintf("cmd_2rst_qpee(0x%lx) success", qp->qpn);
-
- rc = cmd_hw2sw_cq(qp->rcv_cq.cqn);
- if (rc) {
- eprintf("");
- return rc;
- }
- tprintf("cmd_hw2sw_cq(0x%lx) success", qp->snd_cq.cqn);
-
- rc = cmd_hw2sw_cq(qp->snd_cq.cqn);
- if (rc) {
- eprintf("");
- return rc;
- }
- tprintf("cmd_hw2sw_cq(0x%lx) success", qp->rcv_cq.cqn);
-
- return rc;
-}
-
-static void prep_send_wqe_buf(void *qph,
- void *avh,
- void *wqeh,
- const void *buf,
- unsigned int offset, __u16 len, __u8 e)
-{
- struct ud_send_wqe_st *snd_wqe = wqeh;
- struct ud_av_st *av = avh;
-
- if (qph) {
- }
- /* suppress warnings */
- INS_FLD_TO_BE(e, &snd_wqe->next.control,
- arbelprm_wqe_segment_ctrl_send_st, e);
- INS_FLD_TO_BE(1, &snd_wqe->next.control,
- arbelprm_wqe_segment_ctrl_send_st, always1);
- INS_FLD_TO_BE(1, &snd_wqe->next.next, arbelprm_wqe_segment_next_st,
- always1);
- memcpy(&snd_wqe->udseg, &av->av, sizeof av->av);
- INS_FLD_TO_BE(av->dest_qp, snd_wqe->udseg.av,
- arbelprm_wqe_segment_ud_st, destination_qp);
- INS_FLD_TO_BE(av->qkey, snd_wqe->udseg.av, arbelprm_wqe_segment_ud_st,
- q_key);
-
- if (buf) {
- memcpy(bus_to_virt
- (be32_to_cpu(snd_wqe->mpointer[0].local_addr_l)) +
- offset, buf, len);
- len += offset;
- }
- snd_wqe->mpointer[0].byte_count = cpu_to_be32(len);
-}
-
-static void *alloc_ud_av(void)
-{
- u8 next_free;
-
- if (dev_ib_data.udav.udav_next_free == FL_EOL) {
- return NULL;
- }
-
- next_free = dev_ib_data.udav.udav_next_free;
- dev_ib_data.udav.udav_next_free =
- dev_buffers_p->av_array[next_free].ud_av.next_free;
- tprintf("allocated udav %d", next_free);
- return &dev_buffers_p->av_array[next_free].ud_av;
-}
-
-static void free_ud_av(void *avh)
-{
- union ud_av_u *avu;
- __u8 idx, old_idx;
- struct ud_av_st *av = avh;
-
- avu = (union ud_av_u *)av;
-
- idx = avu - dev_buffers_p->av_array;
- tprintf("freeing udav idx=%d", idx);
- old_idx = dev_ib_data.udav.udav_next_free;
- dev_ib_data.udav.udav_next_free = idx;
- avu->ud_av.next_free = old_idx;
-}
-
-static int update_cq_cons_idx(struct cq_st *cq)
-{
- /* write doorbell record */
- WRITE_DWORD_VOL(cq->ci_db_ctx_pointer, 0, htonl(cq->cons_counter));
-
- /*
- INS_FLD_TO_BE(cq->cons_counter,
- cq->ci_db_ctx_pointer,
- arbelprm_cq_arm_db_record_st,
- counter);
-
- INS_FLD_TO_BE(cq->cqn,
- cq->ci_db_ctx_pointer,
- arbelprm_cq_arm_db_record_st,
- cq_number);
-
- INS_FLD_TO_BE(1,
- cq->ci_db_ctx_pointer,
- arbelprm_cq_arm_db_record_st,
- res); */
-
- return 0;
-}
-
-static int poll_cq(void *cqh, union cqe_st *cqe_p, u8 * num_cqes)
-{
- union cqe_st cqe;
- int rc;
- u32 *ptr;
- struct cq_st *cq = cqh;
- __u32 cons_idx = cq->cons_counter & (cq->num_cqes - 1);
-
- ptr = (u32 *) (&(cq->cq_buf[cons_idx]));
- barrier();
- if ((ptr[7] & 0x80000000) == 0) {
- cqe = cq->cq_buf[cons_idx];
- be_to_cpu_buf(&cqe, sizeof(cqe));
- *cqe_p = cqe;
- ptr[7] = 0x80000000;
- barrier();
- cq->cons_counter++;
- rc = update_cq_cons_idx(cq);
- if (rc) {
- return rc;
- }
- *num_cqes = 1;
- } else
- *num_cqes = 0;
-
- return 0;
-}
-
-static void dev2ib_cqe(struct ib_cqe_st *ib_cqe_p, union cqe_st *cqe_p)
-{
- __u8 opcode;
- __u32 wqe_addr_ba;
-
- opcode =
- EX_FLD(cqe_p->good_cqe, arbelprm_completion_queue_entry_st, opcode);
- if (opcode >= CQE_ERROR_OPCODE)
- ib_cqe_p->is_error = 1;
- else
- ib_cqe_p->is_error = 0;
-
- ib_cqe_p->is_send =
- EX_FLD(cqe_p->good_cqe, arbelprm_completion_queue_entry_st, s);
- wqe_addr_ba =
- EX_FLD(cqe_p->good_cqe, arbelprm_completion_queue_entry_st,
- wqe_adr) << 6;
- ib_cqe_p->wqe = bus_to_virt(wqe_addr_ba);
-
- ib_cqe_p->count =
- EX_FLD(cqe_p->good_cqe, arbelprm_completion_queue_entry_st,
- byte_cnt);
-}
-
-static int ib_poll_cq(void *cqh, struct ib_cqe_st *ib_cqe_p, u8 * num_cqes)
-{
- int rc;
- union cqe_st cqe;
- struct cq_st *cq = cqh;
- __u8 opcode;
-
- rc = poll_cq(cq, &cqe, num_cqes);
- if (rc || ((*num_cqes) == 0)) {
- return rc;
- }
-
- dev2ib_cqe(ib_cqe_p, &cqe);
-
- opcode =
- EX_FLD(cqe.good_cqe, arbelprm_completion_queue_entry_st, opcode);
- if (opcode >= CQE_ERROR_OPCODE) {
- struct ud_send_wqe_st *wqe_p, wqe;
- __u32 *ptr;
- unsigned int i;
-
- wqe_p =
- bus_to_virt(EX_FLD
- (cqe.error_cqe,
- arbelprm_completion_with_error_st,
- wqe_addr) << 6);
- eprintf("syndrome=0x%lx",
- EX_FLD(cqe.error_cqe, arbelprm_completion_with_error_st,
- syndrome));
- eprintf("vendor_syndrome=0x%lx",
- EX_FLD(cqe.error_cqe, arbelprm_completion_with_error_st,
- vendor_code));
- eprintf("wqe_addr=0x%lx", wqe_p);
- eprintf("myqpn=0x%lx",
- EX_FLD(cqe.error_cqe, arbelprm_completion_with_error_st,
- myqpn));
- memcpy(&wqe, wqe_p, sizeof wqe);
- be_to_cpu_buf(&wqe, sizeof wqe);
-
- eprintf("dumping wqe...");
- ptr = (__u32 *) (&wqe);
- for (i = 0; i < sizeof wqe; i += 4) {
- printf("%lx : ", ptr[i >> 2]);
- }
-
- }
-
- return rc;
-}
-
-/* always work on ipoib qp */
-static int add_qp_to_mcast_group(union ib_gid_u mcast_gid, __u8 add)
-{
- void *mg;
- __u8 *tmp;
- int rc;
- __u16 mgid_hash;
- void *mgmqp_p;
-
- tmp = dev_buffers_p->inprm_buf;
- memcpy(tmp, mcast_gid.raw, 16);
- be_to_cpu_buf(tmp, 16);
- rc = cmd_mgid_hash(tmp, &mgid_hash);
- if (!rc) {
- mg = (void *)dev_buffers_p->inprm_buf;
- memset(mg, 0, MT_STRUCT_SIZE(arbelprm_mgm_entry_st));
- INS_FLD(mcast_gid.as_u32.dw[0], mg, arbelprm_mgm_entry_st,
- mgid_128_96);
- INS_FLD(mcast_gid.as_u32.dw[1], mg, arbelprm_mgm_entry_st,
- mgid_95_64);
- INS_FLD(mcast_gid.as_u32.dw[2], mg, arbelprm_mgm_entry_st,
- mgid_63_32);
- INS_FLD(mcast_gid.as_u32.dw[3], mg, arbelprm_mgm_entry_st,
- mgid_31_0);
- be_to_cpu_buf(mg +
- MT_BYTE_OFFSET(arbelprm_mgm_entry_st,
- mgid_128_96), 16);
- mgmqp_p = mg + MT_BYTE_OFFSET(arbelprm_mgm_entry_st, mgmqp_0);
- INS_FLD(dev_ib_data.ipoib_qp.qpn, mgmqp_p, arbelprm_mgmqp_st,
- qpn_i);
- INS_FLD(add, mgmqp_p, arbelprm_mgmqp_st, qi);
- rc = cmd_write_mgm(mg, mgid_hash);
- }
- return rc;
-}
-
-static int clear_interrupt(void)
-{
- writel(dev_ib_data.clr_int_data, dev_ib_data.clr_int_addr);
- return 0;
-}
-
-static struct ud_send_wqe_st *alloc_send_wqe(udqp_t qph)
-{
- struct udqp_st *qp = qph;
- __u32 idx;
-
- if (qp->snd_wqe_cur_free) {
- qp->snd_wqe_cur_free--;
- idx = qp->snd_wqe_alloc_idx;
- qp->snd_wqe_alloc_idx =
- (qp->snd_wqe_alloc_idx + 1) & (qp->max_snd_wqes - 1);
- return &qp->snd_wq[idx].wqe_cont.wqe;
- }
-
- return NULL;
-}
-
-static struct recv_wqe_st *alloc_rcv_wqe(struct udqp_st *qp)
-{
- __u32 idx;
-
- if (qp->recv_wqe_cur_free) {
- qp->recv_wqe_cur_free--;
- idx = qp->recv_wqe_alloc_idx;
- qp->recv_wqe_alloc_idx =
- (qp->recv_wqe_alloc_idx + 1) & (qp->max_recv_wqes - 1);
- return &qp->rcv_wq[idx].wqe_cont.wqe;
- }
-
- return NULL;
-}
-
-static int free_send_wqe(struct ud_send_wqe_st *wqe)
-{
- struct udqp_st *qp = ((struct ude_send_wqe_cont_st *)wqe)->qp;
- qp->snd_wqe_cur_free++;
-
- return 0;
-}
-
-static int free_rcv_wqe(struct recv_wqe_st *wqe)
-{
- struct udqp_st *qp = ((struct recv_wqe_cont_st *)wqe)->qp;
- qp->recv_wqe_cur_free++;
-
- return 0;
-}
-
-static int free_wqe(void *wqe)
-{
- int rc = 0;
- struct recv_wqe_st *rcv_wqe;
-
-// tprintf("free wqe= 0x%x", wqe);
- if ((wqe >= (void *)(dev_ib_data.ipoib_qp.rcv_wq)) &&
- (wqe <
- (void *)(&dev_ib_data.ipoib_qp.rcv_wq[NUM_IPOIB_RCV_WQES]))) {
- /* ipoib receive wqe */
- free_rcv_wqe(wqe);
- rcv_wqe = alloc_rcv_wqe(&dev_ib_data.ipoib_qp);
- if (rcv_wqe) {
- rc = post_rcv_buf(&dev_ib_data.ipoib_qp, rcv_wqe);
- if (rc) {
- eprintf("");
- }
- }
- } else if (wqe >= (void *)(dev_ib_data.ipoib_qp.snd_wq) &&
- wqe <
- (void *)(&dev_ib_data.ipoib_qp.snd_wq[NUM_IPOIB_SND_WQES])) {
- /* ipoib send wqe */
- free_send_wqe(wqe);
- } else if (wqe >= (void *)(dev_ib_data.mads_qp.rcv_wq) &&
- wqe <
- (void *)(&dev_ib_data.mads_qp.rcv_wq[NUM_MADS_RCV_WQES])) {
- /* mads receive wqe */
- free_rcv_wqe(wqe);
- rcv_wqe = alloc_rcv_wqe(&dev_ib_data.mads_qp);
- if (rcv_wqe) {
- rc = post_rcv_buf(&dev_ib_data.mads_qp, rcv_wqe);
- if (rc) {
- eprintf("");
- }
- }
- } else if (wqe >= (void *)(dev_ib_data.mads_qp.snd_wq) &&
- wqe <
- (void *)(&dev_ib_data.mads_qp.snd_wq[NUM_MADS_SND_WQES])) {
- /* mads send wqe */
- free_send_wqe(wqe);
- } else {
- rc = -1;
- eprintf("");
- }
-
- return rc;
-}
-
-static int update_eq_cons_idx(struct eq_st *eq)
-{
- writel(eq->cons_counter, eq->ci_base_base_addr);
- return 0;
-}
-
-static void dev2ib_eqe(struct ib_eqe_st *ib_eqe_p, struct eqe_t *eqe_p)
-{
- void *tmp;
-
- ib_eqe_p->event_type =
- EX_FLD(eqe_p, arbelprm_event_queue_entry_st, event_type);
-
- tmp = eqe_p + MT_BYTE_OFFSET(arbelprm_event_queue_entry_st, event_data);
- ib_eqe_p->cqn = EX_FLD(tmp, arbelprm_completion_event_st, cqn);
-}
-
-static int poll_eq(struct ib_eqe_st *ib_eqe_p, __u8 * num_eqes)
-{
- struct eqe_t eqe;
- u8 owner;
- int rc;
- u32 *ptr;
- struct eq_st *eq = &dev_ib_data.eq;
- __u32 cons_idx = eq->cons_counter & (eq->eq_size - 1);
-
- ptr = (u32 *) (&(eq->eq_buf[cons_idx]));
- owner = (ptr[7] & 0x80000000) ? OWNER_HW : OWNER_SW;
- if (owner == OWNER_SW) {
- eqe = eq->eq_buf[cons_idx];
- be_to_cpu_buf(&eqe, sizeof(eqe));
- dev2ib_eqe(ib_eqe_p, &eqe);
- ptr[7] |= 0x80000000;
- eq->eq_buf[cons_idx] = eqe;
- eq->cons_counter++;
- rc = update_eq_cons_idx(eq);
- if (rc) {
- return -1;
- }
- *num_eqes = 1;
- } else {
- *num_eqes = 0;
- }
- return 0;
-}
-
-static int ib_device_close(void)
-{
- iounmap(memfree_pci_dev.uar);
- iounmap(memfree_pci_dev.cr_space);
- return 0;
-}
-
-static __u32 dev_get_qpn(void *qph)
-{
- struct udqp_st *qp = qph;
-
- return qp->qpn;
-}
-
-static void dev_post_dbell(void *dbell, __u32 offset)
-{
- __u32 *ptr;
- unsigned long address;
-
- ptr = dbell;
-
- if (((ptr[0] >> 24) & 0xff) != 1) {
- eprintf("");
- }
- tprintf("ptr[0]= 0x%lx", ptr[0]);
- tprintf("ptr[1]= 0x%lx", ptr[1]);
- address = (unsigned long)(memfree_pci_dev.uar) + offset;
- tprintf("va=0x%lx pa=0x%lx", address,
- virt_to_bus((const void *)address));
- writel(htonl(ptr[0]), memfree_pci_dev.uar + offset);
- barrier();
- address += 4;
- tprintf("va=0x%lx pa=0x%lx", address,
- virt_to_bus((const void *)address));
- writel(htonl(ptr[1]), address /*memfree_pci_dev.uar + offset + 4 */ );
-}
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-
-#include "ipoib.h"
-#include "ib_driver.h"
-#include "ib_mad.h"
-
-static const __u8 arp_packet_template[] = {
- 0x00, 0x20, /* hardware type */
- 0x08, 0x00, /* protocol type */
- 20, /* hw size */
- 4, /* protocol size */
- 0x00, 0x00, /* opcode */
-
- 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, /* sender's mac */
- 0, 0, 0, 0, /* sender's IP address */
-
- 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, /* Target's mac */
- 0, 0, 0, 0 /* targets's IP address */
-};
-
-struct ipoib_data_st {
- __u32 ipoib_qpn;
- udqp_t ipoib_qph;
- ud_av_t bcast_av;
- cq_t snd_cqh;
- cq_t rcv_cqh;
- __u8 *port_gid_raw;
-} ipoib_data;
-
-#define NUM_MAC_ENTRIES (NUM_AVS+2)
-
-static struct mac_xlation_st mac_tbl[NUM_MAC_ENTRIES];
-static __u32 mac_counter = 1;
-static __u32 youth_counter = 0;
-
-#define EQUAL_GUIDS(g1, g2) ( \
- ((g1)[0]==(g2)[0]) && \
- ((g1)[1]==(g2)[1]) && \
- ((g1)[2]==(g2)[2]) && \
- ((g1)[3]==(g2)[3]) && \
- ((g1)[4]==(g2)[4]) && \
- ((g1)[5]==(g2)[5]) && \
- ((g1)[6]==(g2)[6]) && \
- ((g1)[7]==(g2)[7]) )
-
-#define MAC_IDX(i) (((mac_tbl[i].eth_mac_lsb[0])<<16) | \
- ((mac_tbl[i].eth_mac_lsb[0])<<8) | \
- (mac_tbl[i].eth_mac_lsb[0]))
-
-static inline const void *qpn2buf(__u32 qpn, const void *buf)
-{
- ((__u8 *) buf)[0] = qpn >> 16;
- ((__u8 *) buf)[1] = (qpn >> 8) & 0xff;
- ((__u8 *) buf)[2] = qpn & 0xff;
- return buf;
-}
-
-static inline __u32 buf2qpn(const void *buf)
-{
- __u32 qpn;
-
- qpn = ((((__u8 *) buf)[0]) << 16) +
- ((((__u8 *) buf)[1]) << 8) + (((__u8 *) buf)[2]);
-
- return qpn;
-}
-
-static int is_bcast_mac(const char *dest)
-{
- int i;
- __u8 mac = 0xff;
-
- for (i = 0; i < 6; ++i)
- mac &= dest[i];
-
- return mac == 0xff;
-}
-
-/* find a free entry. if not found kick
- * another entry.
- */
-static int find_free_entry(void)
-{
- __u32 youth = 0xffffffff;
- __u8 i, remove_idx = NUM_MAC_ENTRIES;
-
- /* find a free entry */
- for (i = 0; i < NUM_MAC_ENTRIES; ++i) {
- if (!mac_tbl[i].valid) {
- mac_tbl[i].valid = 1;
- mac_tbl[i].youth = youth_counter;
- youth_counter++;
- return i;
- }
- }
-
- for (i = 0; i < NUM_MAC_ENTRIES; ++i) {
- if ((mac_tbl[i].av == NULL) && (mac_tbl[i].youth < youth)) {
- youth = mac_tbl[i].youth;
- remove_idx = i;
- }
- }
-
- if (remove_idx < NUM_MAC_ENTRIES) {
- /* update the new youth value */
- mac_tbl[remove_idx].youth = youth_counter;
- youth_counter++;
- return remove_idx;
- } else {
- tprintf("did not find an entry to kick");
- return -1;
- }
-}
-
-static int find_qpn_gid(__u32 qpn, const __u8 * gid)
-{
- __u16 i;
-
- for (i = 0; i < NUM_MAC_ENTRIES; ++i) {
- if (mac_tbl[i].valid &&
- (mac_tbl[i].qpn == qpn) &&
- !memcmp(mac_tbl[i].gid.raw, gid, 16)) {
- return i;
- }
- }
- return -1;
-}
-
-static void allocate_new_mac6(__u8 * mac_lsb)
-{
- __u32 eth_counter;
-
- eth_counter = mac_counter;
- mac_counter = (mac_counter + 1) & 0xffffff;
-
- mac_lsb[0] = eth_counter >> 16;
- mac_lsb[1] = eth_counter >> 8;
- mac_lsb[2] = eth_counter & 0xff;
- tprintf("add mac: %x:%x:%x", mac_lsb[0], mac_lsb[1], mac_lsb[2]);
-}
-
-static void modify_arp_reply(__u8 * eth_mac_lsb, void *data)
-{
- __u8 *packet;
-
- /* skip 4 bytes */
- packet = ((__u8 *) data) + 4;
-
- /* modify hw type */
- packet[0] = 0;
- packet[1] = 1;
-
- /* modify hw size */
- packet[4] = 6;
-
- /* modify sender's mac */
- packet[8] = MLX_ETH_BYTE0;
- packet[9] = MLX_ETH_BYTE1;
- packet[10] = MLX_ETH_BYTE2;
- packet[11] = eth_mac_lsb[0];
- packet[12] = eth_mac_lsb[1];
- packet[13] = eth_mac_lsb[2];
-
- /* move sender's IP address */
- memcpy(packet + 14, packet + 28, 4);
-
- /* set target MAC - that's us */
- packet[18] = MLX_ETH_BYTE0;
- packet[19] = MLX_ETH_BYTE1;
- packet[20] = MLX_ETH_BYTE2;
- packet[21] = 0;
- packet[22] = 0;
- packet[23] = 0;
-
- /* move target's IP address */
- memcpy(packet + 24, packet + 52, 4);
-}
-
-static void modify_arp_request(__u8 * eth_mac_lsb, void *data)
-{
- __u8 *packet;
-
- /* skip 4 bytes */
- packet = ((__u8 *) data) + 4;
-
- /* modify hw type */
- packet[0] = 0;
- packet[1] = 1;
-
- /* modify hw size */
- packet[4] = 6;
-
- /* modify sender's mac */
- packet[8] = MLX_ETH_BYTE0;
- packet[9] = MLX_ETH_BYTE1;
- packet[10] = MLX_ETH_BYTE2;
- packet[11] = eth_mac_lsb[0];
- packet[12] = eth_mac_lsb[1];
- packet[13] = eth_mac_lsb[2];
-
- /* move sender's IP address */
- memcpy(packet + 14, packet + 28, 4);
-
- /* set target MAC - that's us */
- packet[18] = 0;
- packet[19] = 0;
- packet[20] = 0;
- packet[21] = 0;
- packet[22] = 0;
- packet[23] = 0;
-
- /* move target's IP address */
- memcpy(packet + 24, packet + 52, 4);
-}
-
-static int handle_arp_packet(void *buf, void **out_buf_p,
- unsigned int *new_size_p)
-{
- __u16 opcode;
- const void *p;
- const __u8 *gid;
- __u32 qpn;
- int idx;
-
- opcode = get_opcode(buf);
- switch (opcode) {
- case ARP_OP_REQUESET:
- case ARP_OP_REPLY:
- break;
-
- default:
- return -1;
- }
-
- p = arp_mac20_get_sender_qpn(buf);
- qpn = buf2qpn(p);
- gid = arp_mac20_get_sender_gid(buf);
-
- if (!memcmp(gid, get_port_gid(), 16)) {
- /* my own gid */
- *out_buf_p = NULL;
- return 0;
- }
-
- idx = find_qpn_gid(qpn, gid);
- if (idx == -1) {
- /* entry not in the table */
- idx = find_free_entry();
- if (idx == -1) {
- eprintf("we're in broch\n");
- return -1;
- }
- allocate_new_mac6(mac_tbl[idx].eth_mac_lsb);
- mac_tbl[idx].av = NULL; // free the av id it exists ?? !!
- mac_tbl[idx].qpn = qpn;
- memcpy(mac_tbl[idx].gid.raw, gid, 16);
- }
-
- if (opcode == ARP_OP_REQUESET) {
- modify_arp_request(mac_tbl[idx].eth_mac_lsb, buf);
- } else {
- /* we want to filter possible broadcast arp
- replies not directed to us */
- p = arp_mac20_get_target_qpn(buf);
- qpn = buf2qpn(p);
- gid = arp_mac20_get_target_gid(buf);
-
- if ((qpn != ipoib_data.ipoib_qpn) ||
- (memcmp(gid, get_port_gid(), 16))) {
- *out_buf_p = NULL;
- return 0;
- }
-
- modify_arp_reply(mac_tbl[idx].eth_mac_lsb, buf);
- {
- __u8 i;
- tprintf("arp reply dump:\n");
- for (i = 4; i < 32; ++i) {
- tprintf("%x: ", ((__u8 *) buf)[i]);
- }
- tprintf("\n");
- }
- }
- *out_buf_p = ((__u8 *) buf) + 4;
- *new_size_p = 28; /* size of eth arp packet */
-
- tprintf("");
-
- return 0;
-}
-
-static void modify_udp_csum(void *buf, __u16 size)
-{
- __u8 *ptr = (__u8 *) buf;
- __u32 csum = 0;
- __u16 chksum;
- __u16 buf_size;
- __u16 *tmp;
- int i;
-
- buf_size = (size & 1) ? size + 1 : size;
- tmp = (__u16 *) (ptr + 12); /* src and dst ip addresses */
- for (i = 0; i < 4; ++i) {
- csum += tmp[i];
- }
-
- csum += 0x1100; // udp protocol
-
- tmp = (__u16 *) (ptr + 26);
- tmp[0] = 0; /* zero the checksum */
-
- tmp = (__u16 *) (ptr + 24);
- csum += tmp[0];
-
- tmp = (__u16 *) (ptr + 20);
-
- for (i = 0; i < ((buf_size - 20) >> 1); ++i) {
- csum += tmp[i];
- }
-
- chksum = ~((__u16) ((csum & 0xffff) + (csum >> 16)));
-
- tmp = (__u16 *) (ptr + 26);
- tmp[0] = chksum; /* set the checksum */
-}
-
-static void modify_dhcp_resp(void *buf, __u16 size)
-{
- set_eth_hwtype(buf);
- set_eth_hwlen(buf);
- set_own_mac(buf);
- modify_udp_csum(buf, size);
-}
-
-static void get_my_client_id(__u8 * my_client_id)
-{
-
- my_client_id[0] = 0;
- qpn2buf(ipoib_data.ipoib_qpn, my_client_id + 1);
- memcpy(my_client_id + 4, ipoib_data.port_gid_raw, 16);
-}
-
-static const __u8 *get_client_id(const void *buf, int len)
-{
- const __u8 *ptr;
- int delta;
-
- if (len < 268)
- return NULL;
-
- /* pointer to just after magic cookie */
- ptr = (const __u8 *)buf + 268;
-
- /* find last client identifier option */
- do {
- if (ptr[0] == 255) {
- /* found end of options list */
- return NULL;
- }
-
- if (ptr[0] == 0x3d) {
- /* client identifer option */
- return ptr + 3;
- }
-
- delta = ptr[1] + 2;
- ptr += delta;
- len -= delta;
- } while (len > 0);
-
- return NULL;
-}
-
-static int handle_ipv4_packet(void *buf, void **out_buf_p,
- unsigned int *new_size_p, int *is_bcast_p)
-{
- void *new_buf;
- __u16 new_size;
- __u8 msg_type;
- __u8 my_client_id[20];
-
- new_buf = (void *)(((__u8 *) buf) + 4);
- new_size = (*new_size_p) - 4;
- *out_buf_p = new_buf;
- *new_size_p = new_size;
-
- if (get_ip_protocl(new_buf) == IP_PROT_UDP) {
- __u16 udp_dst_port;
- const __u8 *client_id;
-
- udp_dst_port = get_udp_dst_port(new_buf);
-
- if (udp_dst_port == 67) {
- /* filter dhcp requests */
- *out_buf_p = 0;
- return 0;
- }
-
- if (udp_dst_port == 68) {
- get_my_client_id(my_client_id);
-
- /* packet client id */
- client_id = get_client_id(new_buf, new_size);
- if (!client_id) {
- *out_buf_p = 0;
- return 0;
- }
-
- if (memcmp(client_id, my_client_id, 20)) {
- *out_buf_p = 0;
- return 0;
- }
- }
- }
-
- msg_type = get_dhcp_msg_type(new_buf);
- if ((get_ip_protocl(new_buf) == IP_PROT_UDP) &&
- (get_udp_dst_port(new_buf) == 68) &&
- ((msg_type == DHCP_TYPE_RESPONSE) || (msg_type == DHCP_TYPE_ACK))
- ) {
- *is_bcast_p = 1;
- modify_dhcp_resp(new_buf, new_size);
- }
-
- return 0;
-}
-
-static int is_valid_arp(void *buf, unsigned int size)
-{
- __u8 *ptr = buf;
- __u16 tmp;
-
- if (size != 60) {
- eprintf("");
- return 0;
- }
- if (be16_to_cpu(*((__u16 *) ptr)) != ARP_PROT_TYPE)
- return 0;
-
- if (be16_to_cpu(*((__u16 *) (ptr + 4))) != IPOIB_HW_TYPE)
- return 0;
-
- if (be16_to_cpu(*((__u16 *) (ptr + 6))) != IPV4_PROT_TYPE)
- return 0;
-
- if (ptr[8] != 20) /* hw addr len */
- return 0;
-
- if (ptr[9] != 4) /* protocol len = 4 for IP */
- return 0;
-
- tmp = be16_to_cpu(*((__u16 *) (ptr + 10)));
- if ((tmp != ARP_OP_REQUESET) && (tmp != ARP_OP_REPLY))
- return 0;
-
- return 1;
-}
-
-static int ipoib_handle_rcv(void *buf, void **out_buf_p,
- unsigned int *new_size_p, int *is_bcast_p)
-{
- __u16 prot_type;
- int rc;
-
- prot_type = get_prot_type(buf);
- switch (prot_type) {
- case ARP_PROT_TYPE:
- tprintf("");
- if (is_valid_arp(buf, *new_size_p)) {
- tprintf("got valid arp");
- rc = handle_arp_packet(buf, out_buf_p, new_size_p);
- if (rc) {
- eprintf("");
- return rc;
- }
- if (!out_buf_p) {
- tprintf("");
- }
- tprintf("arp for me");
- *is_bcast_p = 1;
- return rc;
- } else {
- tprintf("got invalid arp");
- *out_buf_p = NULL;
- return 0;
- }
-
- case IPV4_PROT_TYPE:
- tprintf("");
- rc = handle_ipv4_packet(buf, out_buf_p, new_size_p, is_bcast_p);
- return rc;
- }
- eprintf("prot=0x%x", prot_type);
- return -1;
-}
-
-static int is_null_mac(const __u8 * mac)
-{
- __u8 i, tmp = 0;
- __u8 lmac[6];
-
- memcpy(lmac, mac, 6);
-
- for (i = 0; i < 6; ++i) {
- tmp |= lmac[i];
- }
-
- if (tmp == 0)
- return 1;
- else
- return 0;
-}
-
-static int find_mac(const __u8 * mac)
-{
- int i;
- const __u8 *tmp = mac + 3;
-
- for (i = 0; i < NUM_MAC_ENTRIES; ++i) {
- tprintf("checking 0x%02x:0x%02x:0x%02x valid=%d",
- mac_tbl[i].eth_mac_lsb[0], mac_tbl[i].eth_mac_lsb[1],
- mac_tbl[i].eth_mac_lsb[2], mac_tbl[i].valid);
- if (mac_tbl[i].valid && !memcmp(mac_tbl[i].eth_mac_lsb, tmp, 3))
- return i;
- }
- tprintf("mac: %x:%x:%x - dumping", tmp[0], tmp[1], tmp[2]);
- for (i = 0; i < NUM_MAC_ENTRIES; ++i) {
- //__u8 *gid= mac_tbl[i].gid.raw;
- //__u8 *m= mac_tbl[i].eth_mac_lsb;
- /*if (mac_tbl[i].valid) {
- tprintf("%d: qpn=0x%lx, "
- "gid=%x:%x:%x:%x:%x:%x:%x:%x:%x:%x:%x:%x:%x:%x:%x:%x, "
- "av=0x%lx, "
- "youth= %ld, "
- "mac=%x:%x:%x\n",
- i, mac_tbl[i].qpn,
- gid[0], gid[1], gid[2], gid[3], gid[4], gid[5], gid[6], gid[7],
- gid[8], gid[9], gid[10], gid[11], gid[12], gid[13], gid[14], gid[15],
- mac_tbl[i].av, mac_tbl[i].youth,
- m[0], m[1], m[2]);
- } */
- }
- return -1;
-}
-
-static int send_bcast_packet(__u16 protocol, const void *data, __u16 size)
-{
- ud_send_wqe_t snd_wqe, tmp_wqe;
- int rc;
- int is_good;
- void *send_buffer;
-
- snd_wqe = alloc_send_wqe(ipoib_data.ipoib_qph);
- if (!snd_wqe) {
- eprintf("");
- return -1;
- }
-
- send_buffer = get_send_wqe_buf(snd_wqe, 0);
- *((__u32 *) send_buffer) = cpu_to_be32(protocol << 16);
- prep_send_wqe_buf(ipoib_data.ipoib_qph, ipoib_data.bcast_av,
- snd_wqe, data, 4, size, 0);
-
- rc = post_send_req(ipoib_data.ipoib_qph, snd_wqe, 1);
- if (rc) {
- eprintf("");
- goto ex;
- }
-
- rc = poll_cqe_tout(ipoib_data.snd_cqh, SEND_CQE_POLL_TOUT, &tmp_wqe,
- &is_good);
- if (rc) {
- eprintf("");
- goto ex;
- }
- if (!is_good) {
- eprintf("");
- rc = -1;
- goto ex;
- }
- if (tmp_wqe != snd_wqe) {
- eprintf("");
- rc = -1;
- goto ex;
- }
-
- ex:free_wqe(snd_wqe);
- return rc;
-}
-
-static int send_ucast_packet(const __u8 * mac, __u16 protocol, const void *data,
- __u16 size)
-{
- ud_send_wqe_t snd_wqe, tmp_wqe;
- ud_av_t av;
- udqp_t qph;
- __u16 dlid;
- __u8 sl, rate;
- int rc;
- int i;
- int is_good;
-
- i = find_mac(mac);
- if (i < 0) {
- tprintf("");
- return -1;
- }
-
- if (!mac_tbl[i].av) {
- rc = get_path_record(&mac_tbl[i].gid, &dlid, &sl, &rate);
- if (rc) {
- eprintf("");
- return -1;
- } else {
- tprintf("get_path_record() success dlid=0x%x", dlid);
- }
-
- /* no av - allocate one */
- av = alloc_ud_av();
- if (!av) {
- eprintf("");
- return -1;
- }
- modify_av_params(av, dlid, 1, sl, rate, &mac_tbl[i].gid,
- mac_tbl[i].qpn);
- mac_tbl[i].av = av;
- } else {
- av = mac_tbl[i].av;
- }
- qph = ipoib_data.ipoib_qph;
- snd_wqe = alloc_send_wqe(qph);
- if (!snd_wqe) {
- eprintf("");
- return -1;
- }
-
- *((__u32 *) get_send_wqe_buf(snd_wqe, 0)) = cpu_to_be32(protocol << 16);
- prep_send_wqe_buf(qph, av, snd_wqe, data, 4, size, 0);
-
- rc = post_send_req(qph, snd_wqe, 1);
- if (rc) {
- eprintf("");
- return -1;
- }
-
- rc = poll_cqe_tout(ipoib_data.snd_cqh, SEND_CQE_POLL_TOUT, &tmp_wqe,
- &is_good);
- if (rc) {
- eprintf("");
- goto ex;
- }
- if (!is_good) {
- eprintf("");
- rc = -1;
- goto ex;
- }
- if (tmp_wqe != snd_wqe) {
- eprintf("");
- rc = -1;
- goto ex;
- }
-
- ex:free_wqe(snd_wqe);
- return rc;
-}
-
-static void *alloc_convert_arp6_msg(const void *data,
- struct arp_packet_st *ipoib_arp)
-{
- void *buf;
- const void *p1;
- int idx;
- __u8 qpn[3];
-
- memcpy(ipoib_arp, arp_packet_template, sizeof arp_packet_template);
- buf = ipoib_arp;
-
- /* update opcode */
- p1 = arp_mac6_get_opcode(data);
- arp_mac20_set_opcode(p1, buf);
-
- /* update sender ip */
- p1 = arp_mac6_get_sender_ip(data);
- arp_mac20_set_sender_ip(p1, buf);
-
- /* update target ip */
- p1 = arp_mac6_get_target_ip(data);
- arp_mac20_set_target_ip(p1, buf);
-
- /* update sender mac */
- qpn2buf(ipoib_data.ipoib_qpn, qpn);
- arp_mac20_set_sender_mac(qpn, ipoib_data.port_gid_raw, buf);
-
- /* update target mac */
- p1 = arp_mac6_get_target_mac(data);
- if (!is_null_mac(p1)) {
- idx = find_mac(p1);
- if (idx == -1) {
- __u8 *_ptr = (__u8 *) p1;
- eprintf("could not find mac %x:%x:%x",
- _ptr[3], _ptr[4], _ptr[5]);
- return NULL;
- }
- qpn2buf(mac_tbl[idx].qpn, qpn);
- arp_mac20_set_target_mac(qpn, mac_tbl[idx].gid.raw, buf);
- }
-
- return buf;
-}
-
-static __u16 set_client_id(__u8 * packet)
-{
- __u8 *ptr;
- __u8 y[3];
- __u16 new_size;
-
- /* pointer to just after magic cookie */
- ptr = packet + 268;
-
- /* find last option */
- do {
- if (ptr[0] == 255) {
- /* found end of options list */
- break;
- }
- ptr = ptr + ptr[1] + 2;
- } while (1);
-
- ptr[0] = 61; /* client id option identifier */
- ptr[1] = 21; /* length of the option */
- ptr[2] = IPOIB_HW_TYPE;
- ptr[3] = 0;
- qpn2buf(ipoib_data.ipoib_qpn, y);
- memcpy(ptr + 4, y, 3);
- memcpy(ptr + 7, ipoib_data.port_gid_raw, 16);
- ptr[23] = 255;
- new_size = (__u16) (ptr + 24 - packet);
- if (new_size & 3) {
- new_size += (4 - (new_size & 3));
- }
- return new_size;
-}
-
-static __u16 calc_udp_csum(__u8 * packet)
-{
- __u16 *ptr;
- int i;
- __u32 sum = 0;
- __u16 udp_length, udp_csum;
-
- /* src ip, dst ip */
- ptr = (__u16 *) (packet + 12);
- for (i = 0; i < 4; ++i) {
- sum += be16_to_cpu(ptr[i]);
- }
-
- /* udp protocol */
- sum += IP_PROT_UDP;
-
- /* udp length */
- ptr = (__u16 *) (packet + 24);
- udp_length = be16_to_cpu(*ptr);
- sum += udp_length;
-
- /* udp part */
- ptr = (__u16 *) (packet + 20);
- do {
- sum += be16_to_cpu(*ptr);
- ptr++;
- udp_length -= 2;
- } while (udp_length);
-
- udp_csum = ~((__u16) ((sum & 0xffff) + (sum >> 16)));
- return udp_csum;
-}
-
-static __u16 modify_dhcp_request(__u8 * packet, __u16 size)
-{
- __u16 csum, new_size;
-
- set_hw_type(packet);
- zero_hw_len(packet);
- zero_chaddr(packet);
- set_bcast_flag(packet);
- new_size = set_client_id(packet);
- if (new_size > size) {
- add_udp_len(packet, new_size - size);
- } else
- new_size = size;
- set_udp_csum(packet, 0);
- csum = calc_udp_csum(packet);
- set_udp_csum(packet, csum);
- return new_size;
-}
-
-static __u16 copy_dhcp_message(__u8 * buf, const void *packet, __u16 size)
-{
- memcpy(buf, packet, size);
- return size;
-}
-
-static void modify_ip_hdr(__u8 * buf, __u16 add_size)
-{
- __u16 *ptr, ip_csum;
- __u16 tmp;
- __u32 sum = 0;
- __u8 i;
-
- /* update ip length */
- ptr = (__u16 *) buf;
- tmp = be16_to_cpu(ptr[1]);
- ptr[1] = cpu_to_be16(tmp + add_size);
-
- ptr[5] = 0; /* zero csum */
- for (i = 0; i < 10; ++i) {
- sum += be16_to_cpu(ptr[i]);
- }
-
- ip_csum = ~((__u16) ((sum & 0xffff) + (sum >> 16)));
- ptr[5] = cpu_to_be16(ip_csum);
-
-}
-
-static void *update_dhcp_request(const void *packet, unsigned int size,
- __u16 * new_size_p)
-{
- __u8 ip_proto, dhcp_message_type;
- __u16 dest_port, new_size, orig_size;
- static __u8 dhcp_send_buffer[576];
-
- ip_proto = get_ip_protocl_type(packet);
- if (ip_proto != IP_PROT_UDP) {
- return NULL;
- }
-
- dest_port = get_udp_dest_port(packet);
- if (dest_port != 0x4300 /*67 */ )
- return NULL;
-
- dhcp_message_type = get_dhcp_message_type(packet);
- if (dhcp_message_type != DHCP_TYPE_REQUEST)
- return NULL;
-
- memset(dhcp_send_buffer, 0, sizeof dhcp_send_buffer);
- orig_size = copy_dhcp_message(dhcp_send_buffer, packet, size);
-
- new_size = modify_dhcp_request(dhcp_send_buffer, orig_size);
- if (new_size != orig_size) {
- modify_ip_hdr(dhcp_send_buffer, new_size - orig_size);
- }
- *new_size_p = new_size;
- return dhcp_send_buffer;
-}
-
-static int ipoib_send_packet(const __u8 * mac, __u16 protocol, const void *data,
- unsigned int size)
-{
- const void *packet;
- __u16 new_size, dhcp_req_sz;
- void *tmp;
- int rc;
- struct arp_packet_st ipoib_arp;
-
- tprintf("");
-
- if (protocol == ARP_PROT_TYPE) {
- /* special treatment for ARP */
- tmp = alloc_convert_arp6_msg(data, &ipoib_arp);
- if (!tmp) {
- eprintf("");
- return -1;
- }
- packet = tmp;
- new_size = sizeof(struct arp_packet_st);
- tprintf("sending arp");
- } else {
- tmp = update_dhcp_request(data, size, &dhcp_req_sz);
- if (tmp) {
- /* it was a dhcp request so we use a special
- buffer because we may have to enlarge the size of the packet */
- tprintf("sending dhcp");
- packet = tmp;
- new_size = dhcp_req_sz;
- } else {
- packet = data;
- new_size = size;
- tprintf("sending packet");
- }
- }
-
- //eprintf("press key ..."); getchar();
- if (is_bcast_mac(mac)) {
- tprintf("");
- rc = send_bcast_packet(protocol, packet, new_size);
- } else {
- tprintf("");
- rc = send_ucast_packet(mac, protocol, packet, new_size);
- }
-
- return rc;
-}
-
-static int ipoib_read_packet(__u16 * prot_p, void *data, unsigned int *size_p,
- int *is_bcast_p)
-{
- int rc;
- struct ib_cqe_st ib_cqe;
- __u8 num_cqes;
- unsigned int new_size;
- void *buf, *out_buf;
- __u16 prot_type;
-
- rc = ib_poll_cq(ipoib_data.rcv_cqh, &ib_cqe, &num_cqes);
- if (rc) {
- return rc;
- }
-
- if (num_cqes == 0) {
- *size_p = 0;
- return 0;
- }
-
- if (ib_cqe.is_error) {
- eprintf("");
- rc = -1;
- goto ex_func;
- }
-
- new_size = ib_cqe.count - GRH_SIZE;
- buf = get_rcv_wqe_buf(ib_cqe.wqe, 1);
- tprintf("buf=%lx", buf);
- rc = ipoib_handle_rcv(buf, &out_buf, &new_size, is_bcast_p);
- if (rc) {
- eprintf("");
- rc = -1;
- goto ex_func;
- }
- if (out_buf) {
- tprintf("");
- prot_type = get_prot_type(buf);
- *size_p = new_size;
- tprintf("new_size=%d", new_size);
- if (new_size > 1560) {
- eprintf("sizzzzzze = %d", new_size);
- } else {
- memcpy(data, out_buf, new_size);
- }
- *prot_p = prot_type;
- } else {
- tprintf("skip message");
- *size_p = 0;
- }
-
- ex_func:
- if (free_wqe(ib_cqe.wqe)) {
- eprintf("");
- }
-
- return rc;
-}
-
-static int ipoib_init(struct pci_device *pci)
-{
- int rc;
- udqp_t qph;
- int i;
-
- tprintf("");
- rc = ib_driver_init(pci, &qph);
- if (rc)
- return rc;
-
- tprintf("");
- ipoib_data.ipoib_qph = qph;
- ipoib_data.ipoib_qpn = ib_get_qpn(qph);
-
- if(print_info)
- printf("local ipoib qpn=0x%x\n", ipoib_data.ipoib_qpn);
-
- ipoib_data.bcast_av = ib_data.bcast_av;
- ipoib_data.port_gid_raw = ib_data.port_gid.raw;
- ipoib_data.snd_cqh = ib_data.ipoib_snd_cq;
- ipoib_data.rcv_cqh = ib_data.ipoib_rcv_cq;
-
- mac_counter = 1;
- youth_counter = 0;
- for (i = 0; i < NUM_MAC_ENTRIES; ++i) {
- mac_tbl[i].valid = 0;
- mac_tbl[i].av = NULL;
- }
-
- return 0;
-}
-
-static int ipoib_close(int fw_fatal)
-{
- int rc;
-
- rc = ib_driver_close(fw_fatal);
-
- return rc;
-}
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-
-#ifndef __ipoib_h__
-#define __ipoib_h__
-
-#define ARP_PROT_TYPE 0x806
-#define IPV4_PROT_TYPE 0x800
-
-#define IPOIB_HW_TYPE 0x20
-#define ETH_HW_TYPE 1
-
-#define ARP_OP_REQUESET 1
-#define ARP_OP_REPLY 2
-
-#define MLX_ETH_3BYTE_PREFIX 0x2c9 /* 00,02,c9 */
-#define MLX_ETH_BYTE0 0
-#define MLX_ETH_BYTE1 2
-#define MLX_ETH_BYTE2 0xC9
-
-#define IP_PROT_UDP 17
-#define DHCP_TYPE_REQUEST 1
-#define DHCP_TYPE_RESPONSE 2
-#define DHCP_TYPE_ACK 5
-
-struct ipoib_mac_st {
- __u32 qpn:24;
- __u32 r0:8;
- __u8 gid[16];
-} __attribute__ ((packed));
-
-struct arp_packet_st {
- __u16 arp_prot_type;
- __u16 hw_type;
- __u16 opcode;
- __u8 prot_size;
- __u8 hw_len;
- struct ipoib_mac_st sender_mac;
- __u32 sender_ip;
- struct ipoib_mac_st target_mac;
- __u32 target_ip;
-} __attribute__ ((packed));
-
-/* this struct is used to translate between ipoib and
- ethernet mac addresses */
-struct mac_xlation_st {
- __u8 valid; /* 1=entry valid 0=entry free */
- __u32 youth; /* youth of this entry the lowest the
- number the older in age */
- __u8 eth_mac_lsb[3]; /* three bytes Ethernet MAC
- LS bytes are constants */
- union ib_gid_u gid;
- __u32 qpn;
- ud_av_t av; /* address vector representing neighbour */
-};
-
-static inline __u16 get_prot_type(void *data)
-{
- __u8 *ptr = data;
-
- return be16_to_cpu(*((__u16 *) ptr));
-}
-
-static inline __u8 get_hw_len(void *data)
-{
- return ((__u8 *) data)[8];
-}
-
-static inline __u8 get_prot_size(void *data)
-{
- return ((__u8 *) data)[9];
-}
-
-static inline __u16 get_opcode(const void *data)
-{
- return be16_to_cpu(*((__u16 *) (&(((__u8 *) data)[10]))));
-}
-
-static inline __u32 get_sender_qpn(void *data)
-{
- __u8 *ptr = data;
-
- return (ptr[13] << 16) | (ptr[14] << 8) | ptr[15];
-}
-
-static inline const __u8 *get_sender_gid(void *data)
-{
- return &(((__u8 *) data)[16]);
-}
-
-static inline void *arp_mac6_get_sender_ip(const void *data)
-{
- return (__u8 *) data + 14;
-}
-
-static inline const void *arp_mac6_get_target_ip(const void *data)
-{
- return data + 24;
-}
-
-static inline void arp_mac20_set_sender_ip(const void *ip, void *data)
-{
- memcpy(((__u8 *) data) + 28, ip, 4);
-}
-
-static inline void arp_mac20_set_target_ip(const void *ip, void *data)
-{
- memcpy(((__u8 *) data) + 52, ip, 4);
-}
-
-static inline void arp_mac20_set_sender_mac(const void *qpn, const void *gid,
- void *data)
-{
- memcpy(((__u8 *) data) + 9, qpn, 3);
- memcpy(((__u8 *) data) + 12, gid, 16);
-}
-
-static inline void arp_mac20_set_target_mac(void *qpn, void *gid, void *data)
-{
- memcpy(((__u8 *) data) + 33, qpn, 3);
- memcpy(((__u8 *) data) + 36, gid, 16);
-}
-
-static inline const void *arp_mac6_get_opcode(const void *data)
-{
- return data + 6;
-}
-
-static inline void arp_mac20_set_opcode(const void *opcode, void *data)
-{
- memcpy(data + 6, opcode, 2);
-}
-
-static inline const void *arp_mac6_get_target_mac(const void *data)
-{
- return data + 18;
-}
-
-static inline const void *arp_mac20_get_sender_qpn(void *data)
-{
- return ((__u8 *) data) + 13;
-}
-
-static inline const void *arp_mac20_get_sender_gid(void *data)
-{
- return ((__u8 *) data) + 16;
-}
-
-static inline const void *arp_mac20_get_target_qpn(void *data)
-{
- return ((__u8 *) data) + 37;
-}
-
-static inline const void *arp_mac20_get_target_gid(void *data)
-{
- return ((__u8 *) data) + 40;
-}
-
-static inline const void *get_lptr_by_off(const void *packet, __u16 offset)
-{
- return packet + offset;
-}
-
-static inline __u8 get_ip_protocl_type(const void *packet)
-{
- const void *ptr;
- __u8 prot;
-
- ptr = get_lptr_by_off(packet, 9);
-
- memcpy(&prot, ptr, 1);
- return prot;
-}
-
-static inline __u16 get_udp_dest_port(const void *packet)
-{
- const void *ptr;
- __u16 port;
-
- ptr = get_lptr_by_off(packet, 22);
-
- memcpy(&port, ptr, 2);
- return port;
-}
-
-static inline __u8 get_dhcp_message_type(const void *packet)
-{
- const void *ptr;
- __u8 type;
-
- ptr = get_lptr_by_off(packet, 28);
-
- memcpy(&type, ptr, 1);
- return type;
-}
-
-static inline void set_hw_type(__u8 * packet)
-{
- packet[29] = IPOIB_HW_TYPE;
-}
-
-static inline void zero_hw_len(__u8 * packet)
-{
- packet[30] = 0;
-}
-
-static inline void set_udp_csum(__u8 * packet, __u16 val)
-{
- __u16 *csum_ptr;
-
- csum_ptr = (__u16 *) (packet + 26);
-
- *csum_ptr = htons(val);
-}
-
-static inline void zero_chaddr(__u8 * packet)
-{
- memset(packet + 56, 0, 16);
-}
-
-static inline void set_bcast_flag(__u8 * packet)
-{
- packet[38] = 0x80;
-}
-
-static inline __u8 get_ip_protocl(void *buf)
-{
- return ((__u8 *) buf)[9];
-}
-
-static inline __u16 get_udp_dst_port(void *buf)
-{
- return be16_to_cpu(*((__u16 *) (((__u8 *) buf) + 0x16)));
-}
-
-static inline __u8 get_dhcp_msg_type(void *buf)
-{
- return ((__u8 *) buf)[0x1c];
-}
-
-static inline void set_eth_hwtype(void *buf)
-{
- ((__u8 *) buf)[0x1d] = ETH_HW_TYPE;
-}
-
-static inline void set_eth_hwlen(void *buf)
-{
- ((__u8 *) buf)[0x1e] = 6;
-}
-
-static inline void add_udp_len(void *buf, __u16 size_add)
-{
- __u16 old_len, *len_ptr;
-
- len_ptr = (__u16 *) (((__u8 *) buf) + 24);
- old_len = ntohs(*len_ptr);
- *len_ptr = htons(old_len + size_add);
-}
-
-static inline void set_own_mac(void *buf)
-{
- ((__u8 *) buf)[0x38] = 0xff; //MLX_ETH_BYTE0;
- ((__u8 *) buf)[0x39] = 0xff; //MLX_ETH_BYTE1;
- ((__u8 *) buf)[0x3a] = 0xff; //MLX_ETH_BYTE2;
- ((__u8 *) buf)[0x3b] = 0xff; //0;
- ((__u8 *) buf)[0x3c] = 0xff; //0;
- ((__u8 *) buf)[0x3d] = 0xff; //0;
-}
-
-static int ipoib_handle_rcv(void *buf, void **out_buf_p,
- unsigned int *new_size_p, int *bcast_p);
-static int ipoib_send_packet(const __u8 * mac, __u16 protocol, const void *data,
- unsigned int size);
-static int ipoib_init(struct pci_device *pci);
-static u8 *get_port_gid(void);
-static int ipoib_read_packet(__u16 * prot_p, void *data, unsigned int *size_p,
- int *is_bcast_p);
-
-#endif /* __ipoib_h__ */
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-
-#ifndef __mad_attrib_h_
-#define __mad_attrib_h_
-
-#include "ib_mad.h"
-
-#define IB_SA_ATTR_MC_MEMBER_REC 0x38
-#define IB_SA_ATTR_PATH_REC 0x35
-
-#define IB_SA_MCMEMBER_REC_MGID (1<<0)
-#define IB_SA_MCMEMBER_REC_PORT_GID (1<<1)
-#define IB_SA_MCMEMBER_REC_QKEY (1<<2)
-#define IB_SA_MCMEMBER_REC_MLID (1<<3)
-#define IB_SA_MCMEMBER_REC_MTU_SELECTOR (1<<4)
-#define IB_SA_MCMEMBER_REC_MTU (1<<5)
-#define IB_SA_MCMEMBER_REC_TRAFFIC_CLASS (1<<6)
-#define IB_SA_MCMEMBER_REC_PKEY (1<<7)
-#define IB_SA_MCMEMBER_REC_RATE_SELECTOR (1<<8)
-#define IB_SA_MCMEMBER_REC_RATE (1<<9)
-#define IB_SA_MCMEMBER_REC_PACKET_LIFE_TIME_SELECTOR (1<<10)
-#define IB_SA_MCMEMBER_REC_PACKET_LIFE_TIME (1<<11)
-#define IB_SA_MCMEMBER_REC_SL (1<<12)
-#define IB_SA_MCMEMBER_REC_FLOW_LABEL (1<<13)
-#define IB_SA_MCMEMBER_REC_HOP_LIMIT (1<<14)
-#define IB_SA_MCMEMBER_REC_SCOPE (1<<15)
-#define IB_SA_MCMEMBER_REC_JOIN_STATE (1<<16)
-#define IB_SA_MCMEMBER_REC_PROXY_JOIN (1<<17)
-
-#define IB_SA_PATH_REC_DGID (1<<2)
-#define IB_SA_PATH_REC_SGID (1<<3)
-
-struct port_info_st {
- __u32 mkey[2];
- __u32 gid_prefix[2];
- __u16 mastersm_lid;
- __u16 lid;
- __u32 cap_mask;
- __u32 combined2;
- /*__u32 mkey_lease_period:16;
- __u32 diag_code:16;*/
- __u32 combined3;
- /*__u32 link_width_active:8;
- __u32 link_width_supported:8;
- __u32 link_width_enabled:8;
- __u32 local_port_num:8;*/
- __u32 combined4;
- /*__u32 link_speed_enabled:4;
- __u32 link_speed_active:4;
- __u32 lmc:3;
- __u32 r1:3;
- __u32 mkey_prot_bits:2;
- __u32 link_down_def_state:4;
- __u32 port_phys_state:4;
- __u32 port_state:4;
- __u32 link_speed_supported:4;*/
- __u32 combined5;
- /*__u32 vl_arb_hi_cap:8;
- __u32 vl_hi_limit:8;
- __u32 init_type:4;
- __u32 vl_cap:4;
- __u32 master_smsl:4;
- __u32 neigh_mtu:4;*/
- __u32 combined6;
- /*__u32 filt_raw_oub:1;
- __u32 filt_raw_inb:1;
- __u32 part_enf_oub:1;
- __u32 part_enf_inb:1;
- __u32 op_vls:4;
- __u32 hoq_life:5;
- __u32 vl_stall_count:3;
- __u32 mtu_cap:4;
- __u32 init_type_reply:4;
- __u32 vl_arb_lo_cap:8;*/
- __u32 combined7;
- /*__u32 pkey_viol:16;
- __u32 mkey_viol:16;*/
- __u32 combined8;
- /*__u32 subn_tout:5;
- __u32 r2:2;
- __u32 client_rereg:1;
- __u32 guid_cap:8;
- __u32 qkey_viol:16;*/
- __u32 combined9;
- /*__u32 max_cred_hint:16;
- __u32 overrun_err:4;
- __u32 local_phy_err:4;
- __u32 resp_t_val:5;
- __u32 r3:3;*/
- __u32 combined10;
- /*__u32 r4:8;
- __u32 link_rtrip_lat:24;*/
-} __attribute__ ((packed));
-
-struct port_info_mad_st {
- struct ib_mad_hdr_st mad_hdr;
- __u32 mkey[2];
- __u32 r1[8];
- struct port_info_st port_info;
-} __attribute__ ((packed));
-
-union port_info_mad_u {
- __u8 raw[256];
- struct port_info_mad_st mad;
-} __attribute__ ((packed));
-
-struct guid_info_st {
- union ib_gid_u gid_tbl[8];
-} __attribute__ ((packed));
-
-struct guid_info_mad_st {
- struct ib_mad_hdr_st mad_hdr;
- __u32 mkey[2];
- __u32 r1[8];
- struct guid_info_st guid_info;
-} __attribute__ ((packed));
-
-union guid_info_mad_u {
- __u8 raw[256];
- struct guid_info_mad_st mad;
-} __attribute__ ((packed));
-
-struct mc_member_st {
- __u8 mgid[16];
- __u8 port_gid[16];
- __u32 q_key;
- __u32 combined1;
- /*__u32 tclass:8;
- __u32 mtu:6;
- __u32 mtu_selector:2;
- __u32 mlid:16;*/
- __u32 combined2;
- /*__u32 packet_liftime:6;
- __u32 packet_liftime_selector:2;
- __u32 rate:6;
- __u32 rate_selector:2;
- __u32 pkey:16;*/
- __u32 combined3;
- /*__u32 hop_limit:8;
- __u32 flow_label:20;
- __u32 sl:4;*/
- __u32 combined4;
- /*__u32 r0:23;
- __u32 proxy_join:1;
- __u32 join_state:4;
- __u32 scope:4;*/
-} __attribute__ ((packed));
-
-struct mc_member_mad_st {
- struct ib_mad_hdr_st mad_hdr;
- struct rmpp_hdr_st rmpp_hdr;
- struct sa_header_st sa_hdr;
- struct mc_member_st mc_member;
-} __attribute__ ((packed));
-
-union mc_member_mad_u {
- struct mc_member_mad_st mc_member;
- __u8 raw[256];
-} __attribute__ ((packed));
-
-struct pkey_tbl_st {
- __u16 pkey_tbl[16][2];
-} __attribute__ ((packed));
-
-struct pkey_tbl_mad_st {
- struct ib_mad_hdr_st mad_hdr;
- __u32 mkey[2];
- __u32 r1[8];
- struct pkey_tbl_st pkey_tbl;
-} __attribute__ ((packed));
-
-union pkey_tbl_mad_u {
- struct pkey_tbl_mad_st mad;
- __u8 raw[256];
-} __attribute__ ((packed));
-
-struct path_record_st {
- __u32 r0[2];
- union ib_gid_u dgid;
- union ib_gid_u sgid;
- __u16 slid;
- __u16 dlid;
- __u32 combined1;
- /*__u32 hop_limit:8;
- __u32 flow_label:20;
- __u32 r1:3;
- __u32 raw_traffic:1;*/
- __u32 combined2;
- /*__u32 pkey:16;
- __u32 numb_path:7;
- __u32 reversible:1;
- __u32 tclass:8;*/
- __u32 combined3;
- /*__u32 rate:6;
- __u32 rate_selector:2;
- __u32 mtu:6;
- __u32 mtu_selector:2;
- __u32 sl:4;
- __u32 reserved:12;*/
- __u32 combined4;
- /*__u32 r2:16;
- __u32 preference:8;
- __u32 packet_lifetime:6;
- __u32 packet_lifetime_selector:2;*/
- __u32 r3;
-} __attribute__ ((packed));
-
-struct path_record_mad_st {
- struct ib_mad_hdr_st mad_hdr;
- struct rmpp_hdr_st rmpp_hdr;
- struct sa_header_st sa_hdr;
- struct path_record_st path_record;
-} __attribute__ ((packed));
-
-union path_record_mad_u {
- struct path_record_mad_st mad;
- __u8 raw[256];
-} __attribute__ ((packed));
-
-static int get_port_info(__u8 port, struct port_info_st *buf, __u16 * status);
-static int get_guid_info(__u16 * status);
-static int get_pkey_tbl(struct pkey_tbl_st *pkey_tbl, __u16 * status);
-static int join_mc_group(__u32 * qkey_p, __u16 * mlid_p, __u8 join);
-
-#endif /* __mad_attrib_h_ */
+++ /dev/null
-/**************************************************************************
-Etherboot - BOOTP/TFTP Bootstrap Program
-Skeleton NIC driver for Etherboot
-***************************************************************************/
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2, or (at
- * your option) any later version.
- */
-
-/* to get toupper() */
-#include <ctype.h>
-/* to get some global routines like printf */
-#include "etherboot.h"
-/* to get the interface to the body of the program */
-#include "nic.h"
-/* to get the PCI support functions, if this is a PCI NIC */
-#include <gpxe/pci.h>
-/* to get the ISA support functions, if this is an ISA NIC */
-#include <gpxe/isa.h>
-
-#include "mt_version.c"
-#include "mt23108_imp.c"
-
-/* NIC specific static variables go here */
-
-int prompt_key(int secs, unsigned char *ch_p)
-{
- unsigned long tmo;
- unsigned char ch;
-
- for (tmo = currticks() + secs * TICKS_PER_SEC; currticks() < tmo;) {
- if (iskey()) {
- ch = toupper(getchar());
- if ((ch=='V') || (ch=='I')) {
- *ch_p = ch;
- return 1;
- }
- }
- }
-
- return 0;
-}
-
-/**************************************************************************
-IRQ - handle interrupts
-***************************************************************************/
-static void tavor_irq(struct nic *nic, irq_action_t action)
-{
- /* This routine is somewhat optional. Etherboot itself
- * doesn't use interrupts, but they are required under some
- * circumstances when we're acting as a PXE stack.
- *
- * If you don't implement this routine, the only effect will
- * be that your driver cannot be used via Etherboot's UNDI
- * API. This won't affect programs that use only the UDP
- * portion of the PXE API, such as pxelinux.
- */
-
- if (0) {
- nic = NULL;
- }
- switch (action) {
- case DISABLE:
- case ENABLE:
- /* Set receive interrupt enabled/disabled state */
- /*
- outb ( action == ENABLE ? IntrMaskEnabled : IntrMaskDisabled,
- nic->ioaddr + IntrMaskRegister );
- */
- break;
- case FORCE:
- /* Force NIC to generate a receive interrupt */
- /*
- outb ( ForceInterrupt, nic->ioaddr + IntrForceRegister );
- */
- break;
- }
-}
-
-/**************************************************************************
-POLL - Wait for a frame
-***************************************************************************/
-static int tavor_poll(struct nic *nic, int retrieve)
-{
- /* Work out whether or not there's an ethernet packet ready to
- * read. Return 0 if not.
- */
- /*
- if ( ! <packet_ready> ) return 0;
- */
-
- /* retrieve==0 indicates that we are just checking for the
- * presence of a packet but don't want to read it just yet.
- */
- /*
- if ( ! retrieve ) return 1;
- */
-
- /* Copy data to nic->packet. Data should include the
- * link-layer header (dest MAC, source MAC, type).
- * Store length of data in nic->packetlen.
- * Return true to indicate a packet has been read.
- */
- /*
- nic->packetlen = <packet_length>;
- memcpy ( nic->packet, <packet_data>, <packet_length> );
- return 1;
- */
- unsigned int size;
- int rc;
- rc = poll_imp(nic, retrieve, &size);
- if (rc) {
- return 0;
- }
-
- if (size == 0) {
- return 0;
- }
-
- nic->packetlen = size;
-
- return 1;
-}
-
-/**************************************************************************
-TRANSMIT - Transmit a frame
-***************************************************************************/
-static void tavor_transmit(struct nic *nic, const char *dest, /* Destination */
- unsigned int type, /* Type */
- unsigned int size, /* size */
- const char *packet)
-{ /* Packet */
- int rc;
-
- /* Transmit packet to dest MAC address. You will need to
- * construct the link-layer header (dest MAC, source MAC,
- * type).
- */
- if (nic) {
- rc = transmit_imp(dest, type, packet, size);
- if (rc)
- eprintf("tranmit error");
- }
-}
-
-/**************************************************************************
-DISABLE - Turn off ethernet interface
-***************************************************************************/
-static void tavor_disable(struct dev *dev)
-{
- /* put the card in its initial state */
- /* This function serves 3 purposes.
- * This disables DMA and interrupts so we don't receive
- * unexpected packets or interrupts from the card after
- * etherboot has finished.
- * This frees resources so etherboot may use
- * this driver on another interface
- * This allows etherboot to reinitialize the interface
- * if something is something goes wrong.
- */
- if (dev || 1) { // ????
- disable_imp();
- }
-}
-
-/**************************************************************************
-PROBE - Look for an adapter, this routine's visible to the outside
-***************************************************************************/
-
-static int tavor_probe(struct dev *dev, struct pci_device *pci)
-{
- struct nic *nic = (struct nic *)dev;
- int rc;
- unsigned char user_request;
-
- if (pci->vendor != MELLANOX_VENDOR_ID) {
- eprintf("");
- return 0;
- }
-
- printf("\n");
- printf("Mellanox Technologies LTD - Boot over IB implementaion\n");
- printf("Build version = %s\n\n", build_revision);
-
- verbose_messages = 0;
- print_info = 0;
- printf("Press within 3 seconds:\n");
- printf("V - to increase verbosity\n");
- printf("I - to print information\n");
- if (prompt_key(3, &user_request)) {
- if (user_request == 'V') {
- printf("User selected verbose messages\n");
- verbose_messages = 1;
- }
- else if (user_request == 'I') {
- printf("User selected to print information\n");
- print_info = 1;
- }
- }
- printf("\n");
-
- adjust_pci_device(pci);
-
- nic->priv_data = NULL;
- rc = probe_imp(pci, nic);
-
- /* give the user a chance to look at the info */
- if (print_info)
- sleep(5);
-
- if (!rc) {
- /* store NIC parameters */
- nic->ioaddr = pci->ioaddr & ~3;
- nic->irqno = pci->irq;
- /* point to NIC specific routines */
- dev->disable = tavor_disable;
- nic->poll = tavor_poll;
- nic->transmit = tavor_transmit;
- nic->irq = tavor_irq;
-
- return 1;
- }
- /* else */
- return 0;
-}
-
-static struct pci_id tavor_nics[] = {
- PCI_ROM(0x15b3, 0x5a44, "MT23108", "MT23108 HCA driver"),
- PCI_ROM(0x15b3, 0x6278, "MT25208", "MT25208 HCA driver"),
-};
-
-struct pci_driver tavor_driver __pci_driver = {
- .type = NIC_DRIVER,
- .name = "MT23108/MT25208",
- .probe = tavor_probe,
- .ids = tavor_nics,
- .id_count = sizeof(tavor_nics) / sizeof(tavor_nics[0]),
- .class = 0,
-};
+++ /dev/null
-#ifndef __mt23108_h__
-#define __mt23108_h__
-
-#include "MT23108_PRM.h"
-#include "ib_mad.h"
-
-#define TAVOR_DEVICE_ID 0x5a44
-#define TAVOR_BRIDGE_DEVICE_ID 0x5a46
-#define ARTAVOR_DEVICE_ID 0x6278
-
-#define TAVOR_RESET_OFFSET 0xF0010
-
-/*
- * Tavor specific command
- * Only coomands that are specific to Tavor
- * and used by the driver are listed here
- */
-#define TAVOR_CMD_SYS_EN 0x1
-#define TAVOR_CMD_SYS_DIS 0x2
-
-#define TAVOR_CMD_WRITE_MGM 0x26
-#define TAVOR_CMD_MOD_STAT_CFG 0x34
-#define TAVOR_CMD_QUERY_DEV_LIM 0x003
-#define TAVOR_CMD_QUERY_FW 0x004
-
-/*
- * Tavor specific event types
- * Only event types that are specific to Tavor
- * and are used by the driver are listed here
- */
-#define TAVOR_IF_EV_TYPE_OVERRUN 0x0F
-
-/*
- * EQ doorbel commands
- */
-#define EQ_DBELL_CMD_INC_CONS_IDX 1 /* increment Consumer_indx by one */
-#define EQ_DBELL_CMD_ARM_EQ 2 /* Request notifcation for next event (Arm EQ) */
-#define EQ_DBELL_CMD_DISARM_CQ 3 /* Disarm CQ (CQ number is specified in EQ_param) */
-#define EQ_DBELL_CMD_SET_CONS_IDX 4 /* set Consumer_indx to value of EQ_param */
-#define EQ_DBELL_CMD_ALWAYS_ARM 5 /* move EQ to Always Armed state */
-
-/*
- * CQ doorbel commands
- */
-#define CQ_DBELL_CMD_INC_CONS_IDX 1
-#define CQ_DBELL_CMD_REQ_NOTIF_SOL_UNSOL 2
-#define CQ_DBELL_CMD_REQ_NOTIF_SOL 3
-#define CQ_DBELL_CMD_SET_CONS_IDX 4
-#define CQ_DBELL_CMD_REQ_NOTIF_MULT 5
-
-#define INPRM_BUF_SZ 0x200
-#define INPRM_BUF_ALIGN 16
-#define OUTPRM_BUF_SZ 0x200
-#define OUTPRM_BUF_ALIGN 16
-
-/*
- * sizes of parameter blocks used in certain
- * commands.
- * TODO: replace them with sizeof
- * operators of the appropriate structs
- */
-#define SW2HW_MPT_IBUF_SZ MT_STRUCT_SIZE(tavorprm_mpt_st)
-#define SW2HW_EQ_IBUF_SZ MT_STRUCT_SIZE(tavorprm_eqc_st)
-#define INIT_IB_IBUF_SZ 0x100
-#define SW2HW_CQ_IBUF_SZ 0x40
-#define QPCTX_IBUF_SZ 0x200
-
-#define EQN 0
-#define UAR_IDX 1
-
-#define QPC_OFFSET 0
-#define CQC_OFFSET (QPC_OFFSET + 0x100000)
-#define EQPC_OFFSET (CQC_OFFSET + 0x100000)
-#define EQC_OFFSET (EQPC_OFFSET + 0x100000)
-#define MC_BASE_OFFSET (EQC_OFFSET + 0x100000)
-#define MPT_BASE_OFFSET (MC_BASE_OFFSET + 0x100000)
-#define MTT_BASE_OFFSET (MPT_BASE_OFFSET + 0x100000)
-
-#define LOG2_QPS 7
-#define LOG2_CQS 8
-#define LOG2_EQS 6
-#define LOG2_MC_ENTRY 6 /* 8 QPs per group */
-#define LOG2_MC_GROUPS 3 /* 8 groups */
-#define LOG2_MPT_ENTRIES 5
-
-#define LOG2_EQ_SZ 5
-#define LOG2_CQ_SZ 5
-
-#define NUM_PORTS 2
-
-#define EQE_OWNER_SW 0
-#define EQE_OWNER_HW 1
-
-#define OWNER_HW 1
-#define OWNER_SW 0
-
-#define POST_RCV_OFFSET 0x18
-#define POST_SND_OFFSET 0x10
-#define CQ_DBELL_OFFSET 0x20
-#define EQ_DBELL_OFFSET 0x28
-
-#define CQE_ERROR_OPCODE 0xfe
-
-#define MAX_GATHER 1 /* max gather entries used in send */
-#define MAX_SCATTER 2
-
-#define LOG2_MADS_SND_CQ_SZ LOG2_CQ_SZ
-#define LOG2_MADS_RCV_CQ_SZ LOG2_CQ_SZ
-#define LOG2_IPOIB_SND_CQ_SZ LOG2_CQ_SZ
-#define LOG2_IPOIB_RCV_CQ_SZ LOG2_CQ_SZ
-
-#define NUM_MADS_SND_CQES (1<<LOG2_MADS_SND_CQ_SZ)
-#define NUM_MADS_RCV_CQES (1<<LOG2_MADS_RCV_CQ_SZ)
-#define NUM_IPOIB_SND_CQES (1<<LOG2_IPOIB_SND_CQ_SZ)
-#define NUM_IPOIB_RCV_CQES (1<<LOG2_IPOIB_RCV_CQ_SZ)
-
-#define NUM_MADS_RCV_WQES 3
-#define NUM_IPOIB_RCV_WQES 8
-
-#if NUM_MADS_RCV_WQES > NUM_IPOIB_RCV_WQES
-#define MAX_RCV_WQES NUM_MADS_RCV_WQES
-#else
-#define MAX_RCV_WQES NUM_IPOIB_RCV_WQES
-#endif
-
-#define NUM_MADS_SND_WQES 2
-#define NUM_IPOIB_SND_WQES 2
-
-#if NUM_MADS_SND_WQES > NUM_IPOIB_SND_WQES
-#define MAX_SND_WQES NUM_MADS_SND_WQES
-#else
-#define MAX_SND_WQES NUM_IPOIB_SND_WQES
-#endif
-
-struct ib_buffers_st {
- __u8 send_mad_buf[NUM_MADS_SND_WQES][MAD_BUF_SZ];
- __u8 rcv_mad_buf[NUM_MADS_RCV_WQES][MAD_BUF_SZ + GRH_SIZE];
- __u8 ipoib_rcv_buf[NUM_IPOIB_RCV_WQES][IPOIB_RCV_BUF_SZ + GRH_SIZE];
- __u8 ipoib_rcv_grh_buf[NUM_IPOIB_RCV_WQES][IPOIB_RCV_BUF_SZ];
- __u8 send_ipoib_buf[NUM_IPOIB_SND_WQES][IPOIB_SND_BUF_SZ];
-};
-
-struct pcidev {
- unsigned long bar[6];
- __u32 dev_config_space[64];
- struct pci_device *dev;
- __u8 bus;
- __u8 devfn;
-};
-
-struct dev_pci_struct {
- struct pcidev dev;
- struct pcidev br;
- void *cr_space;
- void *uar;
-};
-
-struct eq_st {
- __u8 eqn;
- __u32 cons_idx;
- __u32 eq_size;
- struct eqe_t *eq_buf;
-};
-
-struct udav_st {
- union ud_av_u *av_array;
- __u8 udav_next_free;
-};
-
-#if 0
-struct udavtable_memory_parameters_st {
- __u32 lkey;
- __u32 pd:24;
- __u32 r0:5;
- __u32 xlation_en:1;
- __u32 r1:2;
-} __attribute__ ((packed));
-
-struct multicast_parameters_st {
- __u32 mc_base_addr_h;
- __u32 mc_base_addr_l;
- __u32 r0[2];
- __u32 log_mc_table_entry_sz:16;
- __u32 r1:16;
- __u32 mc_table_hash_sz:17;
- __u32 r2:15;
- __u32 log_mc_table_sz:5;
- __u32 r3:19;
- __u32 mc_hash_fn:3;
- __u32 r4:5;
- __u32 r5;
-} __attribute__ ((packed));
-
-struct tpt_parameters_st {
- __u32 mpt_base_addr_h;
- __u32 mpt_base_addr_l;
-
- __u32 log_mpt_sz:6;
- __u32 r0:2;
- __u32 pfto:5;
- __u32 r1:3;
- __u32 mtt_segment_size:3;
- __u32 r2:13;
-
- __u32 mtt_version:8;
- __u32 r3:24;
-
- __u32 mtt_base_addr_h;
- __u32 mtt_base_addr_l;
- __u32 r4[2];
-} __attribute__ ((packed));
-
-struct uar_parameters_st {
- __u32 uar_base_addr_h;
- __u32 uar_base_addr_l; /* 12 lsbs must be zero */
- __u32 uar_page_sz:8;
- __u32 r1:24;
- __u32 r2;
- __u32 uar_scratch_base_addr_h;
- __u32 uar_scratch_base_addr_l;
- __u32 r3[3];
-} __attribute__ ((packed));
-
-struct comp_event_data_st {
- __u32 cqn:24;
- __u32 r1:8;
- __u32 r2[5];
-} __attribute__ ((packed));
-
-struct qp_event_data_st {
- __u32 qpn_een:24;
- __u32 r1:8;
- __u32 r2;
- __u32 r3:28;
- __u32 e_q:1;
- __u32 r4:3;
- __u32 r5[3];
-} __attribute__ ((packed));
-
-struct port_state_change_event_data_st {
- __u32 r0[2];
- __u32 r1:28;
- __u32 port:2;
- __u32 r2:2;
- __u32 r3[3];
-} __attribute__ ((packed));
-#endif
-
-struct eqe_t {
- __u8 raw[MT_STRUCT_SIZE(tavorprm_event_queue_entry_st)];
-} __attribute__ ((packed));
-
-enum qp_state_e {
- QP_STATE_RST = 0,
- QP_STATE_INIT = 1,
- QP_STATE_RTR = 2,
- QP_STATE_RTS = 3,
- QP_STATE_SQEr = 4,
- QP_STATE_SQD = 5,
- QP_STATE_ERR = 6,
- QP_STATE_SQDING = 7,
- QP_STATE_SUSPEND = 9
-};
-
-struct memory_pointer_st {
- __u32 byte_count;
- __u32 lkey;
- __u32 local_addr_h;
- __u32 local_addr_l;
-} __attribute__ ((packed));
-
-/* receive wqe descriptor */
-struct recv_wqe_st {
- /* part referenced by hardware */
- __u8 next[MT_STRUCT_SIZE(wqe_segment_next_st)];
- __u8 control[MT_STRUCT_SIZE(wqe_segment_ctrl_recv_st)];
- struct memory_pointer_st mpointer[MAX_SCATTER];
-} __attribute__ ((packed));
-
-struct recv_wqe_cont_st {
- struct recv_wqe_st wqe;
-
- struct udqp_st *qp; /* qp this wqe is used with */
-} __attribute__ ((packed));
-
-#define RECV_WQE_U_ALIGN 64
-union recv_wqe_u {
- __u8 align[(sizeof(struct recv_wqe_cont_st) + RECV_WQE_U_ALIGN - 1) & (~(RECV_WQE_U_ALIGN - 1))]; /* this ensures proper alignment */
- struct recv_wqe_st wqe;
- struct recv_wqe_cont_st wqe_cont;
-} __attribute__ ((packed));
-
-struct recv_doorbell_st {
- __u8 raw[MT_STRUCT_SIZE(tavorprm_receive_doorbell_st)];
-} __attribute__ ((packed));
-
-struct send_doorbell_st {
- __u8 raw[MT_STRUCT_SIZE(tavorprm_send_doorbell_st)];
-} __attribute__ ((packed));
-
-struct next_control_seg_st {
- __u8 next[MT_STRUCT_SIZE(wqe_segment_next_st)];
- __u8 control[MT_STRUCT_SIZE(wqe_segment_ctrl_send_st)];
-} __attribute__ ((packed));
-
-struct ud_seg_st {
- __u32 r1;
- __u32 lkey;
- __u32 av_add_h;
- __u32 av_add_l;
- __u32 r2[4];
- __u32 dest_qp;
- __u32 qkey;
- __u32 r3[2];
-} __attribute__ ((packed));
-
-struct ud_send_wqe_st {
- struct next_control_seg_st next;
- struct ud_seg_st udseg;
- struct memory_pointer_st mpointer[MAX_GATHER];
-} __attribute__ ((packed));
-
-struct ude_send_wqe_cont_st {
- struct ud_send_wqe_st wqe;
-
- struct udqp_st *qp; /* qp this wqe is used with */
-} __attribute__ ((packed));
-
-#define UD_SEND_WQE_U_ALIGN 64
-union ud_send_wqe_u {
- __u8 align[(sizeof(struct ude_send_wqe_cont_st) + UD_SEND_WQE_U_ALIGN -
- 1) & (~(UD_SEND_WQE_U_ALIGN - 1))];
- struct ude_send_wqe_cont_st wqe_cont;
- struct ud_send_wqe_st wqe;
-} __attribute__ ((packed));
-
-#define ADDRESS_VECTOR_ST_ALIGN 64
-struct address_vector_st {
- __u8 raw[MT_STRUCT_SIZE(tavorprm_ud_address_vector_st)];
-} __attribute__ ((packed));
-
-struct ud_av_st {
- struct address_vector_st av;
- __u32 dest_qp; /* destination qpn */
- __u8 next_free;
-} __attribute__ ((packed));
-
-union ud_av_u {
- __u8 raw[(sizeof(struct ud_av_st) + ADDRESS_VECTOR_ST_ALIGN -
- 1) & (~(ADDRESS_VECTOR_ST_ALIGN - 1))];
- struct ud_av_st ud_av;
-} __attribute__ ((packed));
-
-union cqe_st {
- __u8 good_cqe[MT_STRUCT_SIZE(tavorprm_completion_queue_entry_st)];
- __u8 error_cqe[MT_STRUCT_SIZE(tavorprm_completion_with_error_st)];
-} __attribute__ ((packed));
-
-struct address_path_st {
- __u8 raw[MT_STRUCT_SIZE(tavorprm_address_path_st)];
-};
-
-struct qp_ee_ctx_t {
- __u8 raw[MT_STRUCT_SIZE(tavorprm_queue_pair_ee_context_entry_st)];
-} __attribute__ ((packed));
-
-struct qp_ee_state_tarnisition_st {
- __u32 opt_param_mask;
- __u32 r1;
- struct qp_ee_ctx_t ctx;
- __u32 r2[62];
-} __attribute__ ((packed));
-
-struct eq_dbell_st {
- __u8 raw[MT_STRUCT_SIZE(tavorprm_eq_cmd_doorbell_st)];
-} __attribute__ ((packed));
-
-struct cq_dbell_st {
- __u8 raw[MT_STRUCT_SIZE(tavorprm_cq_cmd_doorbell_st)];
-} __attribute__ ((packed));
-
-struct mad_ifc_inprm_st {
- union mad_u mad;
-} __attribute__ ((packed));
-
-struct wqe_buf_st {
- struct ud_send_wqe_st *sndq;
- struct recv_wqe_st *rcvq;
-};
-
-struct mad_buffer_st {
- void *buf; /* pointer to a 256 byte buffer */
- __u8 owner; /* sw or hw ownership BUF_OWNER_SW or BUF_OWNER_HW */
-};
-
-struct rcv_buf_st {
- void *buf;
- __u8 busy;
-};
-
-struct ib_eqe_st {
- __u8 event_type;
- __u32 cqn;
-};
-
-struct cq_st {
- __u32 cqn;
- union cqe_st *cq_buf;
- __u32 cons_idx;
- __u8 num_cqes;
-};
-
-struct udqp_st {
- /* cq used by this QP */
- struct cq_st snd_cq;
- struct cq_st rcv_cq;
-
- /* QP related data */
- __u32 qpn; /* QP number */
-
- __u32 qkey;
-
- __u8 recv_wqe_cur_free;
- __u8 recv_wqe_alloc_idx;
- __u8 max_recv_wqes;
- void *rcv_bufs[MAX_RCV_WQES];
- union recv_wqe_u *rcv_wq; /* receive work queue */
- struct recv_wqe_st *last_posted_rcv_wqe;
-
- __u8 snd_wqe_cur_free;
- __u8 snd_wqe_alloc_idx;
- __u8 max_snd_wqes;
- void *snd_bufs[MAX_SND_WQES];
- __u16 send_buf_sz;
- __u16 rcv_buf_sz;
- union ud_send_wqe_u *snd_wq; /* send work queue */
- struct ud_send_wqe_st *last_posted_snd_wqe;
-};
-
-struct device_ib_data_st {
- __u32 mkey;
- __u32 pd;
- __u8 port;
- __u32 qkey;
- struct eq_st eq;
- struct udav_st udav;
- struct udqp_st mads_qp;
- struct udqp_st ipoib_qp;
- void *error_buf_addr;
- __u32 error_buf_size;
-};
-
-
-
-struct query_fw_st {
- __u16 fw_rev_major;
- __u16 fw_rev_minor;
- __u16 fw_rev_subminor;
- __u32 error_buf_start_h;
- __u32 error_buf_start_l;
- __u32 error_buf_size;
-};
-
-
-struct dev_lim_st {
- __u8 log2_rsvd_qps;
- __u16 qpc_entry_sz;
-
- __u8 log2_rsvd_srqs;
- __u16 srq_entry_sz;
-
- __u8 log2_rsvd_ees;
- __u16 eec_entry_sz;
-
- __u8 log2_rsvd_cqs;
- __u16 cqc_entry_sz;
-
- __u8 log2_rsvd_mtts;
- __u16 mtt_entry_sz;
-
- __u8 log2_rsvd_mrws;
- __u16 mpt_entry_sz;
-
- __u16 eqc_entry_sz;
-};
-
-struct init_hca_st {
- __u32 qpc_base_addr_h;
- __u32 qpc_base_addr_l;
- __u8 log_num_of_qp;
-
- __u32 eec_base_addr_h;
- __u32 eec_base_addr_l;
- __u8 log_num_of_ee;
-
- __u32 srqc_base_addr_h;
- __u32 srqc_base_addr_l;
- __u8 log_num_of_srq;
-
- __u32 cqc_base_addr_h;
- __u32 cqc_base_addr_l;
- __u8 log_num_of_cq;
-
- __u32 eqpc_base_addr_h;
- __u32 eqpc_base_addr_l;
-
- __u32 eeec_base_addr_h;
- __u32 eeec_base_addr_l;
-
- __u32 eqc_base_addr_h;
- __u32 eqc_base_addr_l;
- __u8 log_num_of_eq;
-
- __u32 rdb_base_addr_h;
- __u32 rdb_base_addr_l;
-
- __u32 mc_base_addr_h;
- __u32 mc_base_addr_l;
- __u16 log_mc_table_entry_sz;
- __u32 mc_table_hash_sz;
- __u8 log_mc_table_sz;
-
- __u32 mpt_base_addr_h;
- __u32 mpt_base_addr_l;
- __u8 log_mpt_sz;
- __u32 mtt_base_addr_h;
- __u32 mtt_base_addr_l;
- __u8 log_max_uars;
-};
-
-static int create_udqp(struct udqp_st *qp);
-static int destroy_udqp(struct udqp_st *qp);
-static void *get_send_wqe_buf(void *wqe, __u8 index);
-static void *get_rcv_wqe_buf(void *wqe, __u8 index);
-
-static struct recv_wqe_st *alloc_rcv_wqe(struct udqp_st *qp);
-static int free_wqe(void *wqe);
-static int poll_cq(void *cqh, union cqe_st *cqe_p, __u8 * num_cqes);
-static int poll_eq(struct ib_eqe_st *ib_eqe_p, __u8 * num_eqes);
-static int post_rcv_buf(struct udqp_st *qp, struct recv_wqe_st *rcv_wqe);
-static __u32 dev_get_qpn(void *qph);
-
-#endif /* __mt23108_h__ */
+++ /dev/null
-typedef uint32_t __u32;
-typedef uint16_t __u16;
-typedef uint8_t __u8;
-
-static int verbose_messages=0;
-static int print_info=0;
-static int fatal_condition=0;
-static int fw_fatal;
-
-#define tprintf(fmt, a...) \
- do { \
- if ( verbose_messages ) { \
- printf("%s:%d: " fmt "\n", __func__, __LINE__, ##a); \
- } \
- } \
- while(0)
-
-#define eprintf(fmt, a...) \
- printf("%s:%d: " fmt "\n", __func__, __LINE__, ##a)
-
-static void cpu_to_be_buf(void *buf, int size)
-{
- int dw_sz = size >> 2, i;
-
- for (i = 0; i < dw_sz; ++i) {
- ((__u32 *) buf)[i] = cpu_to_be32(((__u32 *) buf)[i]);
- }
-}
-
-static void be_to_cpu_buf(void *buf, int size)
-{
- int dw_sz = size >> 2, i;
- u32 *p = buf;
-
- for (i = 0; i < dw_sz; ++i) {
- p[i] = be32_to_cpu(p[i]);
- }
-}
-
-#include "cmdif_mt23108.c"
-#include "cmdif_comm.c"
-#include "ib_mt23108.c"
-#include "ib_mad.c"
-#include "ib_driver.c"
-#include "ipoib.c"
-
-static int probe_imp(struct pci_device *pci, struct nic *nic)
-{
- int rc;
-
- if (0 && nic) { /* just to supress warning */
- return 0;
- }
-
- fatal_condition= 0;
- fw_fatal= 0;
-
- tprintf("");
- rc = ipoib_init(pci);
- if (rc)
- return rc;
-
- tprintf("");
-
- return rc;
-}
-
-static int disable_imp(void)
-{
- int rc;
-
- rc = ipoib_close(fw_fatal);
-
- return rc;
-}
-
-static int transmit_imp(const char *dest, /* Destination */
- unsigned int type, /* Type */
- const char *packet, /* Packet */
- unsigned int size)
-{ /* size */
- int rc;
-
- if (fatal_condition) {
- /* since the transmit function does not return a value
- we return success but do nothing to suppress error messages */
- return 0;
- }
-
- rc = ipoib_send_packet(dest, type, packet, size);
- if (rc) {
- printf("*** ERROR IN SEND FLOW ***\n");
- printf("restarting Etherboot\n");
- sleep(1);
- longjmp(restart_etherboot, -1);
- /* we should not be here ... */
- return -1;
- }
-
- return rc;
-}
-
-static void hd(void *where, int n)
-{
- int i;
-
- while (n > 0) {
- printf("%X ", where);
- for (i = 0; i < ((n > 16) ? 16 : n); i++)
- printf(" %hhX", ((char *)where)[i]);
- printf("\n");
- n -= 16;
- where += 16;
- }
-}
-
-static int poll_imp(struct nic *nic, int retrieve, unsigned int *size_p)
-{
- static char packet[2048];
- static char *last_packet_p = NULL;
- static unsigned long last_packet_size;
- char *packet_p;
- const int eth_header_len = 14;
- unsigned int packet_len;
- int is_bcast = 0;
- __u16 prot, *ptr;
- int rc;
-
- if (0 && nic) { /* just to supress warning */
- return -1;
- }
-
- if (fatal_condition) {
- *size_p = 0;
- return 0;
- }
-
- if (poll_error_buf()) {
- fatal_condition= 1;
- fw_fatal= 1;
- printf("\n *** DEVICE FATAL ERROR ***\n");
- goto fatal_handling;
- }
- else if (drain_eq()) {
- fatal_condition= 1;
- printf("\n *** FATAL ERROR ***\n");
- goto fatal_handling;
- }
-
-
- if (retrieve) {
- /* we actually want to read the packet */
- if (last_packet_p) {
- eprintf("");
- /* there is already a packet that was previously read */
- memcpy(nic->packet, last_packet_p, last_packet_size);
- *size_p = last_packet_size;
- last_packet_p = NULL;
- return 0;
- }
- packet_p = nic->packet;
- } else {
- /* we don't want to read the packet,
- just know if there is one. so we
- read the packet to a local buffer and
- we will return that buffer when the ip layer wants
- another packet */
- if (last_packet_p) {
- /* there is already a packet that
- was not consumend */
- eprintf("overflow receive packets");
- return -1;
- }
- packet_p = packet;
- }
-
- rc = ipoib_read_packet(&prot, packet_p + eth_header_len, &packet_len,
- &is_bcast);
- if (rc) {
- printf("*** FATAL IN RECEIVE FLOW ****\n");
- goto fatal_handling;
- }
-
- if (packet_len == 0) {
- *size_p = 0;
- return 0;
- }
-
- if (is_bcast) {
- int i;
- for (i = 0; i < 6; ++i) {
- packet_p[i] = 0xff;
- }
- } else {
- packet_p[0] = MLX_ETH_BYTE0;
- packet_p[1] = MLX_ETH_BYTE1;
- packet_p[2] = MLX_ETH_BYTE2;
- packet_p[3] = 0;
- packet_p[4] = 0;
- packet_p[5] = 0;
- }
-
- memset(packet_p + 6, 0, 6);
-
- ptr = (__u16 *) (packet_p + 12);
- *ptr = htons(prot);
-
- if (!retrieve) {
- last_packet_p = packet;
- last_packet_size = packet_len + eth_header_len;
- *size_p = 0;
- }
-
- *size_p = packet_len + eth_header_len;
- tprintf("packet size=%d, prot=%x\n", *size_p, prot);
- if (0) {
- hd(nic->packet, 42);
- }
-
- return 0;
-
-fatal_handling:
- printf("restarting Etherboot\n");
- sleep(1);
- longjmp(restart_etherboot, -1);
- /* we should not be here ... */
- return -1;
-
-}
+++ /dev/null
-/**************************************************************************
-Etherboot - BOOTP/TFTP Bootstrap Program
-Skeleton NIC driver for Etherboot
-***************************************************************************/
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2, or (at
- * your option) any later version.
- */
-
-/* to get toupper() */
-#include <ctype.h>
-/* to get some global routines like printf */
-#include "etherboot.h"
-/* to get the interface to the body of the program */
-#include "nic.h"
-/* to get the PCI support functions, if this is a PCI NIC */
-#include <gpxe/pci.h>
-/* to get the ISA support functions, if this is an ISA NIC */
-#include <gpxe/isa.h>
-
-#include "mt_version.c"
-#include "mt25218_imp.c"
-
-/* NIC specific static variables go here */
-
-int prompt_key(int secs, unsigned char *ch_p)
-{
- unsigned long tmo;
- unsigned char ch;
-
- for (tmo = currticks() + secs * TICKS_PER_SEC; currticks() < tmo;) {
- if (iskey()) {
- ch = toupper(getchar());
- if ((ch=='V') || (ch=='I')) {
- *ch_p = ch;
- return 1;
- }
- }
- }
-
- return 0;
-}
-
-/**************************************************************************
-IRQ - handle interrupts
-***************************************************************************/
-static void mt25218_irq(struct nic *nic, irq_action_t action)
-{
- /* This routine is somewhat optional. Etherboot itself
- * doesn't use interrupts, but they are required under some
- * circumstances when we're acting as a PXE stack.
- *
- * If you don't implement this routine, the only effect will
- * be that your driver cannot be used via Etherboot's UNDI
- * API. This won't affect programs that use only the UDP
- * portion of the PXE API, such as pxelinux.
- */
-
- if (0) {
- nic = NULL;
- }
- switch (action) {
- case DISABLE:
- case ENABLE:
- /* Set receive interrupt enabled/disabled state */
- /*
- outb ( action == ENABLE ? IntrMaskEnabled : IntrMaskDisabled,
- nic->ioaddr + IntrMaskRegister );
- */
- break;
- case FORCE:
- /* Force NIC to generate a receive interrupt */
- /*
- outb ( ForceInterrupt, nic->ioaddr + IntrForceRegister );
- */
- break;
- }
-}
-
-/**************************************************************************
-POLL - Wait for a frame
-***************************************************************************/
-static int mt25218_poll(struct nic *nic, int retrieve)
-{
- /* Work out whether or not there's an ethernet packet ready to
- * read. Return 0 if not.
- */
- /*
- if ( ! <packet_ready> ) return 0;
- */
-
- /* retrieve==0 indicates that we are just checking for the
- * presence of a packet but don't want to read it just yet.
- */
- /*
- if ( ! retrieve ) return 1;
- */
-
- /* Copy data to nic->packet. Data should include the
- * link-layer header (dest MAC, source MAC, type).
- * Store length of data in nic->packetlen.
- * Return true to indicate a packet has been read.
- */
- /*
- nic->packetlen = <packet_length>;
- memcpy ( nic->packet, <packet_data>, <packet_length> );
- return 1;
- */
- unsigned int size;
- int rc;
- rc = poll_imp(nic, retrieve, &size);
- if (rc) {
- return 0;
- }
-
- if (size == 0) {
- return 0;
- }
-
- nic->packetlen = size;
-
- return 1;
-}
-
-/**************************************************************************
-TRANSMIT - Transmit a frame
-***************************************************************************/
-static void mt25218_transmit(struct nic *nic, const char *dest, /* Destination */
- unsigned int type, /* Type */
- unsigned int size, /* size */
- const char *packet)
-{ /* Packet */
- int rc;
-
- /* Transmit packet to dest MAC address. You will need to
- * construct the link-layer header (dest MAC, source MAC,
- * type).
- */
- if (nic) {
- rc = transmit_imp(dest, type, packet, size);
- if (rc)
- eprintf("tranmit error");
- }
-}
-
-/**************************************************************************
-DISABLE - Turn off ethernet interface
-***************************************************************************/
-static void mt25218_disable(struct dev *dev)
-{
- /* put the card in its initial state */
- /* This function serves 3 purposes.
- * This disables DMA and interrupts so we don't receive
- * unexpected packets or interrupts from the card after
- * etherboot has finished.
- * This frees resources so etherboot may use
- * this driver on another interface
- * This allows etherboot to reinitialize the interface
- * if something is something goes wrong.
- */
- if (dev || 1) { // ????
- disable_imp();
- }
-}
-
-/**************************************************************************
-PROBE - Look for an adapter, this routine's visible to the outside
-***************************************************************************/
-
-static int mt25218_probe(struct dev *dev, struct pci_device *pci)
-{
- struct nic *nic = (struct nic *)dev;
- int rc;
- unsigned char user_request;
-
- if (pci->vendor != MELLANOX_VENDOR_ID) {
- eprintf("");
- return 0;
- }
-
- printf("\n");
- printf("Mellanox Technologies LTD - Boot over IB implementaion\n");
- printf("Build version = %s\n\n", build_revision);
-
- verbose_messages = 0;
- print_info = 0;
- printf("Press within 3 seconds:\n");
- printf("V - to increase verbosity\n");
- printf("I - to print information\n");
- if (prompt_key(3, &user_request)) {
- if (user_request == 'V') {
- printf("User selected verbose messages\n");
- verbose_messages = 1;
- }
- else if (user_request == 'I') {
- printf("User selected to print information\n");
- print_info = 1;
- }
- }
- printf("\n");
-
- adjust_pci_device(pci);
-
- nic->priv_data = NULL;
- rc = probe_imp(pci, nic);
-
- /* give the user a chance to look at the info */
- if (print_info)
- sleep(5);
-
- if (!rc) {
- /* store NIC parameters */
- nic->ioaddr = pci->ioaddr & ~3;
- nic->irqno = pci->irq;
- /* point to NIC specific routines */
- dev->disable = mt25218_disable;
- nic->poll = mt25218_poll;
- nic->transmit = mt25218_transmit;
- nic->irq = mt25218_irq;
-
- return 1;
- }
- /* else */
- return 0;
-}
-
-static struct pci_id mt25218_nics[] = {
- PCI_ROM(0x15b3, 0x6282, "MT25218", "MT25218 HCA driver"),
- PCI_ROM(0x15b3, 0x6274, "MT25204", "MT25204 HCA driver"),
-};
-
-struct pci_driver mt25218_driver __pci_driver = {
- .type = NIC_DRIVER,
- .name = "MT25218",
- .probe = mt25218_probe,
- .ids = mt25218_nics,
- .id_count = sizeof(mt25218_nics) / sizeof(mt25218_nics[0]),
- .class = 0,
-};
+++ /dev/null
-#ifndef __mt25218_h__
-#define __mt25218_h__
-
-#include "MT25218_PRM.h"
-#include "ib_mad.h"
-
-#define TAVOR_DEVICE_ID 0x5a44
-#define TAVOR_BRIDGE_DEVICE_ID 0x5a46
-#define ARTAVOR_DEVICE_ID 0x6278
-
-#define MEMFREE_RESET_OFFSET 0xF0010
-
-#define INVALID_WQE_LKEY 0x00000100
-
-/*
- * memfree specific command
- *
- */
-#define MEMFREE_CMD_QUERY_ADAPTER 0x006
-#define MEMFREE_CMD_WRITE_MGM 0x026
-#define MEMFREE_CMD_MOD_STAT_CFG 0x034
-#define MEMFREE_CMD_QUERY_FW 0x004
-#define MEMFREE_CMD_ENABLE_LAM 0xff8
-#define MEMFREE_CMD_MAP_FA 0xfff
-#define MEMFREE_CMD_UNMAP_FA 0xffe
-#define MEMFREE_CMD_RUN_FW 0xff6
-#define MEMFREE_CMD_SET_ICM_SIZE 0xffd
-#define MEMFREE_CMD_MAP_ICM_AUX 0xffc
-#define MEMFREE_CMD_MAP_ICM 0xffa
-#define MEMFREE_CMD_QUERY_DEV_LIM 0x003
-
-/*
- * Tavor specific event types
- * Only event types that are specific to Tavor
- * and are used by the driver are listed here
- */
-#define TAVOR_IF_EV_TYPE_OVERRUN 0x0F
-
-/*
- * EQ doorbel commands
- */
-#define EQ_DBELL_CMD_INC_CONS_IDX 1 /* increment Consumer_indx by one */
-#define EQ_DBELL_CMD_ARM_EQ 2 /* Request notifcation for next event (Arm EQ) */
-#define EQ_DBELL_CMD_DISARM_CQ 3 /* Disarm CQ (CQ number is specified in EQ_param) */
-#define EQ_DBELL_CMD_SET_CONS_IDX 4 /* set Consumer_indx to value of EQ_param */
-#define EQ_DBELL_CMD_ALWAYS_ARM 5 /* move EQ to Always Armed state */
-
-/*
- * CQ doorbel commands
- */
-#define CQ_DBELL_CMD_INC_CONS_IDX 1
-#define CQ_DBELL_CMD_REQ_NOTIF_SOL_UNSOL 2
-#define CQ_DBELL_CMD_REQ_NOTIF_SOL 3
-#define CQ_DBELL_CMD_SET_CONS_IDX 4
-#define CQ_DBELL_CMD_REQ_NOTIF_MULT 5
-
-#define INPRM_BUF_SZ 4096
-#define INPRM_BUF_ALIGN 4096
-#define OUTPRM_BUF_SZ 4096
-#define OUTPRM_BUF_ALIGN 4096
-
-/*
- * sizes of parameter blocks used in certain
- * commands.
- * TODO: replace them with sizeof
- * operators of the appropriate structs
- */
-#define SW2HW_MPT_IBUF_SZ MT_STRUCT_SIZE(arbelprm_mpt_st)
-#define SW2HW_EQ_IBUF_SZ MT_STRUCT_SIZE(arbelprm_eqc_st)
-#define INIT_IB_IBUF_SZ MT_STRUCT_SIZE(arbelprm_init_ib_st)
-#define SW2HW_CQ_IBUF_SZ MT_STRUCT_SIZE(arbelprm_completion_queue_context_st)
-#define QPCTX_IBUF_SZ MT_STRUCT_SIZE(arbelprm_queue_pair_ee_context_entry_st)
-
-#define EQN 0
-#define UAR_IDX 1
-
-#define QPC_OFFSET 0
-#define CQC_OFFSET (QPC_OFFSET + 0x100000)
-#define EQPC_OFFSET (CQC_OFFSET + 0x100000)
-#define EQC_OFFSET (EQPC_OFFSET + 0x100000)
-#define MC_BASE_OFFSET (EQC_OFFSET + 0x100000)
-#define MPT_BASE_OFFSET (MC_BASE_OFFSET + 0x100000)
-#define MTT_BASE_OFFSET (MPT_BASE_OFFSET + 0x100000)
-
-#define LOG2_QPS 7
-#define LOG2_CQS 8
-#define LOG2_EQS 6
-#define LOG2_MC_ENTRY 6 /* 8 QPs per group */
-#define LOG2_MC_GROUPS 3 /* 8 groups */
-#define LOG2_MPT_ENTRIES 5
-
-#define LOG2_EQ_SZ 5
-#define LOG2_CQ_SZ 5
-
-#define NUM_PORTS 2
-
-#define EQE_OWNER_OFFSET 31
-#define EQE_OWNER_VAL_HW 0x80
-
-#define CQE_OWNER_OFFSET 31
-#define CQE_OWNER_VAL_HW 0x80
-
-#define POST_RCV_OFFSET 0x18
-#define POST_SND_OFFSET 0x10
-#define CQ_DBELL_OFFSET 0x20
-#define EQ_DBELL_OFFSET 0x28
-
-#define CQE_ERROR_OPCODE 0xfe
-
-#define OWNER_HW 1
-#define OWNER_SW 0
-
-#define MAX_GATHER 1 /* max gather entries used in send */
-#define MAX_SCATTER 2
-
-#define LOG2_MADS_SND_CQ_SZ LOG2_CQ_SZ
-#define LOG2_MADS_RCV_CQ_SZ LOG2_CQ_SZ
-#define LOG2_IPOIB_SND_CQ_SZ LOG2_CQ_SZ
-#define LOG2_IPOIB_RCV_CQ_SZ LOG2_CQ_SZ
-
-#define NUM_MADS_SND_CQES (1<<LOG2_MADS_SND_CQ_SZ)
-#define NUM_MADS_RCV_CQES (1<<LOG2_MADS_RCV_CQ_SZ)
-#define NUM_IPOIB_SND_CQES (1<<LOG2_IPOIB_SND_CQ_SZ)
-#define NUM_IPOIB_RCV_CQES (1<<LOG2_IPOIB_RCV_CQ_SZ)
-
-/* work queues must be 2^n size with n=0.. */
-#define NUM_MADS_RCV_WQES (1<<1)
-#define NUM_IPOIB_RCV_WQES (1<<1)
-
-#if NUM_MADS_RCV_WQES > NUM_IPOIB_RCV_WQES
-#define MAX_RCV_WQES NUM_MADS_RCV_WQES
-#else
-#define MAX_RCV_WQES NUM_IPOIB_RCV_WQES
-#endif
-
-#define NUM_MADS_SND_WQES (1<<1)
-#define NUM_IPOIB_SND_WQES (1<<1)
-
-#if NUM_MADS_SND_WQES > NUM_IPOIB_SND_WQES
-#define MAX_SND_WQES NUM_MADS_SND_WQES
-#else
-#define MAX_SND_WQES NUM_IPOIB_SND_WQES
-#endif
-
-/* uar context indexes */
-enum {
- MADS_RCV_CQ_ARM_DB_IDX,
- MADS_SND_CQ_ARM_DB_IDX,
- IPOIB_RCV_CQ_ARM_DB_IDX,
- IPOIB_SND_CQ_ARM_DB_IDX,
- MADS_SND_QP_DB_IDX,
- IPOIB_SND_QP_DB_IDX,
- GROUP_SEP_IDX,
- START_UNMAPPED_DB_IDX,
- /* --------------------------
- unmapped doorbell records
- -------------------------- */
- END_UNMAPPED_DB_IDX = 505,
- MADS_RCV_QP_DB_IDX = 506,
- IPOIB_RCV_QP_DB_IDX = 507,
- MADS_RCV_CQ_CI_DB_IDX = 508,
- MADS_SND_CQ_CI_DB_IDX = 509,
- IPOIB_RCV_CQ_CI_DB_IDX = 510,
- IPOIB_SND_CQ_CI_DB_IDX = 511
-};
-
-/* uar resources types */
-enum {
- UAR_RES_INVALID = 0x0, /* Invalid (not allocated) DoorBell record */
- UAR_RES_CQ_SET_CI = 0x1, /* CQ SET_CI DoorBell record */
- UAR_RES_CQ_ARM = 0x2, /* CQ ARM DoorBell record */
- UAR_RES_SQ_DBELL = 0x3, /* Send Queue DoorBell record */
- UAR_RES_RQ_DBELL = 0x4, /* Receive Queue DoorBell record */
- UAR_RES_SRQ_DBELL = 0x5, /* Shared Receive Queue DoorBell record */
- UAR_RES_GROUP_SEP = 0x7 /* Group Separator record */
-};
-
-enum {
- TS_RC,
- TS_UC,
- TS_RD,
- TS_UD,
- TS_MLX
-};
-
-enum {
- PM_STATE_ARMED = 0,
- PM_STATE_REARM = 1,
- PM_STATE_MIGRATED = 3
-};
-
-enum {
- DOORBEL_RES_SQ = 3,
- DOORBEL_RES_RQ = 4,
- DOORBEL_RES_SRQ = 5
-};
-
-struct ib_buffers_st {
- __u8 send_mad_buf[NUM_MADS_SND_WQES][MAD_BUF_SZ];
- __u8 rcv_mad_buf[NUM_MADS_RCV_WQES][MAD_BUF_SZ + GRH_SIZE];
- __u8 ipoib_rcv_buf[NUM_IPOIB_RCV_WQES][IPOIB_RCV_BUF_SZ + GRH_SIZE];
- __u8 ipoib_rcv_grh_buf[NUM_IPOIB_RCV_WQES][IPOIB_RCV_BUF_SZ];
- __u8 send_ipoib_buf[NUM_IPOIB_SND_WQES][IPOIB_SND_BUF_SZ];
-};
-
-struct pcidev {
- unsigned long bar[6];
- __u32 dev_config_space[64];
- struct pci_device *dev;
- __u8 bus;
- __u8 devfn;
-};
-
-struct dev_pci_struct {
- struct pcidev dev;
- struct pcidev br;
- void *cr_space;
- void *uar;
-};
-
-struct eq_st {
- __u8 eqn;
- __u32 cons_counter;
- __u32 eq_size;
- void *ci_base_base_addr;
- struct eqe_t *eq_buf;
-};
-
-struct eqe_t {
- __u8 raw[MT_STRUCT_SIZE(arbelprm_event_queue_entry_st)];
-} __attribute__ ((packed));
-
-enum qp_state_e {
- QP_STATE_RST = 0,
- QP_STATE_INIT = 1,
- QP_STATE_RTR = 2,
- QP_STATE_RTS = 3,
- QP_STATE_SQEr = 4,
- QP_STATE_SQD = 5,
- QP_STATE_ERR = 6,
- QP_STATE_SQDING = 7,
- QP_STATE_SUSPEND = 9
-};
-
-struct memory_pointer_st {
- __u32 byte_count;
- __u32 lkey;
- __u32 local_addr_h;
- __u32 local_addr_l;
-} __attribute__ ((packed));
-
-/* receive wqe descriptor */
-struct recv_wqe_st {
- /* part referenced by hardware */
- __u8 control[MT_STRUCT_SIZE(arbelprm_wqe_segment_ctrl_recv_st)];
- struct memory_pointer_st mpointer[MAX_SCATTER];
-} __attribute__ ((packed));
-
-struct recv_wqe_cont_st {
- struct recv_wqe_st wqe;
-
- struct udqp_st *qp; /* qp this wqe is used with */
-} __attribute__ ((packed));
-
-#define RECV_WQE_U_ALIGN 64
-union recv_wqe_u {
- __u8 align[RECV_WQE_U_ALIGN]; /* this ensures proper alignment */
- struct recv_wqe_st wqe;
- struct recv_wqe_cont_st wqe_cont;
-} __attribute__ ((packed));
-
-struct send_doorbell_st {
- __u8 raw[MT_STRUCT_SIZE(arbelprm_send_doorbell_st)];
-} __attribute__ ((packed));
-
-struct next_control_seg_st {
- __u8 next[MT_STRUCT_SIZE(arbelprm_wqe_segment_next_st)];
- __u8 control[MT_STRUCT_SIZE(arbelprm_wqe_segment_ctrl_send_st)];
-} __attribute__ ((packed));
-
-struct ud_seg_st {
- __u8 av[MT_STRUCT_SIZE(arbelprm_wqe_segment_ud_st)];
-} __attribute__ ((packed));
-
-struct ud_send_wqe_st {
- struct next_control_seg_st next; /* 16 bytes */
- struct ud_seg_st udseg; /* 48 bytes */
- struct memory_pointer_st mpointer[MAX_GATHER]; /* 16 * MAX_GATHER bytes */
-} __attribute__ ((packed));
-
-struct ude_send_wqe_cont_st {
- struct ud_send_wqe_st wqe;
-
- struct udqp_st *qp; /* qp this wqe is used with */
-} __attribute__ ((packed));
-
-#define UD_SEND_WQE_U_ALIGN 128
-union ud_send_wqe_u {
- __u8 align[UD_SEND_WQE_U_ALIGN];
- struct ude_send_wqe_cont_st wqe_cont;
-} __attribute__ ((packed));
-
-struct address_vector_st {
- __u8 raw[MT_STRUCT_SIZE(arbelprm_ud_address_vector_st)];
-} __attribute__ ((packed));
-
-struct ud_av_st {
- struct address_vector_st av;
- __u32 dest_qp; /* destination qpn */
- __u32 qkey;
- __u8 next_free;
-} __attribute__ ((packed));
-
-union ud_av_u {
- struct ud_av_st ud_av;
-} __attribute__ ((packed));
-
-struct udav_st {
- union ud_av_u av_array[NUM_AVS];
- __u8 udav_next_free;
-};
-
-union cqe_st {
- __u8 good_cqe[MT_STRUCT_SIZE(arbelprm_completion_queue_entry_st)];
- __u8 error_cqe[MT_STRUCT_SIZE(arbelprm_completion_with_error_st)];
-} __attribute__ ((packed));
-
-struct qp_ee_ctx_t {
- __u8 raw[MT_STRUCT_SIZE(arbelprm_queue_pair_ee_context_entry_st)];
-} __attribute__ ((packed));
-
-struct qp_ee_state_tarnisition_st {
- __u32 opt_param_mask;
- __u32 r1;
- struct qp_ee_ctx_t ctx;
- __u32 r2[62];
-} __attribute__ ((packed));
-
-struct cq_dbell_st {
- __u8 raw[MT_STRUCT_SIZE(arbelprm_cq_cmd_doorbell_st)];
-} __attribute__ ((packed));
-
-struct mad_ifc_inprm_st {
- union mad_u mad;
-} __attribute__ ((packed));
-
-struct wqe_buf_st {
- struct ud_send_wqe_st *sndq;
- struct recv_wqe_st *rcvq;
-};
-
-struct mad_buffer_st {
- void *buf; /* pointer to a 256 byte buffer */
- __u8 owner; /* sw or hw ownership BUF_OWNER_SW or BUF_OWNER_HW */
-};
-
-struct rcv_buf_st {
- void *buf;
- __u8 busy;
-};
-
-struct ib_eqe_st {
- __u8 event_type;
- __u32 cqn;
-};
-
-struct cq_st {
- __u32 cqn;
- union cqe_st *cq_buf;
- __u32 cons_counter; /* consuner counter */
- __u8 num_cqes;
- __u32 arm_db_ctx_idx;
- void *arm_db_ctx_pointer;
- __u32 ci_db_ctx_idx;
- void *ci_db_ctx_pointer;
-};
-
-struct udqp_st {
- /* cq used by this QP */
- struct cq_st snd_cq;
- struct cq_st rcv_cq;
-
- /* QP related data */
- __u32 qpn; /* QP number */
-
- __u32 qkey;
-
- __u8 recv_wqe_cur_free;
- __u8 recv_wqe_alloc_idx;
- __u8 max_recv_wqes;
- void *rcv_bufs[MAX_RCV_WQES];
- union recv_wqe_u *rcv_wq; /* receive work queue */
- struct recv_wqe_st *last_posted_rcv_wqe;
-
- __u8 snd_wqe_cur_free;
- __u8 snd_wqe_alloc_idx;
- __u8 max_snd_wqes;
- void *snd_bufs[MAX_SND_WQES];
- __u16 send_buf_sz;
- __u16 rcv_buf_sz;
- union ud_send_wqe_u *snd_wq; /* send work queue */
- struct ud_send_wqe_st *last_posted_snd_wqe;
- /* pointers to uar context entries */
- void *send_uar_context;
- __u16 post_send_counter;
- void *rcv_uar_context;
- __u16 post_rcv_counter;
- __u32 snd_db_record_index;
- __u32 rcv_db_record_index;
-};
-
-struct device_ib_data_st {
- __u32 mkey;
- __u32 pd;
- __u8 port;
- __u32 qkey;
- struct eq_st eq;
- struct udav_st udav;
- struct udqp_st mads_qp;
- struct udqp_st ipoib_qp;
- void *clr_int_addr;
- __u32 clr_int_data;
- __u32 uar_idx;
- void *uar_context_base;
- void *error_buf_addr;
- __u32 error_buf_size;
-};
-
-struct query_fw_st {
- __u16 fw_rev_major;
- __u16 fw_rev_minor;
- __u16 fw_rev_subminor;
- __u32 error_buf_start_h;
- __u32 error_buf_start_l;
- __u32 error_buf_size;
- __u32 fw_pages;
- struct addr_64_st eq_ci_table;
- struct addr_64_st clear_int_addr;
-};
-
-struct query_adapter_st {
- __u8 intapin;
-};
-
-struct vpm_entry_st {
- __u32 va_h;
- __u32 va_l;
- __u32 pa_h;
- __u32 pa_l;
- __u8 log2_size;
-};
-
-#define MAX_VPM_PER_CALL 1
-
-struct map_icm_st {
- __u32 num_vpm;
- struct vpm_entry_st vpm_arr[MAX_VPM_PER_CALL];
-};
-
-struct init_hca_st {
- __u32 qpc_base_addr_h;
- __u32 qpc_base_addr_l;
- __u8 log_num_of_qp;
-
- __u32 eec_base_addr_h;
- __u32 eec_base_addr_l;
- __u8 log_num_of_ee;
-
- __u32 srqc_base_addr_h;
- __u32 srqc_base_addr_l;
- __u8 log_num_of_srq;
-
- __u32 cqc_base_addr_h;
- __u32 cqc_base_addr_l;
- __u8 log_num_of_cq;
-
- __u32 eqpc_base_addr_h;
- __u32 eqpc_base_addr_l;
-
- __u32 eeec_base_addr_h;
- __u32 eeec_base_addr_l;
-
- __u32 eqc_base_addr_h;
- __u32 eqc_base_addr_l;
- __u8 log_num_of_eq;
-
- __u32 rdb_base_addr_h;
- __u32 rdb_base_addr_l;
-
- __u32 mc_base_addr_h;
- __u32 mc_base_addr_l;
- __u16 log_mc_table_entry_sz;
- __u32 mc_table_hash_sz;
- __u8 log_mc_table_sz;
-
- __u32 mpt_base_addr_h;
- __u32 mpt_base_addr_l;
- __u8 log_mpt_sz;
- __u32 mtt_base_addr_h;
- __u32 mtt_base_addr_l;
- __u8 log_max_uars;
-};
-
-struct dev_lim_st {
- __u8 log2_rsvd_qps;
- __u16 qpc_entry_sz;
-
- __u8 log2_rsvd_srqs;
- __u16 srq_entry_sz;
-
- __u8 log2_rsvd_ees;
- __u16 eec_entry_sz;
-
- __u8 log2_rsvd_cqs;
- __u16 cqc_entry_sz;
-
- __u8 log2_rsvd_mtts;
- __u16 mtt_entry_sz;
-
- __u8 log2_rsvd_mrws;
- __u16 mpt_entry_sz;
-
- __u8 log2_rsvd_rdbs;
-
- __u16 eqc_entry_sz;
-
- __u32 max_icm_size_l;
- __u32 max_icm_size_h;
-
- __u8 uar_sz;
- __u8 num_rsvd_uars;
-};
-
-static int create_udqp(struct udqp_st *qp);
-static int destroy_udqp(struct udqp_st *qp);
-static void *get_send_wqe_buf(void *wqe, __u8 index);
-static void *get_rcv_wqe_buf(void *wqe, __u8 index);
-
-static struct recv_wqe_st *alloc_rcv_wqe(struct udqp_st *qp);
-static int free_wqe(void *wqe);
-static int poll_cq(void *cqh, union cqe_st *cqe_p, __u8 * num_cqes);
-static int poll_eq(struct ib_eqe_st *ib_eqe_p, __u8 * num_eqes);
-static int post_rcv_buf(struct udqp_st *qp, struct recv_wqe_st *rcv_wqe);
-static __u32 dev_get_qpn(void *qph);
-
-#endif /* __mt25218_h__ */
+++ /dev/null
-typedef uint32_t __u32;
-typedef uint16_t __u16;
-typedef uint8_t __u8;
-
-static int verbose_messages=0;
-static int print_info=0;
-static int fatal_condition=0;
-static int fw_fatal;
-
-#define tprintf(fmt, a...) \
- do { \
- if ( verbose_messages ) { \
- printf("%s:%d: " fmt "\n", __func__, __LINE__, ##a); \
- } \
- } \
- while(0)
-
-#define eprintf(fmt, a...) \
- printf("%s:%d: " fmt "\n", __func__, __LINE__, ##a)
-
-static void cpu_to_be_buf(void *buf, int size)
-{
- int dw_sz = size >> 2, i;
-
- for (i = 0; i < dw_sz; ++i) {
- ((__u32 *) buf)[i] = cpu_to_be32(((__u32 *) buf)[i]);
- }
-}
-
-static void be_to_cpu_buf(void *buf, int size)
-{
- int dw_sz = size >> 2, i;
- u32 *p = buf;
-
- for (i = 0; i < dw_sz; ++i) {
- p[i] = be32_to_cpu(p[i]);
- }
-}
-
-#include "cmdif_mt25218.c"
-#include "cmdif_comm.c"
-#include "ib_mt25218.c"
-#include "ib_mad.c"
-#include "ib_driver.c"
-#include "ipoib.c"
-
-static int probe_imp(struct pci_device *pci, struct nic *nic)
-{
- int rc;
-
- if (0 && nic) { /* just to supress warning */
- return 0;
- }
-
- fatal_condition= 0;
- fw_fatal= 0;
-
- tprintf("");
- rc = ipoib_init(pci);
- if (rc)
- return rc;
-
- tprintf("");
-
- return rc;
-}
-
-static int disable_imp(void)
-{
- int rc;
-
- rc = ipoib_close(fw_fatal);
-
- return rc;
-}
-
-static int transmit_imp(const char *dest, /* Destination */
- unsigned int type, /* Type */
- const char *packet, /* Packet */
- unsigned int size)
-{ /* size */
- int rc;
-
- if (fatal_condition) {
- /* since the transmit function does not return a value
- we return success but do nothing to suppress error messages */
- return 0;
- }
-
- rc = ipoib_send_packet(dest, type, packet, size);
- if (rc) {
- printf("*** ERROR IN SEND FLOW ***\n");
- printf("restarting Etherboot\n");
- sleep(1);
- longjmp(restart_etherboot, -1);
- /* we should not be here ... */
- return -1;
- }
-
- return rc;
-}
-
-static void hd(void *where, int n)
-{
- int i;
-
- while (n > 0) {
- printf("%X ", where);
- for (i = 0; i < ((n > 16) ? 16 : n); i++)
- printf(" %hhX", ((char *)where)[i]);
- printf("\n");
- n -= 16;
- where += 16;
- }
-}
-
-static int poll_imp(struct nic *nic, int retrieve, unsigned int *size_p)
-{
- static char packet[2048];
- static char *last_packet_p = NULL;
- static unsigned long last_packet_size;
- char *packet_p;
- const int eth_header_len = 14;
- unsigned int packet_len;
- int is_bcast = 0;
- __u16 prot, *ptr;
- int rc;
-
- if (0 && nic) { /* just to supress warning */
- return -1;
- }
-
- if (fatal_condition) {
- *size_p = 0;
- return 0;
- }
-
- if (poll_error_buf()) {
- fatal_condition= 1;
- fw_fatal= 1;
- printf("\n *** DEVICE FATAL ERROR ***\n");
- goto fatal_handling;
- }
- else if (drain_eq()) {
- fatal_condition= 1;
- printf("\n *** FATAL ERROR ***\n");
- goto fatal_handling;
- }
-
-
- if (retrieve) {
- /* we actually want to read the packet */
- if (last_packet_p) {
- eprintf("");
- /* there is already a packet that was previously read */
- memcpy(nic->packet, last_packet_p, last_packet_size);
- *size_p = last_packet_size;
- last_packet_p = NULL;
- return 0;
- }
- packet_p = nic->packet;
- } else {
- /* we don't want to read the packet,
- just know if there is one. so we
- read the packet to a local buffer and
- we will return that buffer when the ip layer wants
- another packet */
- if (last_packet_p) {
- /* there is already a packet that
- was not consumend */
- eprintf("overflow receive packets");
- return -1;
- }
- packet_p = packet;
- }
-
- rc = ipoib_read_packet(&prot, packet_p + eth_header_len, &packet_len,
- &is_bcast);
- if (rc) {
- printf("*** FATAL IN RECEIVE FLOW ****\n");
- goto fatal_handling;
- }
-
- if (packet_len == 0) {
- *size_p = 0;
- return 0;
- }
-
- if (is_bcast) {
- int i;
- for (i = 0; i < 6; ++i) {
- packet_p[i] = 0xff;
- }
- } else {
- packet_p[0] = MLX_ETH_BYTE0;
- packet_p[1] = MLX_ETH_BYTE1;
- packet_p[2] = MLX_ETH_BYTE2;
- packet_p[3] = 0;
- packet_p[4] = 0;
- packet_p[5] = 0;
- }
-
- memset(packet_p + 6, 0, 6);
-
- ptr = (__u16 *) (packet_p + 12);
- *ptr = htons(prot);
-
- if (!retrieve) {
- last_packet_p = packet;
- last_packet_size = packet_len + eth_header_len;
- *size_p = 0;
- }
-
- *size_p = packet_len + eth_header_len;
- tprintf("packet size=%d, prot=%x\n", *size_p, prot);
- if (0) {
- hd(nic->packet, 42);
- }
-
- return 0;
-
-fatal_handling:
- printf("restarting Etherboot\n");
- sleep(1);
- longjmp(restart_etherboot, -1);
- /* we should not be here ... */
- return -1;
-
-}
+++ /dev/null
-/*
- This software is available to you under a choice of one of two
- licenses. You may choose to be licensed under the terms of the GNU
- General Public License (GPL) Version 2, available at
- <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
- license, available in the LICENSE.TXT file accompanying this
- software. These details are also available at
- <http://openib.org/license.html>.
-
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
-
- Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
-*/
-
-/* definition of the build version goes here */
-const char *build_revision= "113";
+++ /dev/null
-diff -ru ../../orig/dhcp-3.0.4b2/common/options.c ./common/options.c
---- ../../orig/dhcp-3.0.4b2/common/options.c 2005-11-02 01:19:03.000000000 +0200
-+++ ./common/options.c 2005-12-06 14:38:17.000000000 +0200
-@@ -537,6 +537,7 @@
- priority_list [priority_len++] = DHO_DHCP_LEASE_TIME;
- priority_list [priority_len++] = DHO_DHCP_MESSAGE;
- priority_list [priority_len++] = DHO_DHCP_REQUESTED_ADDRESS;
-+ priority_list [priority_len++] = DHO_DHCP_CLIENT_IDENTIFIER;
- priority_list [priority_len++] = DHO_FQDN;
-
- if (prl && prl -> len > 0) {
-diff -ru ../../orig/dhcp-3.0.4b2/includes/site.h ./includes/site.h
---- ../../orig/dhcp-3.0.4b2/includes/site.h 2002-03-12 20:33:39.000000000 +0200
-+++ ./includes/site.h 2005-12-06 14:36:55.000000000 +0200
-@@ -135,7 +135,7 @@
- the aforementioned problems do not matter to you, or if no other
- API is supported for your system, you may want to go with it. */
-
--/* #define USE_SOCKETS */
-+#define USE_SOCKETS
-
- /* Define this to use the Sun Streams NIT API.
-
+++ /dev/null
-# dhcpd.conf
-#
-# Sample configuration file for ISC dhcpd
-#
-
-# option definitions common to all supported networks...
-
-DHCPD_INTERFACE = "ib0";
-
-# if you do not use dynamical DNS updates:
-#
-# this statement is needed by dhcpd-3 needs at least this statement.
-# you have to delete it for dhcpd-2, because it does not know it.
-#
-# if you want to use dynamical DNS updates, you should first read
-# read /usr/share/doc/packages/dhcp-server/DDNS-howto.txt
-ddns-update-style none; ddns-updates off;
-
-filename "pxelinux.bin";
-
-# If this DHCP server is the official DHCP server for the local
-# network, the authoritative directive should be uncommented.
-#authoritative;
-
-# No service will be given on this subnet, but declaring it helps the
-# DHCP server to understand the network topology.
-
-subnet 10.152.187.0 netmask 255.255.255.0 {
-}
-
-# This declaration allows BOOTP clients to get dynamic addresses,
-# which we don't really recommend.
-
-shared-network "ipoib_network" {
- subnet 11.4.8.0 netmask 255.255.255.0 {
- option dhcp-client-identifier = option dhcp-client-identifier;
- option subnet-mask 255.255.255.0;
- option domain-name "yok.mtl.com";
- option domain-name-servers 10.0.0.1;
- default-lease-time 28800;
- max-lease-time 86400;
- next-server 11.4.8.99;
-
- }
-}
-
-
-# You need one such entry for each client
-host swlab35 {
- fixed-address 11.4.8.35; # the IP address to be assigned to the client
- # The value of the client identifier must be comprised from the prefix 20:00:
- # folowed by the client's ipoib qp number - 55:04:01 in this example -
- # followed by the GID of the port
- option dhcp-client-identifier = 20:00:55:04:01:fe:80:00:00:00:00:00:00:00:02:c9:00:01:70:8a:81;
-}
-
/* Reset the chip to erase previous misconfiguration */
DBG ( "ASIC Control is %#x\n", inl(BASE + ASICCtrl) );
outw(0x007f, BASE + ASICCtrl + 2);
+
+ /*
+ * wait for reset to complete
+ * this is heavily inspired by the linux sundance driver
+ * according to the linux driver it can take up to 1ms for the reset
+ * to complete
+ */
+ i = 0;
+ while(inl(BASE + ASICCtrl) & (ResetBusy << 16)) {
+ if(i++ >= 10) {
+ DBG("sundance: NIC reset did not complete.\n");
+ break;
+ }
+ udelay(100);
+ }
+
DBG ( "ASIC Control is now %#x.\n", inl(BASE + ASICCtrl) );
sundance_reset(nic);
}
/**
+ * The "chain" command
+ *
+ * @v argc Argument count
+ * @v argv Argument list
+ * @ret rc Exit code
+ */
+static int chain_exec ( int argc, char **argv) {
+ int rc;
+
+ if ( ( rc = imgfetch_core_exec ( NULL, IMG_EXEC, argc, argv ) ) != 0 )
+ return rc;
+
+ return 0;
+}
+
+/**
* "imgload" command syntax message
*
* @v argv Argument list
.exec = kernel_exec,
},
{
+ .name = "chain",
+ .exec = chain_exec,
+ },
+ {
.name = "imgload",
.exec = imgload_exec,
},
+++ /dev/null
-#!gpxe
-autoboot
*
* @v refcnt Reference counter
*/
-static void embedded_image_free ( struct refcnt *refcnt __unused ) {
+static void __attribute__ (( unused ))
+embedded_image_free ( struct refcnt *refcnt __unused ) {
/* Do nothing */
}
* Register all embedded images
*/
static void embedded_init ( void ) {
- unsigned int i;
+ int i;
struct image *image;
void *data;
int rc;
+ /* Skip if we have no embedded images */
+ if ( ! sizeof ( embedded_images ) )
+ return;
+
/* Fix up data pointers and register images */
- for ( i = 0 ; i < ( sizeof ( embedded_images ) /
- sizeof ( embedded_images[0] ) ) ; i++ ) {
+ for ( i = 0 ; i < ( int ) ( sizeof ( embedded_images ) /
+ sizeof ( embedded_images[0] ) ) ; i++ ) {
image = &embedded_images[i];
/* virt_to_user() cannot be used in a static
#ifndef _GPXE_AES_H
#define _GPXE_AES_H
-struct crypto_algorithm;
+struct cipher_algorithm;
-extern struct crypto_algorithm aes_algorithm;
+extern struct cipher_algorithm aes_cbc_algorithm;
#endif /* _GPXE_AES_H */
--- /dev/null
+#ifndef _GPXE_CBC_H
+#define _GPXE_CBC_H
+
+/** @file
+ *
+ * Cipher-block chaining
+ *
+ */
+
+#include <gpxe/crypto.h>
+
+/**
+ * Set key
+ *
+ * @v ctx Context
+ * @v key Key
+ * @v keylen Key length
+ * @v raw_cipher Underlying cipher algorithm
+ * @v cbc_ctx CBC context
+ * @ret rc Return status code
+ */
+static inline int cbc_setkey ( void *ctx, const void *key, size_t keylen,
+ struct cipher_algorithm *raw_cipher,
+ void *cbc_ctx __unused ) {
+
+ return cipher_setkey ( raw_cipher, ctx, key, keylen );
+}
+
+/**
+ * Set initialisation vector
+ *
+ * @v ctx Context
+ * @v iv Initialisation vector
+ * @v raw_cipher Underlying cipher algorithm
+ * @v cbc_ctx CBC context
+ */
+static inline void cbc_setiv ( void *ctx __unused, const void *iv,
+ struct cipher_algorithm *raw_cipher,
+ void *cbc_ctx ) {
+ memcpy ( cbc_ctx, iv, raw_cipher->blocksize );
+}
+
+extern void cbc_encrypt ( void *ctx, const void *src, void *dst,
+ size_t len, struct cipher_algorithm *raw_cipher,
+ void *cbc_ctx );
+extern void cbc_decrypt ( void *ctx, const void *src, void *dst,
+ size_t len, struct cipher_algorithm *raw_cipher,
+ void *cbc_ctx );
+
+/**
+ * Create a cipher-block chaining mode of behaviour of an existing cipher
+ *
+ * @v _cbc_name Name for the new CBC cipher
+ * @v _cbc_cipher New cipher algorithm
+ * @v _raw_cipher Underlying cipher algorithm
+ * @v _raw_context Context structure for the underlying cipher
+ * @v _blocksize Cipher block size
+ */
+#define CBC_CIPHER( _cbc_name, _cbc_cipher, _raw_cipher, _raw_context, \
+ _blocksize ) \
+struct _cbc_name ## _context { \
+ _raw_context raw_ctx; \
+ uint8_t cbc_ctx[_blocksize]; \
+}; \
+static int _cbc_name ## _setkey ( void *ctx, const void *key, \
+ size_t keylen ) { \
+ struct _cbc_name ## _context * _cbc_name ## _ctx = ctx; \
+ return cbc_setkey ( &_cbc_name ## _ctx->raw_ctx, key, keylen, \
+ &_raw_cipher, &_cbc_name ## _ctx->cbc_ctx );\
+} \
+static void _cbc_name ## _setiv ( void *ctx, const void *iv ) { \
+ struct _cbc_name ## _context * _cbc_name ## _ctx = ctx; \
+ cbc_setiv ( &_cbc_name ## _ctx->raw_ctx, iv, \
+ &_raw_cipher, &aes_cbc_ctx->cbc_ctx ); \
+} \
+static void _cbc_name ## _encrypt ( void *ctx, const void *src, \
+ void *dst, size_t len ) { \
+ struct _cbc_name ## _context * _cbc_name ## _ctx = ctx; \
+ cbc_encrypt ( &_cbc_name ## _ctx->raw_ctx, src, dst, len, \
+ &_raw_cipher, &aes_cbc_ctx->cbc_ctx ); \
+} \
+static void _cbc_name ## _decrypt ( void *ctx, const void *src, \
+ void *dst, size_t len ) { \
+ struct _cbc_name ## _context * _cbc_name ## _ctx = ctx; \
+ cbc_decrypt ( &_cbc_name ## _ctx->raw_ctx, src, dst, len, \
+ &_raw_cipher, &aes_cbc_ctx->cbc_ctx ); \
+} \
+struct cipher_algorithm _cbc_cipher = { \
+ .name = #_cbc_name, \
+ .ctxsize = sizeof ( struct _cbc_name ## _context ), \
+ .blocksize = _blocksize, \
+ .setkey = _cbc_name ## _setkey, \
+ .setiv = _cbc_name ## _setiv, \
+ .encrypt = _cbc_name ## _encrypt, \
+ .decrypt = _cbc_name ## _decrypt, \
+};
+
+#endif /* _GPXE_CBC_H */
#include <stdint.h>
#include <gpxe/md5.h>
-struct crypto_algorithm;
+struct digest_algorithm;
/** A CHAP response */
struct chap_response {
/** Digest algorithm used for the response */
- struct crypto_algorithm *digest;
+ struct digest_algorithm *digest;
/** Context used by the digest algorithm */
uint8_t *digest_context;
/** CHAP response */
};
extern int chap_init ( struct chap_response *chap,
- struct crypto_algorithm *digest );
+ struct digest_algorithm *digest );
extern void chap_update ( struct chap_response *chap, const void *data,
size_t len );
extern void chap_respond ( struct chap_response *chap );
#include <stdint.h>
#include <stddef.h>
-/** A cryptographic algorithm */
-struct crypto_algorithm {
+/** A message digest algorithm */
+struct digest_algorithm {
/** Algorithm name */
const char *name;
/** Context size */
size_t ctxsize;
/** Block size */
size_t blocksize;
- /** Final output size */
+ /** Digest size */
size_t digestsize;
- /** Initialise algorithm
+ /** Initialise digest
*
* @v ctx Context
*/
void ( * init ) ( void *ctx );
+ /** Update digest with new data
+ *
+ * @v ctx Context
+ * @v src Data to digest
+ * @v len Length of data
+ *
+ * @v len is not necessarily a multiple of @c blocksize.
+ */
+ void ( * update ) ( void *ctx, const void *src, size_t len );
+ /** Finalise digest
+ *
+ * @v ctx Context
+ * @v out Buffer for digest output
+ */
+ void ( * final ) ( void *ctx, void *out );
+};
+
+/** A cipher algorithm */
+struct cipher_algorithm {
+ /** Algorithm name */
+ const char *name;
+ /** Context size */
+ size_t ctxsize;
+ /** Block size */
+ size_t blocksize;
/** Set key
*
* @v ctx Context
* @v ctx Context
* @v iv Initialisation vector
*/
- void ( *setiv ) ( void *ctx, const void *iv );
- /** Encode data
+ void ( * setiv ) ( void *ctx, const void *iv );
+ /** Encrypt data
*
* @v ctx Context
- * @v src Data to encode
- * @v dst Encoded data, or NULL
+ * @v src Data to encrypt
+ * @v dst Buffer for encrypted data
* @v len Length of data
- * @ret rc Return status code
- *
- * For a cipher algorithm, the enciphered data should be
- * placed in @c dst. For a digest algorithm, only the digest
- * state should be updated, and @c dst will be NULL.
*
* @v len is guaranteed to be a multiple of @c blocksize.
*/
- void ( * encode ) ( void *ctx, const void *src, void *dst,
- size_t len );
- /** Decode data
+ void ( * encrypt ) ( void *ctx, const void *src, void *dst,
+ size_t len );
+ /** Decrypt data
*
* @v ctx Context
- * @v src Data to decode
- * @v dst Decoded data
+ * @v src Data to decrypt
+ * @v dst Buffer for decrypted data
* @v len Length of data
- * @ret rc Return status code
*
* @v len is guaranteed to be a multiple of @c blocksize.
*/
- void ( * decode ) ( void *ctx, const void *src, void *dst,
- size_t len );
- /** Finalise algorithm
- *
- * @v ctx Context
- * @v out Algorithm final output
- */
- void ( * final ) ( void *ctx, void *out );
+ void ( * decrypt ) ( void *ctx, const void *src, void *dst,
+ size_t len );
};
-static inline void digest_init ( struct crypto_algorithm *crypto,
+/** A public key algorithm */
+struct pubkey_algorithm {
+ /** Algorithm name */
+ const char *name;
+ /** Context size */
+ size_t ctxsize;
+};
+
+static inline void digest_init ( struct digest_algorithm *digest,
void *ctx ) {
- crypto->init ( ctx );
+ digest->init ( ctx );
}
-static inline void digest_update ( struct crypto_algorithm *crypto,
+static inline void digest_update ( struct digest_algorithm *digest,
void *ctx, const void *data, size_t len ) {
- crypto->encode ( ctx, data, NULL, len );
+ digest->update ( ctx, data, len );
}
-static inline void digest_final ( struct crypto_algorithm *crypto,
+static inline void digest_final ( struct digest_algorithm *digest,
void *ctx, void *out ) {
- crypto->final ( ctx, out );
+ digest->final ( ctx, out );
+}
+
+static inline int cipher_setkey ( struct cipher_algorithm *cipher,
+ void *ctx, const void *key, size_t keylen ) {
+ return cipher->setkey ( ctx, key, keylen );
}
-static inline void cipher_setiv ( struct crypto_algorithm *crypto,
+static inline void cipher_setiv ( struct cipher_algorithm *cipher,
void *ctx, const void *iv ) {
- crypto->setiv ( ctx, iv );
+ cipher->setiv ( ctx, iv );
}
-static inline int cipher_setkey ( struct crypto_algorithm *crypto,
- void *ctx, const void *key, size_t keylen ) {
- return crypto->setkey ( ctx, key, keylen );
+static inline void cipher_encrypt ( struct cipher_algorithm *cipher,
+ void *ctx, const void *src, void *dst,
+ size_t len ) {
+ cipher->encrypt ( ctx, src, dst, len );
}
+#define cipher_encrypt( cipher, ctx, src, dst, len ) do { \
+ assert ( ( len & ( (cipher)->blocksize - 1 ) ) == 0 ); \
+ cipher_encrypt ( (cipher), (ctx), (src), (dst), (len) ); \
+ } while ( 0 )
-static inline int is_stream_cipher ( struct crypto_algorithm *crypto ) {
- return ( crypto->blocksize == 1 );
+static inline void cipher_decrypt ( struct cipher_algorithm *cipher,
+ void *ctx, const void *src, void *dst,
+ size_t len ) {
+ cipher->decrypt ( ctx, src, dst, len );
}
+#define cipher_decrypt( cipher, ctx, src, dst, len ) do { \
+ assert ( ( len & ( (cipher)->blocksize - 1 ) ) == 0 ); \
+ cipher_decrypt ( (cipher), (ctx), (src), (dst), (len) ); \
+ } while ( 0 )
-extern struct crypto_algorithm crypto_null;
+static inline int is_stream_cipher ( struct cipher_algorithm *cipher ) {
+ return ( cipher->blocksize == 1 );
+}
-extern int cipher_encrypt ( struct crypto_algorithm *crypto,
- void *ctx, const void *src, void *dst,
- size_t len );
-extern int cipher_decrypt ( struct crypto_algorithm *crypto,
- void *ctx, const void *src, void *dst,
- size_t len );
+extern struct digest_algorithm digest_null;
+extern struct cipher_algorithm cipher_null;
+extern struct pubkey_algorithm pubkey_null;
#endif /* _GPXE_CRYPTO_H */
* @v data Data
* @v len Length of data
*/
-static inline void hmac_update ( struct crypto_algorithm *digest,
+static inline void hmac_update ( struct digest_algorithm *digest,
void *digest_ctx, const void *data,
size_t len ) {
digest_update ( digest, digest_ctx, data, len );
}
-extern void hmac_init ( struct crypto_algorithm *digest, void *digest_ctx,
+extern void hmac_init ( struct digest_algorithm *digest, void *digest_ctx,
void *key, size_t *key_len );
-extern void hmac_final ( struct crypto_algorithm *digest, void *digest_ctx,
+extern void hmac_final ( struct digest_algorithm *digest, void *digest_ctx,
void *key, size_t *key_len, void *hmac );
#endif /* _GPXE_HMAC_H */
#define for_each_image( image ) \
list_for_each_entry ( (image), &images, list )
+/**
+ * Test for existence of images
+ *
+ * @ret existence Some images exist
+ */
+static inline int have_images ( void ) {
+ return ( ! list_empty ( &images ) );
+}
+
extern struct image * alloc_image ( void );
extern int image_set_uri ( struct image *image, struct uri *uri );
extern int image_set_cmdline ( struct image *image, const char *cmdline );
char *target_username;
/** Target password (if any) */
char *target_password;
- /** Target has authenticated acceptably */
- int target_auth_ok;
/** CHAP challenge (for target auth only)
*
* This is a block of random data; the first byte is used as
/** Mask for all iSCSI "needs to send" flags */
#define ISCSI_STATUS_STRINGS_MASK 0xff00
+/** Target has requested forward (initiator) authentication */
+#define ISCSI_STATUS_AUTH_FORWARD_REQUIRED 0x00010000
+
+/** Initiator requires target (reverse) authentication */
+#define ISCSI_STATUS_AUTH_REVERSE_REQUIRED 0x00020000
+
+/** Target authenticated itself correctly */
+#define ISCSI_STATUS_AUTH_REVERSE_OK 0x00040000
+
/** Maximum number of retries at connecting */
#define ISCSI_MAX_RETRIES 2
#ifndef _GPXE_MD5_H
#define _GPXE_MD5_H
-struct crypto_algorithm;
+struct digest_algorithm;
#include <stdint.h>
#define MD5_CTX_SIZE sizeof ( struct md5_ctx )
-extern struct crypto_algorithm md5_algorithm;
+extern struct digest_algorithm md5_algorithm;
#endif /* _GPXE_MD5_H */
#ifndef _GPXE_RSA_H
#define _GPXE_RSA_H
-struct crypto_algorithm;
+struct pubkey_algorithm;
-extern struct crypto_algorithm rsa_algorithm;
+extern struct pubkey_algorithm rsa_algorithm;
#include "crypto/axtls/crypto.h"
#include "crypto/axtls/crypto.h"
-struct crypto_algorithm;
+struct digest_algorithm;
#define SHA1_CTX_SIZE sizeof ( SHA1_CTX )
#define SHA1_DIGEST_SIZE SHA1_SIZE
-extern struct crypto_algorithm sha1_algorithm;
+extern struct digest_algorithm sha1_algorithm;
#endif /* _GPXE_SHA1_H */
/** A TLS cipher specification */
struct tls_cipherspec {
/** Public-key encryption algorithm */
- struct crypto_algorithm *pubkey;
+ struct pubkey_algorithm *pubkey;
/** Bulk encryption cipher algorithm */
- struct crypto_algorithm *cipher;
+ struct cipher_algorithm *cipher;
/** MAC digest algorithm */
- struct crypto_algorithm *digest;
+ struct digest_algorithm *digest;
/** Key length */
size_t key_len;
/** Dynamically-allocated storage */
/* Enter security negotiation phase */
iscsi->status = ( ISCSI_STATUS_SECURITY_NEGOTIATION_PHASE |
ISCSI_STATUS_STRINGS_SECURITY );
+ if ( iscsi->target_username )
+ iscsi->status |= ISCSI_STATUS_AUTH_REVERSE_REQUIRED;
/* Assign fresh initiator task tag */
iscsi->itt++;
/* Clear connection status */
iscsi->status = 0;
- /* Deauthenticate target */
- iscsi->target_auth_ok = 0;
-
/* Reset TX and RX state machines */
iscsi->tx_state = ISCSI_TX_IDLE;
iscsi->rx_state = ISCSI_RX_BHS;
static int iscsi_handle_authmethod_value ( struct iscsi_session *iscsi,
const char *value ) {
- /* Mark target as authenticated if no authentication required */
- if ( ! iscsi->target_username )
- iscsi->target_auth_ok = 1;
-
/* If server requests CHAP, send the CHAP_A string */
if ( strcmp ( value, "CHAP" ) == 0 ) {
DBGC ( iscsi, "iSCSI %p initiating CHAP authentication\n",
iscsi );
- iscsi->status |= ISCSI_STATUS_STRINGS_CHAP_ALGORITHM;
+ iscsi->status |= ( ISCSI_STATUS_STRINGS_CHAP_ALGORITHM |
+ ISCSI_STATUS_AUTH_FORWARD_REQUIRED );
}
return 0;
assert ( i == iscsi->chap.response_len );
/* Mark session as authenticated */
- iscsi->target_auth_ok = 1;
+ iscsi->status |= ISCSI_STATUS_AUTH_REVERSE_OK;
return 0;
}
/* Handle login transitions */
if ( response->flags & ISCSI_LOGIN_FLAG_TRANSITION ) {
+ iscsi->status &= ~( ISCSI_STATUS_PHASE_MASK |
+ ISCSI_STATUS_STRINGS_MASK );
switch ( response->flags & ISCSI_LOGIN_NSG_MASK ) {
case ISCSI_LOGIN_NSG_OPERATIONAL_NEGOTIATION:
- iscsi->status =
+ iscsi->status |=
( ISCSI_STATUS_OPERATIONAL_NEGOTIATION_PHASE |
ISCSI_STATUS_STRINGS_OPERATIONAL );
break;
case ISCSI_LOGIN_NSG_FULL_FEATURE_PHASE:
- iscsi->status = ISCSI_STATUS_FULL_FEATURE_PHASE;
+ iscsi->status |= ISCSI_STATUS_FULL_FEATURE_PHASE;
break;
default:
DBGC ( iscsi, "iSCSI %p got invalid response flags "
}
/* Check that target authentication was successful (if required) */
- if ( ! iscsi->target_auth_ok ) {
+ if ( ( iscsi->status & ISCSI_STATUS_AUTH_REVERSE_REQUIRED ) &&
+ ! ( iscsi->status & ISCSI_STATUS_AUTH_REVERSE_OK ) ) {
DBGC ( iscsi, "iSCSI %p nefarious target tried to bypass "
"authentication\n", iscsi );
return -EPROTO;
* @v digest_ctx Digest context
* @v args ( data, len ) pairs of data, terminated by NULL
*/
-static void tls_hmac_update_va ( struct crypto_algorithm *digest,
+static void tls_hmac_update_va ( struct digest_algorithm *digest,
void *digest_ctx, va_list args ) {
void *data;
size_t len;
* @v seeds ( data, len ) pairs of seed data, terminated by NULL
*/
static void tls_p_hash_va ( struct tls_session *tls,
- struct crypto_algorithm *digest,
+ struct digest_algorithm *digest,
void *secret, size_t secret_len,
void *out, size_t out_len,
va_list seeds ) {
tls, strerror ( rc ) );
return rc;
}
-
- /* FIXME: AES needs to be fixed to not require this */
- AES_convert_key ( rx_cipherspec->cipher_ctx );
-
DBGC ( tls, "TLS %p RX key:\n", tls );
DBGC_HD ( tls, key, key_size );
key += key_size;
struct tls_cipherspec *cipherspec ) {
free ( cipherspec->dynamic );
memset ( cipherspec, 0, sizeof ( cipherspec ) );
- cipherspec->pubkey = &crypto_null;
- cipherspec->cipher = &crypto_null;
- cipherspec->digest = &crypto_null;
+ cipherspec->pubkey = &pubkey_null;
+ cipherspec->cipher = &cipher_null;
+ cipherspec->digest = &digest_null;
}
/**
*/
static int tls_set_cipher ( struct tls_session *tls,
struct tls_cipherspec *cipherspec,
- struct crypto_algorithm *pubkey,
- struct crypto_algorithm *cipher,
- struct crypto_algorithm *digest,
+ struct pubkey_algorithm *pubkey,
+ struct cipher_algorithm *cipher,
+ struct digest_algorithm *digest,
size_t key_len ) {
size_t total;
void *dynamic;
*/
static int tls_select_cipher ( struct tls_session *tls,
unsigned int cipher_suite ) {
- struct crypto_algorithm *pubkey = &crypto_null;
- struct crypto_algorithm *cipher = &crypto_null;
- struct crypto_algorithm *digest = &crypto_null;
+ struct pubkey_algorithm *pubkey = &pubkey_null;
+ struct cipher_algorithm *cipher = &cipher_null;
+ struct digest_algorithm *digest = &digest_null;
unsigned int key_len = 0;
int rc;
switch ( cipher_suite ) {
case htons ( TLS_RSA_WITH_AES_128_CBC_SHA ):
key_len = ( 128 / 8 );
- cipher = &aes_algorithm;
+ cipher = &aes_cbc_algorithm;
digest = &sha1_algorithm;
break;
case htons ( TLS_RSA_WITH_AES_256_CBC_SHA ):
key_len = ( 256 / 8 );
- cipher = &aes_algorithm;
+ cipher = &aes_cbc_algorithm;
digest = &sha1_algorithm;
break;
default:
/* Sanity check */
if ( /* FIXME (when pubkey is not hard-coded to RSA):
- * ( pending->pubkey == &crypto_null ) || */
- ( pending->cipher == &crypto_null ) ||
- ( pending->digest == &crypto_null ) ) {
+ * ( pending->pubkey == &pubkey_null ) || */
+ ( pending->cipher == &cipher_null ) ||
+ ( pending->digest == &digest_null ) ) {
DBGC ( tls, "TLS %p refusing to use null cipher\n", tls );
return -ENOTSUP;
}
* far.
*/
static void tls_verify_handshake ( struct tls_session *tls, void *out ) {
- struct crypto_algorithm *md5 = &md5_algorithm;
- struct crypto_algorithm *sha1 = &sha1_algorithm;
+ struct digest_algorithm *md5 = &md5_algorithm;
+ struct digest_algorithm *sha1 = &sha1_algorithm;
uint8_t md5_ctx[md5->ctxsize];
uint8_t sha1_ctx[sha1->ctxsize];
void *md5_digest = out;
struct tls_cipherspec *cipherspec,
uint64_t seq, struct tls_header *tlshdr,
const void *data, size_t len, void *hmac ) {
- struct crypto_algorithm *digest = cipherspec->digest;
+ struct digest_algorithm *digest = cipherspec->digest;
uint8_t digest_ctx[digest->ctxsize];
hmac_init ( digest, digest_ctx, cipherspec->mac_secret,
tlshdr->length = htons ( plaintext_len );
memcpy ( cipherspec->cipher_next_ctx, cipherspec->cipher_ctx,
cipherspec->cipher->ctxsize );
- if ( ( rc = cipher_encrypt ( cipherspec->cipher,
- cipherspec->cipher_next_ctx, plaintext,
- iob_put ( ciphertext, plaintext_len ),
- plaintext_len ) ) != 0 ) {
- DBGC ( tls, "TLS %p could not encrypt: %s\n",
- tls, strerror ( rc ) );
- DBGC_HD ( tls, plaintext, plaintext_len );
- goto done;
- }
+ cipher_encrypt ( cipherspec->cipher, cipherspec->cipher_next_ctx,
+ plaintext, iob_put ( ciphertext, plaintext_len ),
+ plaintext_len );
/* Free plaintext as soon as possible to conserve memory */
free ( plaintext );
}
/* Decrypt the record */
- if ( ( rc = cipher_decrypt ( cipherspec->cipher,
- cipherspec->cipher_ctx, ciphertext,
- plaintext, record_len ) ) != 0 ) {
- DBGC ( tls, "TLS %p could not decrypt: %s\n",
- tls, strerror ( rc ) );
- DBGC_HD ( tls, ciphertext, record_len );
- goto done;
- }
+ cipher_decrypt ( cipherspec->cipher, cipherspec->cipher_ctx,
+ ciphertext, plaintext, record_len );
/* Split record into content and MAC */
if ( is_stream_cipher ( cipherspec->cipher ) ) {
+++ /dev/null
-#!gpxe
-kernel http://www.zytor.com/netboot/pxelinux.0
-set filename http://www.zytor.com/netboot/pxelinux.0
-boot
projects / platform / upstream / syslinux.git / commitdiff