board: artik5: correct WRSTBI gpio pin

Unlike any other exynos3250 boards, the WRSTBI pin of the artik5 is connected
to GPE1_2. This patch fixes the pin from GPE1_1 to GPE1_2 only for
artik5.

Created-by: jeho park <jhpark@insignal.co.kr>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>

diff --git a/board/samsung/espresso3250/lowlevel_init.S b/board/samsung/espresso3250/lowlevel_init.S
index fb66fbe7961e295a42baf30e782014eede52a10e..927259ffe9ed35dd12fd4c2920ca14e17b862e63 100644 (file)
--- a/board/samsung/espresso3250/lowlevel_init.S
+++ b/board/samsung/espresso3250/lowlevel_init.S
@@ -129,6 +129,21 @@ pmic_gpio_init:
        mov     r1, #0x0
        str     r1, [r0]
 
+#ifdef CONFIG_MACH_ARTIK5
+       /* Set PMIC WRSTBI(GPE1_2) to Output */
+       ldr     r0, =(0x11000140)
+       ldr     r1, [r0]
+       bic     r2, r1, #0xF00
+       and     r1, r1, r2
+       orr     r1, r1, #0x100
+       str     r1, [r0]
+
+       /* Set PMIC WRSTBI(GPE1_2) to High */
+       ldr     r0, =(0x11000144)
+       ldr     r1, [r0]
+       orr     r1, r1, #0x4
+       str     r1, [r0]
+#else
        /* Set PMIC WRSTBI(GPE1_1) to Output */
        ldr     r0, =(0x11000140)
        ldr     r1, [r0]
@@ -142,6 +157,7 @@ pmic_gpio_init:
        ldr     r1, [r0]
        orr     r1, r1, #0x2
        str     r1, [r0]
+#endif
        mov     pc, lr
 
 read_om: