dt-bindings: iommu: Convert QCOM IOMMU to YAML

Convert the Qualcomm IOMMU bindings to YAML.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230406-topic-qciommu-v3-1-aa0e4f018191@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>

diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
deleted file mode 100644 (file)
index e6cecfd..0000000
--- a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
+++ /dev/null
@@ -1,122 +0,0 @@
-* QCOM IOMMU v1 Implementation
-
-Qualcomm "B" family devices which are not compatible with arm-smmu have
-a similar looking IOMMU but without access to the global register space,
-and optionally requiring additional configuration to route context irqs
-to non-secure vs secure interrupt line.
-
-** Required properties:
-
-- compatible       : Should be one of:
-
-                        "qcom,msm8916-iommu"
-                        "qcom,msm8953-iommu"
-
-                     Followed by "qcom,msm-iommu-v1".
-
-- clock-names      : Should be a pair of "iface" (required for IOMMUs
-                     register group access) and "bus" (required for
-                     the IOMMUs underlying bus access).
-
-- clocks           : Phandles for respective clocks described by
-                     clock-names.
-
-- #address-cells   : must be 1.
-
-- #size-cells      : must be 1.
-
-- #iommu-cells     : Must be 1.  Index identifies the context-bank #.
-
-- ranges           : Base address and size of the iommu context banks.
-
-- qcom,iommu-secure-id  : secure-id.
-
-- List of sub-nodes, one per translation context bank.  Each sub-node
-  has the following required properties:
-
-  - compatible     : Should be one of:
-        - "qcom,msm-iommu-v1-ns"  : non-secure context bank
-        - "qcom,msm-iommu-v1-sec" : secure context bank
-  - reg            : Base address and size of context bank within the iommu
-  - interrupts     : The context fault irq.
-
-** Optional properties:
-
-- reg              : Base address and size of the SMMU local base, should
-                     be only specified if the iommu requires configuration
-                     for routing of context bank irq's to secure vs non-
-                     secure lines.  (Ie. if the iommu contains secure
-                     context banks)
-
-
-** Examples:
-
-       apps_iommu: iommu@1e20000 {
-               #address-cells = <1>;
-               #size-cells = <1>;
-               #iommu-cells = <1>;
-               compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
-               ranges = <0 0x1e20000 0x40000>;
-               reg = <0x1ef0000 0x3000>;
-               clocks = <&gcc GCC_SMMU_CFG_CLK>,
-                        <&gcc GCC_APSS_TCU_CLK>;
-               clock-names = "iface", "bus";
-               qcom,iommu-secure-id = <17>;
-
-               // mdp_0:
-               iommu-ctx@4000 {
-                       compatible = "qcom,msm-iommu-v1-ns";
-                       reg = <0x4000 0x1000>;
-                       interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-               };
-
-               // venus_ns:
-               iommu-ctx@5000 {
-                       compatible = "qcom,msm-iommu-v1-sec";
-                       reg = <0x5000 0x1000>;
-                       interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-               };
-       };
-
-       gpu_iommu: iommu@1f08000 {
-               #address-cells = <1>;
-               #size-cells = <1>;
-               #iommu-cells = <1>;
-               compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
-               ranges = <0 0x1f08000 0x10000>;
-               clocks = <&gcc GCC_SMMU_CFG_CLK>,
-                        <&gcc GCC_GFX_TCU_CLK>;
-               clock-names = "iface", "bus";
-               qcom,iommu-secure-id = <18>;
-
-               // gfx3d_user:
-               iommu-ctx@1000 {
-                       compatible = "qcom,msm-iommu-v1-ns";
-                       reg = <0x1000 0x1000>;
-                       interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
-               };
-
-               // gfx3d_priv:
-               iommu-ctx@2000 {
-                       compatible = "qcom,msm-iommu-v1-ns";
-                       reg = <0x2000 0x1000>;
-                       interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
-               };
-       };
-
-       ...
-
-       venus: video-codec@1d00000 {
-               ...
-               iommus = <&apps_iommu 5>;
-       };
-
-       mdp: mdp@1a01000 {
-               ...
-               iommus = <&apps_iommu 4>;
-       };
-
-       gpu@1c00000 {
-               ...
-               iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
-       };

diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
new file mode 100644 (file)
index 0000000..d9fabdf
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies legacy IOMMU implementations
+
+maintainers:
+  - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+description: |
+  Qualcomm "B" family devices which are not compatible with arm-smmu have
+  a similar looking IOMMU, but without access to the global register space
+  and optionally requiring additional configuration to route context IRQs
+  to non-secure vs secure interrupt line.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - qcom,msm8916-iommu
+          - qcom,msm8953-iommu
+      - const: qcom,msm-iommu-v1
+
+  clocks:
+    items:
+      - description: Clock required for IOMMU register group access
+      - description: Clock required for underlying bus access
+
+  clock-names:
+    items:
+      - const: iface
+      - const: bus
+
+  power-domains:
+    maxItems: 1
+
+  reg:
+    maxItems: 1
+
+  ranges: true
+
+  qcom,iommu-secure-id:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      The SCM secure ID of the IOMMU instance.
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 1
+
+  '#iommu-cells':
+    const: 1
+
+patternProperties:
+  "^iommu-ctx@[0-9a-f]+$":
+    type: object
+    additionalProperties: false
+    properties:
+      compatible:
+        enum:
+          - qcom,msm-iommu-v1-ns
+          - qcom,msm-iommu-v1-sec
+
+      interrupts:
+        maxItems: 1
+
+      reg:
+        maxItems: 1
+
+    required:
+      - compatible
+      - interrupts
+      - reg
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - ranges
+  - '#address-cells'
+  - '#size-cells'
+  - '#iommu-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-msm8916.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    apps_iommu: iommu@1e20000 {
+      compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
+      reg = <0x01ef0000 0x3000>;
+      clocks = <&gcc GCC_SMMU_CFG_CLK>,
+               <&gcc GCC_APSS_TCU_CLK>;
+      clock-names = "iface", "bus";
+      qcom,iommu-secure-id = <17>;
+      #address-cells = <1>;
+      #size-cells = <1>;
+      #iommu-cells = <1>;
+      ranges = <0 0x01e20000 0x40000>;
+
+      /* mdp_0: */
+      iommu-ctx@4000 {
+        compatible = "qcom,msm-iommu-v1-ns";
+        reg = <0x4000 0x1000>;
+        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+      };
+    };